From patchwork Mon Mar 22 18:54:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 406243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB0ADC433E1 for ; Mon, 22 Mar 2021 18:55:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE82F6199F for ; Mon, 22 Mar 2021 18:55:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230393AbhCVSzK (ORCPT ); Mon, 22 Mar 2021 14:55:10 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:48484 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232137AbhCVSyl (ORCPT ); Mon, 22 Mar 2021 14:54:41 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12MIsY4v041991; Mon, 22 Mar 2021 13:54:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616439274; bh=at9D+epvxqJRiJx1gp7/YbKAENVgMcmU7iiha4Ya0vk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ezqc/ZAU11kro1/0srSglKhoM0/IauBVnB4p/Y9jryRX6pITIyJO86LKAmTvPfWCu Wki0TU6GPx5SaPHWOX97xZggTnhSISz/9pmm5ZEApZoRlnjfjBuz5cHWgIG/A5ULAS z8+mCYf1erpRrSTXj4t3Swko5bIJ5/2u2Ww1uuYc= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12MIsYqA057288 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Mar 2021 13:54:34 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 22 Mar 2021 13:54:34 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 22 Mar 2021 13:54:34 -0500 Received: from lelv0597.itg.ti.com (lelv0597.itg.ti.com [10.181.64.32]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12MIsY4Q059119; Mon, 22 Mar 2021 13:54:34 -0500 Received: from localhost ([10.250.66.107]) by lelv0597.itg.ti.com (8.14.7/8.14.7) with ESMTP id 12MIsYWd019557; Mon, 22 Mar 2021 13:54:34 -0500 From: Suman Anna To: Nishanth Menon , Tero Kristo CC: Gowtham Tammana , , , Suman Anna Subject: [PATCH v2 1/3] arm64: dts: ti: k3-am64-main: Add hwspinlock node Date: Mon, 22 Mar 2021 13:54:28 -0500 Message-ID: <20210322185430.957-2-s-anna@ti.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210322185430.957-1-s-anna@ti.com> References: <20210322185430.957-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AM64x SoC contains a HwSpinlock IP instance that is a minor variant of the IP on existing TI K3 SoCs such as AM65x, J721E or J7200 SoCs. Add the DT node for this on AM64x SoCs. The node is present within the MAIN domain, and is added as a child node under the cbass_main node. Signed-off-by: Suman Anna Reviewed-by: Gowtham Tammana --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index a03b66456062..b34b98969b47 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -563,4 +563,10 @@ ospi0: spi@fc40000 { power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; }; }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; }; From patchwork Mon Mar 22 18:54:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 406242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A49DAC433E3 for ; Mon, 22 Mar 2021 18:55:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5CA98619A1 for ; Mon, 22 Mar 2021 18:55:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232101AbhCVSzL (ORCPT ); Mon, 22 Mar 2021 14:55:11 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35870 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232246AbhCVSyn (ORCPT ); Mon, 22 Mar 2021 14:54:43 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12MIsZCR108101; Mon, 22 Mar 2021 13:54:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616439276; bh=LgnkISi5sP9nD3D55mg+BQJYMT4pSZVW2X270a8GdjE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Cilo3vJ9y7y9B0gxnfQDYjfoBunmE7e7sTlFtGbwNaick59rtPyftfS3hKYwj2bVF TqvFh2anHmPj3iszHAoWavAVYwedpW1mag4rVtiUEw+dPJrx5g+wSirRhR9TaRta/w 86kVoG67DiFnLYNn8RgyPu9DOdt1vG3k0wMlZLqU= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12MIsZ90010993 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Mar 2021 13:54:35 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 22 Mar 2021 13:54:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 22 Mar 2021 13:54:35 -0500 Received: from lelv0597.itg.ti.com (lelv0597.itg.ti.com [10.181.64.32]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12MIsZgE037590; Mon, 22 Mar 2021 13:54:35 -0500 Received: from localhost ([10.250.66.107]) by lelv0597.itg.ti.com (8.14.7/8.14.7) with ESMTP id 12MIsZlJ019565; Mon, 22 Mar 2021 13:54:35 -0500 From: Suman Anna To: Nishanth Menon , Tero Kristo CC: Gowtham Tammana , , , Suman Anna Subject: [PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes Date: Mon, 22 Mar 2021 13:54:30 -0500 Message-ID: <20210322185430.957-4-s-anna@ti.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210322185430.957-1-s-anna@ti.com> References: <20210322185430.957-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the AM64x SoCs for the AM642 EVM and AM642 SK boards. These include the R5F remote processors in the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; and a M4 processor in the MCU safety island. These sub-mailbox nodes utilize the System Mailbox clusters 2, 4 and 6. The remaining clusters 3, 5 and 7 are currently not used, and so are disabled. Clusters 0 and 1 were never added to the dts file as they do not support interrupts towards the A53 core. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The R5F processor sub-systems are assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. Only the sub-mailbox node for the first R5F core in each cluster is used in case of a Single-CPU mode for that R5F cluster. NOTE: The cluster nodes only have the Mailbox IP interrupt outputs that are routed to the GIC_SPI. The sub-mailbox nodes' irq-id are indexing into the listed interrupts, with the usr-id using the actual interrupt output line number from the Mailbox IP. Signed-off-by: Suman Anna Reviewed-by: Gowtham Tammana --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 43 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 43 +++++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 9522f104d979..0ebdd7981853 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -418,3 +418,46 @@ flash@0{ #size-cells = <1>; }; }; + +&mailbox0_cluster2 { + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 3a5bee4b0b0c..5503fc6ddc0d 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -284,3 +284,46 @@ flash@0{ #size-cells = <1>; }; }; + +&mailbox0_cluster2 { + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +&mailbox0_cluster7 { + status = "disabled"; +};