From patchwork Fri May 11 13:06:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 135536 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp849333lji; Fri, 11 May 2018 06:06:32 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrdLpiQ1e+p/uFKb7wgiw+7d+J4dDGCe2w/wMcfgc0CpGZDLANhc57Lu1Ql7okxQNXHfZAP X-Received: by 2002:a65:45c2:: with SMTP id m2-v6mr4411266pgr.433.1526043992735; Fri, 11 May 2018 06:06:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526043992; cv=none; d=google.com; s=arc-20160816; b=HX/rI95vcxEL+BIEE0eP3hSv9GT8mLiQQlB6qfgLv+hwT35UiqPcGPHsXzlqqj04Vj wKx/Wvjopif8GgccO3OghqYlOPjKxLtH1uLfZJdBh2lAA6tm84/+xpfMa+Uz8J8IaVeR 2K+N5jFHb/KYH6aD4sFneFyzw0KeXUwttZliHg5E8BFEuM0/2eD454WvSwVlJ8tJ18Dl GScSDtxENo9vtRo2ntZvEVmI679DXCK+bNccIjDVonJVH/yG+jYjOHoQvRfKBO4L54yX WZaS7AP9p2Sd9BR8Q8EjGc9DV69YB7Gi6hBEV1O556NyNbuKZVFjfB0k83Nc9HYg2Ges LxWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=P8qVn7duv4L+MCy+WDkvvkjLr/mE9ObELlapvfModXY=; b=ACuCJQL4ogutQFHU2NWdzrlJMwS2Xm54qXVQ5sUMsfDUqMohtlFdTmcMDSwNr/uXM+ LsmpBzI48Yk1bk+hoZ2UDs6fmVG5QHGAbwmv9i67TeUghuewgJD/4TsOWpG1yq9hPW2J za1pzaDZrFr74UmaTBm+2bAj3C0FVT8pcWOetLwk9am499Oh2DNiWan1+q/iT3W++0AZ VxdT3G+xN8v5XMrJQ1iUpaVY/ryoe8sAP+WtxdzShFFIRPsNjtMRzfkgsZ8nAdOp1fLR wDLyB0aj/eGHHr6D+zjYf1TKXP+05PrHhocZk38AIUQr3LY2f3V6/s85NoVWutwnUrgC 184w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuJYw2X5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o19-v6si3136165pll.447.2018.05.11.06.06.32; Fri, 11 May 2018 06:06:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuJYw2X5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753100AbeEKNG3 (ORCPT + 29 others); Fri, 11 May 2018 09:06:29 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:35006 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753019AbeEKNG1 (ORCPT ); Fri, 11 May 2018 09:06:27 -0400 Received: by mail-pl0-f67.google.com with SMTP id i5-v6so3284456plt.2 for ; Fri, 11 May 2018 06:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=P8qVn7duv4L+MCy+WDkvvkjLr/mE9ObELlapvfModXY=; b=fuJYw2X5x8+bpc0m+pv3lqku7XidQKgs+Okj8lnwyhKcZHXF39R0ckPla5GDUvVxcO 7e+XhQsYdJf27ETUW6YDp8BtXD9T3e4YXPrFW8nhGsBzofgz4AjaTHBfIJ97htNUtr8g mTALLRMk9POYwRn5NZL5qwX6lb1+vSX5iOuck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=P8qVn7duv4L+MCy+WDkvvkjLr/mE9ObELlapvfModXY=; b=ORev7lBckQLp0gfXUCWZlfxwnPBjNC6VWfYoXHOPgps5KPb60NBvvmID7ev2h6+OHG iA9uF9nTFHT6GLc7FqUGTlQGzlGAEvSNKq9JgHjAQtcNrB2BLBDajqmT+Dm5swGPsPOk XdGm8o5iUax0+XyRnY/7Jr7FQpwti1trLBvbaq2gQ/aQuIgyXV41iuJa2k1jteR1plHD hDHj+ft+6u1vaxbDaZy3OUFJk2o7qpWS5+qRSPJCnAH97Yvxgh1cYj1brG+iRDZLJWv0 afTq3hvRyIEhvYIJEqMGLydIc/oEh2FC3ECQqBOfqQCWFoEnZccAJtm4FwKDUzfhgRc4 huXA== X-Gm-Message-State: ALKqPweewrWEwQDfmppNzIM88IBWf3h2uQ8i52IjOf/y745JXXiWE/iv EgQKURVPZteMPwLHG6CFthaGQA== X-Received: by 2002:a17:902:74c9:: with SMTP id f9-v6mr5514045plt.385.1526043986966; Fri, 11 May 2018 06:06:26 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k13-v6sm8348590pfj.186.2018.05.11.06.06.24 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 May 2018 06:06:26 -0700 (PDT) From: Baolin Wang To: dan.j.williams@intel.com, vkoul@kernel.org Cc: eric.long@spreadtrum.com, broonie@kernel.org, baolin.wang@linaro.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dmaengine: sprd: Optimize the sprd_dma_prep_dma_memcpy() Date: Fri, 11 May 2018 21:06:04 +0800 Message-Id: <08819489e52add194fecf2b4b234fff9deecdb4c.1526043689.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Eric Long This is one preparation patch, we can use default DMA configuration to implement the device_prep_dma_memcpy() interface instead of issuing sprd_dma_config(). We will implement one new sprd_dma_config() function with introducing device_prep_slave_sg() interface in following patch. So we can remove the obsolete sprd_dma_config() firstly. Signed-off-by: Eric Long Signed-off-by: Baolin Wang --- Changes since v2: - Change logic to make code more readable. Changes since v1: - No updates. --- drivers/dma/sprd-dma.c | 167 +++++++++++------------------------------------- 1 file changed, 39 insertions(+), 128 deletions(-) -- 1.7.9.5 diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c index e715d07..924ada4 100644 --- a/drivers/dma/sprd-dma.c +++ b/drivers/dma/sprd-dma.c @@ -552,147 +552,58 @@ static void sprd_dma_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&schan->vc.lock, flags); } -static int sprd_dma_config(struct dma_chan *chan, struct sprd_dma_desc *sdesc, - dma_addr_t dest, dma_addr_t src, size_t len) -{ - struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan); - struct sprd_dma_chn_hw *hw = &sdesc->chn_hw; - u32 datawidth, src_step, des_step, fragment_len; - u32 block_len, req_mode, irq_mode, transcation_len; - u32 fix_mode = 0, fix_en = 0; - - if (IS_ALIGNED(len, 4)) { - datawidth = SPRD_DMA_DATAWIDTH_4_BYTES; - src_step = SPRD_DMA_WORD_STEP; - des_step = SPRD_DMA_WORD_STEP; - } else if (IS_ALIGNED(len, 2)) { - datawidth = SPRD_DMA_DATAWIDTH_2_BYTES; - src_step = SPRD_DMA_SHORT_STEP; - des_step = SPRD_DMA_SHORT_STEP; - } else { - datawidth = SPRD_DMA_DATAWIDTH_1_BYTE; - src_step = SPRD_DMA_BYTE_STEP; - des_step = SPRD_DMA_BYTE_STEP; - } - - fragment_len = SPRD_DMA_MEMCPY_MIN_SIZE; - if (len <= SPRD_DMA_BLK_LEN_MASK) { - block_len = len; - transcation_len = 0; - req_mode = SPRD_DMA_BLK_REQ; - irq_mode = SPRD_DMA_BLK_INT; - } else { - block_len = SPRD_DMA_MEMCPY_MIN_SIZE; - transcation_len = len; - req_mode = SPRD_DMA_TRANS_REQ; - irq_mode = SPRD_DMA_TRANS_INT; - } - - hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET; - hw->wrap_ptr = (u32)((src >> SPRD_DMA_HIGH_ADDR_OFFSET) & - SPRD_DMA_HIGH_ADDR_MASK); - hw->wrap_to = (u32)((dest >> SPRD_DMA_HIGH_ADDR_OFFSET) & - SPRD_DMA_HIGH_ADDR_MASK); - - hw->src_addr = (u32)(src & SPRD_DMA_LOW_ADDR_MASK); - hw->des_addr = (u32)(dest & SPRD_DMA_LOW_ADDR_MASK); - - if ((src_step != 0 && des_step != 0) || (src_step | des_step) == 0) { - fix_en = 0; - } else { - fix_en = 1; - if (src_step) - fix_mode = 1; - else - fix_mode = 0; - } - - hw->frg_len = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET | - datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET | - req_mode << SPRD_DMA_REQ_MODE_OFFSET | - fix_mode << SPRD_DMA_FIX_SEL_OFFSET | - fix_en << SPRD_DMA_FIX_EN_OFFSET | - (fragment_len & SPRD_DMA_FRG_LEN_MASK); - hw->blk_len = block_len & SPRD_DMA_BLK_LEN_MASK; - - hw->intc = SPRD_DMA_CFG_ERR_INT_EN; - - switch (irq_mode) { - case SPRD_DMA_NO_INT: - break; - - case SPRD_DMA_FRAG_INT: - hw->intc |= SPRD_DMA_FRAG_INT_EN; - break; - - case SPRD_DMA_BLK_INT: - hw->intc |= SPRD_DMA_BLK_INT_EN; - break; - - case SPRD_DMA_BLK_FRAG_INT: - hw->intc |= SPRD_DMA_BLK_INT_EN | SPRD_DMA_FRAG_INT_EN; - break; - - case SPRD_DMA_TRANS_INT: - hw->intc |= SPRD_DMA_TRANS_INT_EN; - break; - - case SPRD_DMA_TRANS_FRAG_INT: - hw->intc |= SPRD_DMA_TRANS_INT_EN | SPRD_DMA_FRAG_INT_EN; - break; - - case SPRD_DMA_TRANS_BLK_INT: - hw->intc |= SPRD_DMA_TRANS_INT_EN | SPRD_DMA_BLK_INT_EN; - break; - - case SPRD_DMA_LIST_INT: - hw->intc |= SPRD_DMA_LIST_INT_EN; - break; - - case SPRD_DMA_CFGERR_INT: - hw->intc |= SPRD_DMA_CFG_ERR_INT_EN; - break; - - default: - dev_err(sdev->dma_dev.dev, "invalid irq mode\n"); - return -EINVAL; - } - - if (transcation_len == 0) - hw->trsc_len = block_len & SPRD_DMA_TRSC_LEN_MASK; - else - hw->trsc_len = transcation_len & SPRD_DMA_TRSC_LEN_MASK; - - hw->trsf_step = (des_step & SPRD_DMA_TRSF_STEP_MASK) << - SPRD_DMA_DEST_TRSF_STEP_OFFSET | - (src_step & SPRD_DMA_TRSF_STEP_MASK) << - SPRD_DMA_SRC_TRSF_STEP_OFFSET; - - hw->frg_step = 0; - hw->src_blk_step = 0; - hw->des_blk_step = 0; - hw->src_blk_step = 0; - return 0; -} - static struct dma_async_tx_descriptor * sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); struct sprd_dma_desc *sdesc; - int ret; + struct sprd_dma_chn_hw *hw; + enum sprd_dma_datawidth datawidth; + u32 step, temp; sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); if (!sdesc) return NULL; - ret = sprd_dma_config(chan, sdesc, dest, src, len); - if (ret) { - kfree(sdesc); - return NULL; + hw = &sdesc->chn_hw; + + hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET; + hw->intc = SPRD_DMA_TRANS_INT | SPRD_DMA_CFG_ERR_INT_EN; + hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK; + hw->des_addr = dest & SPRD_DMA_LOW_ADDR_MASK; + hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & + SPRD_DMA_HIGH_ADDR_MASK; + hw->wrap_to = (dest >> SPRD_DMA_HIGH_ADDR_OFFSET) & + SPRD_DMA_HIGH_ADDR_MASK; + + if (IS_ALIGNED(len, 8)) { + datawidth = SPRD_DMA_DATAWIDTH_8_BYTES; + step = SPRD_DMA_DWORD_STEP; + } else if (IS_ALIGNED(len, 4)) { + datawidth = SPRD_DMA_DATAWIDTH_4_BYTES; + step = SPRD_DMA_WORD_STEP; + } else if (IS_ALIGNED(len, 2)) { + datawidth = SPRD_DMA_DATAWIDTH_2_BYTES; + step = SPRD_DMA_SHORT_STEP; + } else { + datawidth = SPRD_DMA_DATAWIDTH_1_BYTE; + step = SPRD_DMA_BYTE_STEP; } + temp = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET; + temp |= datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET; + temp |= SPRD_DMA_TRANS_REQ << SPRD_DMA_REQ_MODE_OFFSET; + temp |= len & SPRD_DMA_FRG_LEN_MASK; + hw->frg_len = temp; + + hw->blk_len = len & SPRD_DMA_BLK_LEN_MASK; + hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK; + + temp = (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET; + temp |= (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET; + hw->trsf_step = temp; + return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); } From patchwork Fri May 11 13:06:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 135537 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp849424lji; Fri, 11 May 2018 06:06:37 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqCcX7QfAOyyrflhMqX8UaEznfj4sYw+59miC+H5SlLnCggd6fcF/AikDQ9IC21lwIof4Ma X-Received: by 2002:a63:3286:: with SMTP id y128-v6mr4535522pgy.419.1526043997561; Fri, 11 May 2018 06:06:37 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id o19-v6si3136165pll.447.2018.05.11.06.06.37; Fri, 11 May 2018 06:06:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RiA33sXc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753140AbeEKNGd (ORCPT + 29 others); Fri, 11 May 2018 09:06:33 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:43763 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753110AbeEKNGa (ORCPT ); Fri, 11 May 2018 09:06:30 -0400 Received: by mail-pl0-f68.google.com with SMTP id a39-v6so3270486pla.10 for ; Fri, 11 May 2018 06:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=qp5Sc/ssRGNURubTAK8nfpnkotaqPUNffrtqXDh9xI0=; b=RiA33sXc8NHqneoOwKeqx0oZJ9n6b4ubMVaxIbzogqe43EWv9DwTPrZeQPr2pf/y90 wisM3oGZgrDNVuDh4Xg4eeijTz4A5fkKZm3G7/SSMowxrZNHSNA+RaDjLNZl3uzpEFZQ 9jYOfd80ySUOTBPUHeqGaYaPP4nRDXJOtS5eQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=qp5Sc/ssRGNURubTAK8nfpnkotaqPUNffrtqXDh9xI0=; b=pzcT8ZX9uFQxevmE6jitrDPia8VWDBYwBcYwR6fxVAqKvFrpBPfMm40YVQrn5L1ouX TaT/mfSGLqKDMhZNcPj5sQ96tEkOmCPXoo/jGuNayCthNqICtt/hGF5UAjj0yp6yFBQD 1vDbuNA5vzQDl5isblOJ0JhOvKLJHdjfNLywM5GTNiKI9OJSnOOjwQoG8Y0MGJyeiep1 urucFI9urr74ujA5s+1owoK07G2B0LTXg89o8av+9SDzTalYaAmgSX2IIMsicK9HqveU 5V/9i9Q4ifWSNjYyK19pUXhGQ6GjU5RAcvIAJFjs5rh68IIqS9MxWUxt9Bzd4oagpED+ UFlg== X-Gm-Message-State: ALKqPwfWVBXzcdwrk7dXD6IUNKrEjjw2PUDgjmAvy43ya9+Vvu9o+uud HYCiD8wy+iVdcSHjYNo5ZTx4+A== X-Received: by 2002:a17:902:7b83:: with SMTP id w3-v6mr5593267pll.12.1526043989536; Fri, 11 May 2018 06:06:29 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k13-v6sm8348590pfj.186.2018.05.11.06.06.27 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 May 2018 06:06:28 -0700 (PDT) From: Baolin Wang To: dan.j.williams@intel.com, vkoul@kernel.org Cc: eric.long@spreadtrum.com, broonie@kernel.org, baolin.wang@linaro.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] dmaengine: sprd: Add Spreadtrum DMA configuration Date: Fri, 11 May 2018 21:06:05 +0800 Message-Id: <85413038c111c58747194dd5736834be9adb0f20.1526043689.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <08819489e52add194fecf2b4b234fff9deecdb4c.1526043689.git.baolin.wang@linaro.org> References: <08819489e52add194fecf2b4b234fff9deecdb4c.1526043689.git.baolin.wang@linaro.org> In-Reply-To: <08819489e52add194fecf2b4b234fff9deecdb4c.1526043689.git.baolin.wang@linaro.org> References: <08819489e52add194fecf2b4b234fff9deecdb4c.1526043689.git.baolin.wang@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Eric Long This patch adds the 'device_config' and 'device_prep_slave_sg' interfaces for users to configure DMA, as well as adding one 'struct sprd_dma_config' structure to save Spreadtrum DMA configuration for each DMA channel. Signed-off-by: Eric Long Signed-off-by: Baolin Wang --- Changes since v2: - Remove src/dst from struct sprd_dma_config. - Simplify sprd_dma_get_datawidth()/sprd_dma_get_step(). - Change some logic to make code more readable. - Other optimization. Changes since v1: - Fix the incorrect parameter type of sprd_dma_get_step(). --- drivers/dma/sprd-dma.c | 213 ++++++++++++++++++++++++++++++++++++++++++ include/linux/dma/sprd-dma.h | 4 + 2 files changed, 217 insertions(+) -- 1.7.9.5 diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c index 924ada4..00fcec4 100644 --- a/drivers/dma/sprd-dma.c +++ b/drivers/dma/sprd-dma.c @@ -100,6 +100,8 @@ #define SPRD_DMA_DES_DATAWIDTH_OFFSET 28 #define SPRD_DMA_SWT_MODE_OFFSET 26 #define SPRD_DMA_REQ_MODE_OFFSET 24 +#define SPRD_DMA_WRAP_SEL_OFFSET 23 +#define SPRD_DMA_WRAP_EN_OFFSET 22 #define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0) #define SPRD_DMA_FIX_SEL_OFFSET 21 #define SPRD_DMA_FIX_EN_OFFSET 20 @@ -154,6 +156,31 @@ struct sprd_dma_chn_hw { u32 des_blk_step; }; +/* + * struct sprd_dma_config - DMA configuration structure + * @cfg: dma slave channel runtime config + * @block_len: specify one block transfer length + * @transcation_len: specify one transcation transfer length + * @src_step: source transfer step + * @dst_step: destination transfer step + * @wrap_ptr: wrap pointer address, once the transfer address reaches the + * 'wrap_ptr', the next transfer address will jump to the 'wrap_to' address. + * @wrap_to: wrap jump to address + * @req_mode: specify the DMA request mode + * @int_mode: specify the DMA interrupt type + */ +struct sprd_dma_config { + struct dma_slave_config cfg; + u32 block_len; + u32 transcation_len; + u32 src_step; + u32 dst_step; + phys_addr_t wrap_ptr; + phys_addr_t wrap_to; + enum sprd_dma_req_mode req_mode; + enum sprd_dma_int_type int_mode; +}; + /* dma request description */ struct sprd_dma_desc { struct virt_dma_desc vd; @@ -164,6 +191,7 @@ struct sprd_dma_desc { struct sprd_dma_chn { struct virt_dma_chan vc; void __iomem *chn_base; + struct sprd_dma_config slave_cfg; u32 chn_num; u32 dev_id; struct sprd_dma_desc *cur_desc; @@ -552,6 +580,113 @@ static void sprd_dma_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&schan->vc.lock, flags); } +static enum sprd_dma_datawidth +sprd_dma_get_datawidth(enum dma_slave_buswidth buswidth) +{ + switch (buswidth) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + case DMA_SLAVE_BUSWIDTH_2_BYTES: + case DMA_SLAVE_BUSWIDTH_4_BYTES: + case DMA_SLAVE_BUSWIDTH_8_BYTES: + return ffs(buswidth) - 1; + default: + return SPRD_DMA_DATAWIDTH_4_BYTES; + } +} + +static u32 sprd_dma_get_step(enum dma_slave_buswidth buswidth) +{ + switch (buswidth) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + case DMA_SLAVE_BUSWIDTH_2_BYTES: + case DMA_SLAVE_BUSWIDTH_4_BYTES: + case DMA_SLAVE_BUSWIDTH_8_BYTES: + return buswidth; + + default: + return SPRD_DMA_DWORD_STEP; + } +} + +static int sprd_dma_config(struct dma_chan *chan, struct sprd_dma_desc *sdesc, + dma_addr_t src, dma_addr_t dst, + struct sprd_dma_config *slave_cfg) +{ + struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan); + struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); + struct sprd_dma_chn_hw *hw = &sdesc->chn_hw; + u32 fix_mode = 0, fix_en = 0, wrap_en = 0, wrap_mode = 0; + u32 src_datawidth, dst_datawidth, temp; + + if (slave_cfg->cfg.slave_id) + schan->dev_id = slave_cfg->cfg.slave_id; + + hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET; + + temp = slave_cfg->wrap_ptr & SPRD_DMA_LOW_ADDR_MASK; + temp |= (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK; + hw->wrap_ptr = temp; + + temp = slave_cfg->wrap_to & SPRD_DMA_LOW_ADDR_MASK; + temp |= (dst >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK; + hw->wrap_to = temp; + + hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK; + hw->des_addr = dst & SPRD_DMA_LOW_ADDR_MASK; + + if ((slave_cfg->src_step != 0 && slave_cfg->dst_step != 0) + || (slave_cfg->src_step | slave_cfg->dst_step) == 0) { + fix_en = 0; + } else { + fix_en = 1; + if (slave_cfg->src_step) + fix_mode = 1; + else + fix_mode = 0; + } + + if (slave_cfg->wrap_ptr && slave_cfg->wrap_to) { + wrap_en = 1; + if (slave_cfg->wrap_to == src) { + wrap_mode = 0; + } else if (slave_cfg->wrap_to == dst) { + wrap_mode = 1; + } else { + dev_err(sdev->dma_dev.dev, "invalid wrap mode\n"); + return -EINVAL; + } + } + + hw->intc = slave_cfg->int_mode | SPRD_DMA_CFG_ERR_INT_EN; + + src_datawidth = sprd_dma_get_datawidth(slave_cfg->cfg.src_addr_width); + dst_datawidth = sprd_dma_get_datawidth(slave_cfg->cfg.dst_addr_width); + + temp = src_datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET; + temp |= dst_datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET; + temp |= slave_cfg->req_mode << SPRD_DMA_REQ_MODE_OFFSET; + temp |= wrap_mode << SPRD_DMA_WRAP_SEL_OFFSET; + temp |= wrap_en << SPRD_DMA_WRAP_EN_OFFSET; + temp |= fix_mode << SPRD_DMA_FIX_SEL_OFFSET; + temp |= fix_en << SPRD_DMA_FIX_EN_OFFSET; + temp |= slave_cfg->cfg.src_maxburst & SPRD_DMA_FRG_LEN_MASK; + hw->frg_len = temp; + + hw->blk_len = slave_cfg->block_len & SPRD_DMA_BLK_LEN_MASK; + hw->trsc_len = slave_cfg->transcation_len & SPRD_DMA_TRSC_LEN_MASK; + + temp = (slave_cfg->dst_step & SPRD_DMA_TRSF_STEP_MASK) << + SPRD_DMA_DEST_TRSF_STEP_OFFSET; + temp |= (slave_cfg->src_step & SPRD_DMA_TRSF_STEP_MASK) << + SPRD_DMA_SRC_TRSF_STEP_OFFSET; + hw->trsf_step = temp; + + hw->frg_step = 0; + hw->src_blk_step = 0; + hw->des_blk_step = 0; + return 0; +} + static struct dma_async_tx_descriptor * sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) @@ -607,6 +742,82 @@ static void sprd_dma_issue_pending(struct dma_chan *chan) return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); } +static void sprd_dma_fill_config(struct sprd_dma_config *slave_cfg, + u32 src_step, u32 dst_step, u32 len, + unsigned long flags) +{ + slave_cfg->src_step = src_step; + slave_cfg->dst_step = dst_step; + slave_cfg->block_len = len; + slave_cfg->transcation_len = len; + slave_cfg->req_mode = + (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK; + slave_cfg->int_mode = flags & SPRD_DMA_INT_MASK; +} + +static struct dma_async_tx_descriptor * +sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sglen, enum dma_transfer_direction dir, + unsigned long flags, void *context) +{ + struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); + struct sprd_dma_config *slave_cfg = &schan->slave_cfg; + u32 src_step = 0, dst_step = 0, len = 0; + dma_addr_t src = 0, dst = 0; + struct sprd_dma_desc *sdesc; + struct scatterlist *sg; + int ret, i; + + /* TODO: now we only support one sg for each DMA configuration. */ + if (!is_slave_direction(dir) || sglen > 1) + return NULL; + + sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); + if (!sdesc) + return NULL; + + for_each_sg(sgl, sg, sglen, i) { + len = sg_dma_len(sg); + + if (dir == DMA_MEM_TO_DEV) { + src = sg_dma_address(sg); + dst = slave_cfg->cfg.dst_addr; + src_step = sprd_dma_get_step(slave_cfg->cfg.src_addr_width); + dst_step = SPRD_DMA_NONE_STEP; + } else { + src = slave_cfg->cfg.src_addr; + dst = sg_dma_address(sg); + src_step = SPRD_DMA_NONE_STEP; + dst_step = sprd_dma_get_step(slave_cfg->cfg.dst_addr_width); + } + } + + sprd_dma_fill_config(slave_cfg, src_step, dst_step, len, flags); + + ret = sprd_dma_config(chan, sdesc, src, dst, slave_cfg); + if (ret) { + kfree(sdesc); + return NULL; + } + + return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); +} + +static int sprd_dma_slave_config(struct dma_chan *chan, + struct dma_slave_config *config) +{ + struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); + struct sprd_dma_config *slave_cfg = &schan->slave_cfg; + + if (!is_slave_direction(config->direction)) + return -EINVAL; + + memset(slave_cfg, 0, sizeof(*slave_cfg)); + memcpy(&slave_cfg->cfg, config, sizeof(*config)); + + return 0; +} + static int sprd_dma_pause(struct dma_chan *chan) { struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); @@ -733,6 +944,8 @@ static int sprd_dma_probe(struct platform_device *pdev) sdev->dma_dev.device_tx_status = sprd_dma_tx_status; sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending; sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy; + sdev->dma_dev.device_prep_slave_sg = sprd_dma_prep_slave_sg; + sdev->dma_dev.device_config = sprd_dma_slave_config; sdev->dma_dev.device_pause = sprd_dma_pause; sdev->dma_dev.device_resume = sprd_dma_resume; sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all; diff --git a/include/linux/dma/sprd-dma.h b/include/linux/dma/sprd-dma.h index c545162..b0115e3 100644 --- a/include/linux/dma/sprd-dma.h +++ b/include/linux/dma/sprd-dma.h @@ -3,6 +3,10 @@ #ifndef _SPRD_DMA_H_ #define _SPRD_DMA_H_ +#define SPRD_DMA_REQ_SHIFT 16 +#define SPRD_DMA_FLAGS(req_mode, int_type) \ + ((req_mode) << SPRD_DMA_REQ_SHIFT | (int_type)) + /* * enum sprd_dma_req_mode: define the DMA request mode * @SPRD_DMA_FRAG_REQ: fragment request mode