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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:44 -0700 Message-Id: <20180511024454.31679-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 01/11] target/arm: Implement FMOV (general) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b0471c842e..10d3856351 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5700,6 +5700,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); clear_vec_high(s, true, rd); break; + case 3: + /* 16 bit */ + tmp = tcg_temp_new_i64(); + tcg_gen_ext16u_i64(tmp, tcg_rn); + write_fp_dreg(s, rd, tmp); + tcg_temp_free_i64(tmp); + break; + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_rd = cpu_reg(s, rd); @@ -5717,6 +5726,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) /* 64 bits from top half */ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); break; + case 3: + /* 16 bit */ + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); + break; + default: + g_assert_not_reached(); } } } @@ -5756,6 +5771,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) case 0xa: /* 64 bit */ case 0xd: /* 64 bit to top half of quad */ break; + case 0x6: /* 16-bit float, 32-bit int */ + case 0xe: /* 16-bit float, 64-bit int */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ default: /* all other sf/type/rmode combinations are invalid */ unallocated_encoding(s); From patchwork Fri May 11 02:44:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135473 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp328807lji; Thu, 10 May 2018 19:51:09 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqVs2+saF5wakmnx4OsJMxRPohP+4vt5wogpsoLmMkFUItnKZnfDbqwIIB+0THssLFwEbd5 X-Received: by 2002:a37:2a6a:: with SMTP id q103-v6mr3449769qkh.245.1526007069556; Thu, 10 May 2018 19:51:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526007069; cv=none; d=google.com; s=arc-20160816; b=q2M93GwJxMoier9ITegnWchMcE4uQhLhNK+Do+DimaFEu/aN/5K5aDSbHCMFH3Bs2b A4c+sBakgqKPKpwjZ/5eR3H3D1fn+5m7+xSeeyvqUrMwTaXmbB8Ku4hiJOFXrDtMwFxC C7HQ8Sxr4NnMwQkoWz/lOQfl7tT5STG5+KdK0pc0IbsCWCqNvUyTFQnyeRiF9sIWoCbK aKKNDKVUyezUtCNL0eDWB0HjgNgjWQMqXbXzdUc+4GrHK2emfMdfNRYOTxf2cD0B0azF C8V6yJyxvYdXaSZP59iUyrFOxZS4i9LWijPN6RykF+pWai0gKnFwrm88tvyqXre2qEuz 97dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=I3PSoTtMStTJ7R72mjpDN+LuXGvjQpqcgD+JZkivJBk=; b=1BBZevCsAG3x5Oxwm3Nj6roIxROXhQv/qGP+lFOMe8+ljM3jSLLrWWarW7wZ7q8zb5 eHsVyHeCJ7q5xz3qpzsc+1z4B6DhWTMypMDKHiHncU4xSoSa8hCUdHIzQe+m9K3UOG2H hGMoO1VXqlmxSKA0ywGStA+yQDrgl89dnXBf91hnUojwTaEHj148mjSe0TsKj0ZA5pp3 jkhA0EHYip0AVhlrdWvXxFffcn7fYvB8HKk4Dn4hFKen44kQP5VeloEMeOyX9aCeHMaI lN1Jf6/3k+eC1O9w170KFk8K4qNaZk24hGg3P6+VE3kBeurK3JWgGiXoSJuJa9C+Tyuv gfAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MwzUKz5+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:45 -0700 Message-Id: <20180511024454.31679-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 02/11] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No sense in emitting code after the exception. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 10d3856351..edb4dc243f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5780,7 +5780,7 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) default: /* all other sf/type/rmode combinations are invalid */ unallocated_encoding(s); - break; + return; } if (!fp_access_check(s)) { From patchwork Fri May 11 02:44:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135472 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp328566lji; Thu, 10 May 2018 19:50:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoMQ09VfJ6qUrzrknBWxU5er5jy8VtqzXXeiavZWLxMA1GrUoba451CkHrWovnlyxBgV1S4 X-Received: by 2002:ac8:35e9:: with SMTP id l38-v6mr3752603qtb.290.1526007048720; Thu, 10 May 2018 19:50:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526007048; cv=none; d=google.com; s=arc-20160816; b=nMqsjyzLKyS/KtO4HFeVVtsWPr3bKzmbwhP5sgPHHQGiqX62siWMwRwj4e5YVYwyNg eiWEDthGwV5/5zLIGcx6q6xgqZynzCdWpJK5a9EZIPy5dZg3bcWDIiairmAZ+4vX58FI 7RIOgSbBE6ljgZiTKEzo41HwwsKa4dTQkcNDTRDTVGma8MrD2EyWafsrmDTCBy6jN2Sx LRWvh1JZYqKihCa/oLrbRV2b/5OaK8lwFBWDP9XADLt8PwcD3MWqiFk6EzTE4AzLwPq5 R2kVgVk1yaux9q5y1lwarNlBUq023Ju3RQoefq2/r6ZzkCBJ1Bo2BdfdLWSRHv1uQxtv 4dLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QT8ASjtS0LVDIt3nPzO8APmyPfiEdpd8UtM1B4qiCmY=; b=0ZZDp62eb5fRbJB7aWhwqOVME9Ib33enZDbusvTUW0DoD2dwOs5bI8peoi74yk7pPz RwDw/2CumuMC8d6wPNdvLb8vOCeeqRl4cMXIWGJxAJIetf74tv6Q71GsXHPtUb6H7S9T /mCl2uXcdKKvTAF9ub0xjaJPzpx5CcJAO3AIHlinLzSFiCJVq866XmV8Ku3OEr6Ee+Go 9L9rY+gEFL0fheXR5s3+Wq0dAPNKrRuH8PQDkNCDe5QJmxnqVK3ZsYrj69Vl0JjR/HVv JHPAXMGK+I46hNcfyYoOmR6XRUkII29rxqb0SThols5u/hBsZdP/PWukfOzALKPmZ0mL fkfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WCHHqfiQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:46 -0700 Message-Id: <20180511024454.31679-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 03/11] target/arm: Implement FCVT (scalar, integer) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 +++ target/arm/helper.c | 38 ++++++++++++++- target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++------- 3 files changed, 122 insertions(+), 18 deletions(-) -- 2.17.0 diff --git a/target/arm/helper.h b/target/arm/helper.h index 1969b37f2d..ce89968b2d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -151,6 +151,10 @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) @@ -177,6 +181,8 @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) diff --git a/target/arm/helper.c b/target/arm/helper.c index 817f9d81a0..c6fd7f9479 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11427,8 +11427,12 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) #undef VFP_CONV_FIX_A64 /* Conversion to/from f16 can overflow to infinity before/after scaling. - * Therefore we convert to f64 (which does not round), scale, - * and then convert f64 to f16 (which may round). + * Therefore we convert to f64, scale, and then convert f64 to f16; or + * vice versa for conversion to integer. + * + * For 16- and 32-bit integers, the conversion to f64 never rounds. + * For 64-bit integers, any integer that would cause rounding will also + * overflow to f16 infinity, so there is no double rounding problem. */ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst) @@ -11446,6 +11450,16 @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst); } +float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst); +} + +float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst); +} + static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst) { if (unlikely(float16_is_any_nan(f))) { @@ -11475,6 +11489,26 @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst) return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst); } +uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst); +} + /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index edb4dc243f..14f35e878a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5511,11 +5511,11 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, bool itof, int rmode, int scale, int sf, int type) { bool is_signed = !(opcode & 1); - bool is_double = type; TCGv_ptr tcg_fpstatus; - TCGv_i32 tcg_shift; + TCGv_i32 tcg_shift, tcg_single; + TCGv_i64 tcg_double; - tcg_fpstatus = get_fpstatus_ptr(false); + tcg_fpstatus = get_fpstatus_ptr(type == 3); tcg_shift = tcg_const_i32(64 - scale); @@ -5533,8 +5533,9 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_int = tcg_extend; } - if (is_double) { - TCGv_i64 tcg_double = tcg_temp_new_i64(); + switch (type) { + case 1: /* float64 */ + tcg_double = tcg_temp_new_i64(); if (is_signed) { gen_helper_vfp_sqtod(tcg_double, tcg_int, tcg_shift, tcg_fpstatus); @@ -5544,8 +5545,10 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, } write_fp_dreg(s, rd, tcg_double); tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single = tcg_temp_new_i32(); + break; + + case 0: /* float32 */ + tcg_single = tcg_temp_new_i32(); if (is_signed) { gen_helper_vfp_sqtos(tcg_single, tcg_int, tcg_shift, tcg_fpstatus); @@ -5555,6 +5558,23 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, } write_fp_sreg(s, rd, tcg_single); tcg_temp_free_i32(tcg_single); + break; + + case 3: /* float16 */ + tcg_single = tcg_temp_new_i32(); + if (is_signed) { + gen_helper_vfp_sqtoh(tcg_single, tcg_int, + tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_uqtoh(tcg_single, tcg_int, + tcg_shift, tcg_fpstatus); + } + write_fp_sreg(s, rd, tcg_single); + tcg_temp_free_i32(tcg_single); + break; + + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_int = cpu_reg(s, rd); @@ -5571,8 +5591,9 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - if (is_double) { - TCGv_i64 tcg_double = read_fp_dreg(s, rn); + switch (type) { + case 1: /* float64 */ + tcg_double = read_fp_dreg(s, rn); if (is_signed) { if (!sf) { gen_helper_vfp_tosld(tcg_int, tcg_double, @@ -5590,9 +5611,14 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_shift, tcg_fpstatus); } } + if (!sf) { + tcg_gen_ext32u_i64(tcg_int, tcg_int); + } tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single = read_fp_sreg(s, rn); + break; + + case 0: /* float32 */ + tcg_single = read_fp_sreg(s, rn); if (sf) { if (is_signed) { gen_helper_vfp_tosqs(tcg_int, tcg_single, @@ -5614,14 +5640,39 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_temp_free_i32(tcg_dest); } tcg_temp_free_i32(tcg_single); + break; + + case 3: /* float16 */ + tcg_single = read_fp_sreg(s, rn); + if (sf) { + if (is_signed) { + gen_helper_vfp_tosqh(tcg_int, tcg_single, + tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_touqh(tcg_int, tcg_single, + tcg_shift, tcg_fpstatus); + } + } else { + TCGv_i32 tcg_dest = tcg_temp_new_i32(); + if (is_signed) { + gen_helper_vfp_toslh(tcg_dest, tcg_single, + tcg_shift, tcg_fpstatus); + } else { + gen_helper_vfp_toulh(tcg_dest, tcg_single, + tcg_shift, tcg_fpstatus); + } + tcg_gen_extu_i32_i64(tcg_int, tcg_dest); + tcg_temp_free_i32(tcg_dest); + } + tcg_temp_free_i32(tcg_single); + break; + + default: + g_assert_not_reached(); } gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); - - if (!sf) { - tcg_gen_ext32u_i64(tcg_int, tcg_int); - } } tcg_temp_free_ptr(tcg_fpstatus); @@ -5791,7 +5842,20 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) /* actual FP conversions */ bool itof = extract32(opcode, 1, 1); - if (type > 1 || (rmode != 0 && opcode > 1)) { + if (rmode != 0 && opcode > 1) { + unallocated_encoding(s); + return; + } + switch (type) { + case 0: /* float32 */ + case 1: /* float64 */ + break; + case 3: /* float16 */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } From patchwork Fri May 11 02:44:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135470 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp327457lji; Thu, 10 May 2018 19:49:12 -0700 (PDT) X-Google-Smtp-Source: AB8JxZolZ8829JrCFrOQQPdkckJFUXqFf7XfQHkckhfj1Jmw7TrTmNVUAD6diTAbjQQ6W06Kp7iI X-Received: by 2002:a0c:923b:: with SMTP id a56-v6mr3569488qva.248.1526006952300; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:47 -0700 Message-Id: <20180511024454.31679-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 04/11] target/arm: Implement FCVT (scalar, fixed-point) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 14f35e878a..eb69a548e1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5491,6 +5491,20 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) return; } + switch (type) { + case 0: /* float32 */ + case 1: /* float64 */ + break; + case 3: /* float16 */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { return; } @@ -5697,8 +5711,7 @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) bool sf = extract32(insn, 31, 1); bool itof; - if (sbit || (type > 1) - || (!sf && scale < 32)) { + if (sbit || (!sf && scale < 32)) { unallocated_encoding(s); return; } From patchwork Fri May 11 02:44:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135469 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp327447lji; Thu, 10 May 2018 19:49:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZopf0bj2cuoOGi2I9LRbJK/gorV2eOg0G2kzRCxHbKPKb7ZCOBHfy1bus387rbqD5mFhHx5 X-Received: by 2002:a0c:c602:: with SMTP id v2-v6mr3602619qvi.11.1526006951678; Thu, 10 May 2018 19:49:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526006951; cv=none; d=google.com; s=arc-20160816; b=t9jToYOkq4+qMFgz+jBOmUsKr31Cx7aOJfafxn26d+1IeLBSS86BsuVVDjEzlDgkFp JkWhWVG9HctMfWkInpHSKVih6zlPAMhloWBTMuspol4nDqXYCNnKoZhNcpJKuNnw/2xN qhmBcZxvBTA1aIdaQJJplZxWSsSSWln7lFhWqChvYuyt7i9SRjyYj0tJYpeWihuFr64p 1u9lEhnAalG+HnzBbFXFc3fVgavd9MJBJQGzV0JKNBM4qdNl2+OsJtfd9qIwiHVfPJUF 96zltcz2WdulCEcBTRRqCVOscmS1Slomc/ABfGAzrngmvRpV3nH8k7Ep/lBB29bayDVI 2Mpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uR2Q5iEyxGiWW0TsSf+fLL7yus1zRFGEpIBJL3HBzdQ=; b=fzvx/d4+6KnEX61JcQWVW9WZuJcYGbTbNEgbIpw1ubRfLFMveZqP2i3qfhutcLy+jE SBz7GKvxky3XzfEZ9nGkHVQSd1ZBFG1Q8VI1XCeHvoW8TbBWjm4ZZxWOsWDaf8k/PSU7 VphyNZch56j7YXo8wudnLtA92supozMW+QFoRqqF9RLoPZ+hK6fVo2QYriCHRK67p5lj p5efSHBVl1+aODKHG3cDuu+sk5ZIuIi0hWcbGD/0l1yDdalG+3J+e9Oaq6IxzCWhCpPn 5tCvWSLeKurcdT0dHnYTMATZsIe1fEwWTB96M0HsGSHSDySPw6+Gah/5XKYuSyd00aOt /3NQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PD4zimq1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:48 -0700 Message-Id: <20180511024454.31679-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 05/11] target/arm: Introduce and use read_fp_hreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eb69a548e1..031213bb06 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -615,6 +615,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) +{ + TCGv_i32 v = tcg_temp_new_i32(); + + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + return v; +} + /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). * If SVE is not enabled, then there are only 128 bits in the vector. */ @@ -4881,11 +4889,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) { TCGv_ptr fpst = NULL; - TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_op = read_fp_hreg(s, rn); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (opcode) { case 0x0: /* FMOV */ tcg_gen_mov_i32(tcg_res, tcg_op); @@ -7784,13 +7790,10 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_op2); tcg_temp_free_i64(tcg_res); } else { - TCGv_i32 tcg_op1 = tcg_temp_new_i32(); - TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); + TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); TCGv_i64 tcg_res = tcg_temp_new_i64(); - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); @@ -8331,13 +8334,10 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, fpst = get_fpstatus_ptr(true); - tcg_op1 = tcg_temp_new_i32(); - tcg_op2 = tcg_temp_new_i32(); + tcg_op1 = read_fp_hreg(s, rn); + tcg_op2 = read_fp_hreg(s, rm); tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - switch (fpopcode) { case 0x03: /* FMULX */ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); @@ -12235,11 +12235,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) } if (is_scalar) { - TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_op = read_fp_hreg(s, rn); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (fpop) { case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ From patchwork Fri May 11 02:44:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135471 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp327721lji; Thu, 10 May 2018 19:49:38 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqDgaAw2p90JYiMrdP8CIbhLKZRrAuxNL4pSR436WBIW7HAHUvZEXfhc1PjrpkQiAPpQNND X-Received: by 2002:ac8:6753:: with SMTP id n19-v6mr3785398qtp.68.1526006978193; Thu, 10 May 2018 19:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526006978; cv=none; d=google.com; s=arc-20160816; b=cuFSur/f7oYBbdXEFL+3E4xn7s0bOkXiI6mcjlLBgb51X6sFu1Tc15Edb2TeWBN2B2 gJd4ilgqgQYVq4yskpgYOFWad6gJmha39yK/0rD/y0gv/Iy6EPgaGhZ272UZaFL/bMfI +chkKozlmKevvErm/Zy0gfz1e9xCjRPdr88HjeW8d/EfffYqvJUrPZceUjyAAYx5SJm/ 1e9RmFWGERvLEDCYDofE9Y2nFHKf4RprUCNPJ+pNPAexlpdxUQzOe0nBh4Lhp7pduhvx diXR1C/4ktHSkus9tEYLvEzlbGZ8OzNZ3VjF7rWvKHxaHJ/jAKjAYB0hRgfS2u7Loq9m j6Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7MNyMFHvx58ZXGFdXLFB2Vf0VyV5CoW7cXdjX/jA+Sw=; b=WSdZLn9jUUeCII6cqiIq1lM3QtKX6/I1IoJMMmoxcMXAlPi/R9XsfgoR9Bl4KxDfBV VoHIqa6/7b9rx1iEa7TbujcnWgbz9EcGa3sVuaAOTpW7UtYqYDpkBo0Bf8W93FgbMfxD vpbARhEOi87hWNL3U1wexb+zzyr+ZsH8whmVrYPx3BZ4bPEtaFwSbl+00gldMq0VcDR/ 0wjb4j4oVvNpXlmZVUlfDBaQIoA57Wwrt7LrCUAsi1EtryDcNKrvD2o+9wQHwKkHrpuU t1g+Tt4t8a37J/IZicq3ql3pm1f4hbudEB+aZw0afBw+zFhZwvbacR2NBLgq8UNJzrza 5vGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vz5TkaQv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:49 -0700 Message-Id: <20180511024454.31679-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 06/11] target/arm: Implement FP data-processing (2 source) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We missed all of the scalar fp16 binary operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 031213bb06..1264e798a7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5299,6 +5299,61 @@ static void handle_fp_2src_double(DisasContext *s, int opcode, tcg_temp_free_i64(tcg_res); } +/* Floating-point data-processing (2 source) - half precision */ +static void handle_fp_2src_half(DisasContext *s, int opcode, + int rd, int rn, int rm) +{ + TCGv_i32 tcg_op1; + TCGv_i32 tcg_op2; + TCGv_i32 tcg_res; + TCGv_ptr fpst; + + tcg_res = tcg_temp_new_i32(); + fpst = get_fpstatus_ptr(true); + tcg_op1 = read_fp_hreg(s, rn); + tcg_op2 = read_fp_hreg(s, rm); + + switch (opcode) { + case 0x0: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x3: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x4: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x5: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x7: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FNMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); + break; + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_res); +} + /* Floating point data-processing (2 source) * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -5331,6 +5386,16 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn) } handle_fp_2src_double(s, opcode, rd, rn, rm); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + handle_fp_2src_half(s, opcode, rd, rn, rm); + break; default: unallocated_encoding(s); } From patchwork Fri May 11 02:44:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135468 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp325581lji; Thu, 10 May 2018 19:46:19 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqguewga51HN/qEiO1pQocuEEb4nTHHl9L2IRpLAK+zPVfmKhhiA3M6PYMsZW1LvYDX+1Yv X-Received: by 2002:a37:9342:: with SMTP id v63-v6mr3663836qkd.40.1526006779595; Thu, 10 May 2018 19:46:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526006779; cv=none; d=google.com; s=arc-20160816; b=ZFwtNBMOeaDVgKI2a+d3mXwrOPeka7p/LzwDPYA2cIyLCdkG044ucekocBUF52wvhG rMsrI1YE0QH0t9OsixJMc/ENdrM3Ws3osswJjjgf8draQIY26A4fvnxTJePwXl476fG3 dxMFAWYy1/Ch4l+7fHwhaLuUQCAQV7dMzNkg3n+S+08FCt/9XzcFy4H+gM15cxK+l9av h3UZyu72Iy5xI+0fWsVq5XYsnqV+y3i74EYIwPhfKvb4Da5bAyvqIgzd6ijNneznmOrO t549VtikLswDRhBRBlTZGBxZq+yRmrKDJEh/hx70yYAhUy5rTakT369/buFYCqGmMB3C giMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=syQxlWTmbSK8Q3TAku1LWmkyym/aXYqXxRnVattmjbE=; b=Nxhu0yxPjsjL4QUwGkd0wSm8oybZP5qDphsitBKbRdBH0FSiLZfyqn5kwGXhPnhOeE HoxIKADz2kCcJ4nIqlDpyeENu9PfRkUHL7EJ+WDlJqvgGU2dyyBS0GGK07MXWRo2vPgx aGW8/u2r5N3fz78VOo6gyEAmoJMJ8YjYBJG1SX1OGyfnSCXpNh+D3fegj7yDeTPjBBI/ 9VUWtNwW+z5TVwnkQIcMJnxxJ8KnoNNtutFKKZn8xHEcKz4YhgQn4HLFm/MwauEBDEnS YFxCcear+8Rj3W+QJC6PAFMbaUa4Ar5hJ0XoVgBrNLgsg7Zw1H+W+y17Nx/NUoNsTJ/e HWeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dRKiyUiy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:50 -0700 Message-Id: <20180511024454.31679-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v3 07/11] target/arm: Implement FP data-processing (3 source) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We missed all of the scalar fp16 fma operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1264e798a7..523fcf4801 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5477,6 +5477,44 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, tcg_temp_free_i64(tcg_res); } +/* Floating-point data-processing (3 source) - half precision */ +static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, + int rd, int rn, int rm, int ra) +{ + TCGv_i32 tcg_op1, tcg_op2, tcg_op3; + TCGv_i32 tcg_res = tcg_temp_new_i32(); + TCGv_ptr fpst = get_fpstatus_ptr(true); + + tcg_op1 = read_fp_hreg(s, rn); + tcg_op2 = read_fp_hreg(s, rm); + tcg_op3 = read_fp_hreg(s, ra); + + /* These are fused multiply-add, and must be done as one + * floating point operation with no rounding between the + * multiplication and addition steps. + * NB that doing the negations here as separate steps is + * correct : an input NaN should come out with its sign bit + * flipped if it is a negated-input. + */ + if (o1 == true) { + tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); + } + + if (o0 != o1) { + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); + } + + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); + + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_i32(tcg_op3); + tcg_temp_free_i32(tcg_res); +} + /* Floating point data-processing (3 source) * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 * +---+---+---+-----------+------+----+------+----+------+------+------+ @@ -5506,6 +5544,16 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) } handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); + break; default: unallocated_encoding(s); } From patchwork Fri May 11 02:44:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135474 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp329588lji; Thu, 10 May 2018 19:52:24 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoYNZ9XNmvJH3bGgb16yX1k/L5TplVv0QiPNoboZCjPlRDJB0l1PS+8jSPVYGOT4R6nqi8N X-Received: by 2002:a0c:946c:: with SMTP id i41-v6mr3636823qvi.139.1526007144287; Thu, 10 May 2018 19:52:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526007144; cv=none; d=google.com; s=arc-20160816; b=NJs18UNiKvcvEtflLplmEla8Vfe1n67CATZp9yhaq1ixLq1x10750i/1nvcu+FAZdE LuJ/sELuTIuLC3Ztw2Th3KrJlRFgyORdxL2pVj5uXK1DuM1q50DLcvF/fle0Te01TlI9 RfRwazt4Sn88aq87PK6jthAaHjIR18vYB5vW1NZplsut3N041UeBumHDcguVK10OKI9G cBogLpE8LFCQ0WrJjwTrNLaI5gV281Yc9JOFOu6A60/ZJ++7PZKz9rHBHWKft199HDS9 ocUAjQMjGEM+iIRD8s4Ps3o7Cf42KyNSxSAyhTpSsKQ8ycTS6dbZnNL4eV+HWdCV2TJl X1Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=imkLBLHYrUm4+V0oyc+OoHT1TLZgCH1uUIOJdSiz5m8=; b=tlEXHk3lMsW8HH79qY+ml3wtuiRCaMZuTcCAXCi0lZV/4GC2b5dtR+cZffHiuFFaLD 4j/VkCrgiREPQ8lWR+0WtK9kX0QTCxtXJHH18D7lihR57rZ5lvy05r/55iCHyeK8g7/n MMwpOCYSju6KwnS922YxFfty09ERtQ4d745LOYi0++jssQKBHU1yPQD/Eui5aJhsRHpC 103rFS/e6dpruIs2IdlxXgo2TbvIF3WveoUBeagLm9eYolr06g+NSQNyHsXsWvSYkVPo oG0bO52Cbjk8epkdAUMwqvra6ud4fApQ706FvLjX/YLEwhcWJ3VfAv01rUpy4UT7k0KI u9Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c8W4HfAE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:51 -0700 Message-Id: <20180511024454.31679-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v3 08/11] target/arm: Implement FCMP for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée These where missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Diagnose lack of FP16 before fp_access_check] Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 + target/arm/helper-a64.c | 10 +++++ target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++-------- 3 files changed, 83 insertions(+), 17 deletions(-) -- 2.17.0 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b8028ac98c..9d3a907049 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,8 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) +DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 549ed3513e..4f8034c513 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -85,6 +85,16 @@ static inline uint32_t float_rel_to_flags(int res) return flags; } +uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status) +{ + return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); +} + +uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status) +{ + return float_rel_to_flags(float16_compare(x, y, fp_status)); +} + uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) { return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 523fcf4801..0ac586345e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4712,14 +4712,14 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) } } -static void handle_fp_compare(DisasContext *s, bool is_double, +static void handle_fp_compare(DisasContext *s, int size, unsigned int rn, unsigned int rm, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags = tcg_temp_new_i64(); - TCGv_ptr fpst = get_fpstatus_ptr(false); + TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); - if (is_double) { + if (size == MO_64) { TCGv_i64 tcg_vn, tcg_vm; tcg_vn = read_fp_dreg(s, rn); @@ -4736,19 +4736,35 @@ static void handle_fp_compare(DisasContext *s, bool is_double, tcg_temp_free_i64(tcg_vn); tcg_temp_free_i64(tcg_vm); } else { - TCGv_i32 tcg_vn, tcg_vm; + TCGv_i32 tcg_vn = tcg_temp_new_i32(); + TCGv_i32 tcg_vm = tcg_temp_new_i32(); - tcg_vn = read_fp_sreg(s, rn); + read_vec_element_i32(s, tcg_vn, rn, 0, size); if (cmp_with_zero) { - tcg_vm = tcg_const_i32(0); + tcg_gen_movi_i32(tcg_vm, 0); } else { - tcg_vm = read_fp_sreg(s, rm); + read_vec_element_i32(s, tcg_vm, rm, 0, size); } - if (signal_all_nans) { - gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); - } else { - gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + + switch (size) { + case MO_32: + if (signal_all_nans) { + gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } else { + gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } + break; + case MO_16: + if (signal_all_nans) { + gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } else { + gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); + } + break; + default: + g_assert_not_reached(); } + tcg_temp_free_i32(tcg_vn); tcg_temp_free_i32(tcg_vm); } @@ -4769,16 +4785,35 @@ static void handle_fp_compare(DisasContext *s, bool is_double, static void disas_fp_compare(DisasContext *s, uint32_t insn) { unsigned int mos, type, rm, op, rn, opc, op2r; + int size; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); op = extract32(insn, 14, 2); rn = extract32(insn, 5, 5); opc = extract32(insn, 3, 2); op2r = extract32(insn, 0, 3); - if (mos || op || op2r || type > 1) { + if (mos || op || op2r) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + size = MO_32; + break; + case 1: + size = MO_64; + break; + case 3: + size = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4787,7 +4822,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t insn) return; } - handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); + handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); } /* Floating point conditional compare @@ -4801,16 +4836,35 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) unsigned int mos, type, rm, cond, rn, op, nzcv; TCGv_i64 tcg_flags; TCGLabel *label_continue = NULL; + int size; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); cond = extract32(insn, 12, 4); rn = extract32(insn, 5, 5); op = extract32(insn, 4, 1); nzcv = extract32(insn, 0, 4); - if (mos || type > 1) { + if (mos) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + size = MO_32; + break; + case 1: + size = MO_64; + break; + case 3: + size = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4831,7 +4885,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) gen_set_label(label_match); } - handle_fp_compare(s, type, rn, rm, false, op); + handle_fp_compare(s, size, rn, rm, false, op); if (cond < 0x0e) { gen_set_label(label_continue); From patchwork Fri May 11 02:44:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135475 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp330239lji; Thu, 10 May 2018 19:53:26 -0700 (PDT) X-Google-Smtp-Source: AB8JxZq+7gDG6XHsPwB42zQorOsEL0p9LgVo6vqaj5CVUx7L8gVwZY9+n0W5fQqcm8p+jrwdBZON X-Received: by 2002:a37:4f10:: with SMTP id d16-v6mr3357300qkb.50.1526007206128; Thu, 10 May 2018 19:53:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526007206; cv=none; d=google.com; s=arc-20160816; b=UJ8ONBKigTGvNwvvbSaUr/HhBWZMi/8aAexE70vRiqj+m/r+US3NNbrJi/qcywx/4n wFGv2qP5CRC1/ujvr27rOOqMUs8DbUVtWgsXZCIEbZg3pL44BV+DEjoBIvrmhIw9B6uV AA9ffuikdeV66A40V6yolTIGjSg29o8D2QisEQRg5K4H0br+uX0MTZpmXBbf71hkSxhV 3zCA5Sng87hUu0StDGPy6PnTAxQrOUpL2UH9BBkfs7w6CTDh3MvnTBMajq0MObkyhqc/ 8LYHbXp0grx1DJTZfLVM8568DEesbGBVIvesc4lHupXP5Ng505i7D0qoP2jhg9er8Lj4 zHyg== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:52 -0700 Message-Id: <20180511024454.31679-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v3 09/11] target/arm: Implement FCSEL for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée These were missed out from the rest of the half-precision work. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Fix erroneous check vs type] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0ac586345e..85a46f7abd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4903,15 +4903,34 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) unsigned int mos, type, rm, cond, rn, rd; TCGv_i64 t_true, t_false, t_zero; DisasCompare64 c; + TCGMemOp sz; mos = extract32(insn, 29, 3); - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ + type = extract32(insn, 22, 2); rm = extract32(insn, 16, 5); cond = extract32(insn, 12, 4); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (mos || type > 1) { + if (mos) { + unallocated_encoding(s); + return; + } + + switch (type) { + case 0: + sz = MO_32; + break; + case 1: + sz = MO_64; + break; + case 3: + sz = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -4920,11 +4939,11 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) return; } - /* Zero extend sreg inputs to 64 bits now. */ + /* Zero extend sreg & hreg inputs to 64 bits now. */ t_true = tcg_temp_new_i64(); t_false = tcg_temp_new_i64(); - read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32); - read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32); + read_vec_element(s, t_true, rn, 0, sz); + read_vec_element(s, t_false, rm, 0, sz); a64_test_cc(&c, cond); t_zero = tcg_const_i64(0); @@ -4933,7 +4952,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) tcg_temp_free_i64(t_false); a64_free_cc(&c); - /* Note that sregs write back zeros to the high bits, + /* Note that sregs & hregs write back zeros to the high bits, and we've already done the zero-extension. */ write_fp_dreg(s, rd, t_true); tcg_temp_free_i64(t_true); From patchwork Fri May 11 02:44:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135477 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp331826lji; Thu, 10 May 2018 19:55:54 -0700 (PDT) X-Google-Smtp-Source: AB8JxZprYedTOu6W64E2jkXn6SFcGPgKFWFyazxPv2yGuGw4+5sf9AdEbRGzuI6vQGSJaUtZr6Jw X-Received: by 2002:a37:b6c6:: with SMTP id g189-v6mr3647589qkf.334.1526007353965; Thu, 10 May 2018 19:55:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526007353; cv=none; d=google.com; s=arc-20160816; b=QKhg4rCfElTJEZS4NPFwVS8sev7nwGrIgmHHEUEwq+Zqt31U9llgSUmEHvyhDbaixa q7aiYgdgF7EQrnM601DrL0/HH06V6uqesc+rOy23S97l/RX6kjgDsj928NRSgLhHJTUk sZqTzK0oKik8BDW7O/ZcEg1ffN7t7jiEsS4SuaODiwPAFuEM4doZSQMcHZiPBfD4EPij yb/A4GGE0rNoJ3LqV5YhXXcU4XtwU9awEcbLYWC7xlP7xiT12rSacJCHZdHcof+hhuJG LLjySZZXGk78eD8SMPRbCz/3UxYwB519/DvCXn9rts+LVz1suTM6Hm1dsOJBX2wjVYlq 5ZPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RBjkwsmo6PqvvVb5ytRMTfzsA4/w11RdkNk+t8rA5Kg=; b=oMZq/A/yBBg0AWKtnqpW2c0E1JlZ2jaBglB++stXi67NBeb7jrYWFLzgEpkxPOoj0L BehU8tQ0aNKrsXfziVYcjyOwirBuZl6m6o1ZXicswRy2BG7m7S17ozNpQGQEUYOapuqq Jxa0O3er6TQBnDRhN6rT2/mfqKP2SRg2lKHRfPAA9pacr26gAeP/1rM2g5HpYiGPx7yA F1Bo7RzlIDTm32jISOFm+QIBKwARjZBQHYiDbTVBUuD0gonooricRXkLaZLyKBINUJNQ 1t5X1fzbwxh1pvPZEJqPoUUIUAjm8rNPCsgPnJeFhwo2VADspR1CRzLiklUtzu9HNyr5 V+aQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R+/oBYIJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:53 -0700 Message-Id: <20180511024454.31679-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 10/11] target/arm: Implement FMOV (immediate) for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée All the hard work is already done by vfp_expand_imm, we just need to make sure we pick up the correct size. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Merge unallocated_encoding check with TCGMemOp conversion.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 85a46f7abd..d77eda7cbc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5674,11 +5674,25 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) { int rd = extract32(insn, 0, 5); int imm8 = extract32(insn, 13, 8); - int is_double = extract32(insn, 22, 2); + int type = extract32(insn, 22, 2); uint64_t imm; TCGv_i64 tcg_res; + TCGMemOp sz; - if (is_double > 1) { + switch (type) { + case 0: + sz = MO_32; + break; + case 1: + sz = MO_64; + break; + case 3: + sz = MO_16; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: unallocated_encoding(s); return; } @@ -5701,7 +5715,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) return; } - imm = vfp_expand_imm(MO_32 + is_double, imm8); + imm = vfp_expand_imm(sz, imm8); tcg_res = tcg_const_i64(imm); write_fp_dreg(s, rd, tcg_res); From patchwork Fri May 11 02:44:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135476 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp330664lji; Thu, 10 May 2018 19:54:06 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrwrqvpGSG3MACDguS1haopTbBGH4Oe+1L4soLLYkwr7lchlKAOiI1E/ntO+t4aZz7Qt1Ds X-Received: by 2002:a0c:e78a:: with SMTP id x10-v6mr3606314qvn.13.1526007246178; Thu, 10 May 2018 19:54:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526007246; cv=none; d=google.com; s=arc-20160816; b=RbxTV1bh/Y2LhmnHKZWB6AVwLfo6KDZXV+UncvQZ2gq392wbeRW8VzfWLQRcJBXUby 9ShQ9iQKGBuDDetERRf5Aq6/8dteuGJ3i3h+Cy3C6WAM7D9FJFG3gAn7hAAMVQoLF74C OyqTt6GY/k4FgWf8GIzwDeiL6L3k7fZ9UThrX7kBVoOncFTiC02ZybYzNoe8spUdtAOP fAWFQql7UuX0oWc16hIPWFOOrEddzLq/20YAOnqcy/FCouM1bbn2WB/4jkpDOmwBnukE b9UCJsuTL71emEizyavrCze0bMm5KufKV4K2jhbwFfTTztu/dSbplU4UAthyeS/JT5Db p4TA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=3wO77nwWyvUTdrKptxzVk6DCxG2ZwD2EuEIfUFsq+dw=; b=lLl+outDnvxa+y6BxG9DuGC8yVpfF8VBkLrp9knLJoE1eAaq9QkVixdIAc5rVRPCPv +m961fd/hyjWNOHbpOxyvg4QTt4enQIyNlizzN1HkAh6THGS7l3EVLnKF6LThA2BJsFx F7H6NYIbgzTEj7O5GwcKFNNWWLAx7gFl8aeSSIsqqoF732WERRD2KZbs5+BJkH/4991E A5o9URXyxWhk23xiH0UMTjk1hDEDKnJldc53+orptf6a3J++NxVRhSWud54q46ZKGmJN EZJWkU49Jj2vkFrgVi0Ot+WJT7nj5XP0Kw6ShGFMOSGEnWLwHLcVQok1wKvrKY4/Bpdt tiBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PQVniZui; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id n18-v6sm5420915pfg.36.2018.05.10.19.45.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 19:45:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 19:44:54 -0700 Message-Id: <20180511024454.31679-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511024454.31679-1-richard.henderson@linaro.org> References: <20180511024454.31679-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 11/11] target/arm: Fix sqrt_f16 exception raising X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée We are meant to explicitly pass fpst, not cpu_env. Cc: qemu-stable@nongnu.org Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d77eda7cbc..009a151379 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4976,7 +4976,8 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; case 0x3: /* FSQRT */ - gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env); + fpst = get_fpstatus_ptr(true); + gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); break; case 0x8: /* FRINTN */ case 0x9: /* FRINTP */