From patchwork Fri Mar 19 00:52:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 405168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69239C433E0 for ; Fri, 19 Mar 2021 00:53:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E14564F11 for ; Fri, 19 Mar 2021 00:53:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233427AbhCSAxF (ORCPT ); Thu, 18 Mar 2021 20:53:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231892AbhCSAwr (ORCPT ); Thu, 18 Mar 2021 20:52:47 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9316FC06175F; Thu, 18 Mar 2021 17:52:46 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id w18so8914383edc.0; Thu, 18 Mar 2021 17:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Igmc9cLwjjnQbW2NQgn8XSOIxrY5hQGnjVY13RlbqSs=; b=ZuwZPySLxKfbajls8fvAx6ZxvxXLGCqrU6d0wSZyj0vi8HicNuJqERrJvFiYYkudnH orbOFHe4B4R3hIpm/S4rTBazuQg20OuI9Ac+U9noozWEk3S563a4UyQF7/fRqqMC7fUt qvNLifBraOyIMw3wWZqsX/teK5T7dmBDngOs1FpMaRqxywHgfWIjPvDus8Lnj1nCjhFi rx8Y00V/lQEQRj1VWlvWOnuRbCZpXMHAVshuDPQ+7uyzN/7ec7q3tZBQevAwlw7UveYL m6s6bmNq/I1QPF/ZssPG90JA2xAhhfQhxGhtXh2y/ZPG/PRQlkuFVrLdLGga1P2I0KGS QbRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Igmc9cLwjjnQbW2NQgn8XSOIxrY5hQGnjVY13RlbqSs=; b=aRWOSlEsm8my1EcYfkPPfbfnZZWWx1AScdR4jCzE+J/fO8+O4nJIsX9U0ZkZDy8r+r IfWnwXDuJe20E/9F4u1Ahe7r1eYsMLTPLZxx6vZPLqjgGyf0Mj8Oc4RZG/53d/UE9Mc3 5PtdJQtKw3iRtqjGhqYcLGzlANF4d02fAreXYE/xl2Y4gGg3xMH5K1ULrY4G1iJOoryG zaYi1Rb880q+fZA7hpkX8OO5v14IQ7yA/8gSriqe8dRBNEPFIe1ZDr5VYCwPfJwwAa44 BrKzYDEZ6Zj7H8mrN05JQc6n3GkQW/62XODTiihyeWVm3a5kYzknKywKAMg4NiPknDSq bzvQ== X-Gm-Message-State: AOAM531AIA/cC51vRb9kK+7O+PZPLZeN5BJB4rJjsw/ie7ncwtl4FDrH LSGpf02krxRkoaglkB2vRjU= X-Google-Smtp-Source: ABdhPJyOx/xJvbaDPN/uPN7cj/jTTvZX29GGie3BKYmg774cntnpq8LkLb/WyerU4NEAeWFKCnfW1w== X-Received: by 2002:a05:6402:2744:: with SMTP id z4mr6831334edd.347.1616115165262; Thu, 18 Mar 2021 17:52:45 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:52:45 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 1/9] drivers: thermal: tsens: Add VER_0 tsens version Date: Fri, 19 Mar 2021 01:52:19 +0100 Message-Id: <20210319005228.1250-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org VER_0 is used to describe device based on tsens version before v0.1. These device are devices based on msm8960 for example apq8064 or ipq806x. Signed-off-by: Ansuel Smith Reviewed-by: Thara Gopinath --- drivers/thermal/qcom/tsens.c | 141 ++++++++++++++++++++++++++++------- drivers/thermal/qcom/tsens.h | 4 +- 2 files changed, 116 insertions(+), 29 deletions(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index d8ce3a687b80..277d9b17e949 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int irq, void *data) dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", hw_id, __func__, temp); } + + if (tsens_version(priv) < VER_0_1) { + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + break; + } } return IRQ_HANDLED; @@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + if (tsens_version(priv) < VER_0_1) { + /* Pre v0.1 IP had a single register for each type of interrupt + * and thresholds + */ + hw_id = 0; + } + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); @@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp) u32 valid; int ret; - ret = regmap_field_read(priv->rf[valid_idx], &valid); - if (ret) - return ret; - while (!valid) { - /* Valid bit is 0 for 6 AHB clock cycles. - * At 19.2MHz, 1 AHB clock is ~60ns. - * We should enter this loop very, very rarely. - */ - ndelay(400); + /* VER_0 doesn't have VALID bit */ + if (tsens_version(priv) >= VER_0_1) { ret = regmap_field_read(priv->rf[valid_idx], &valid); if (ret) return ret; + while (!valid) { + /* Valid bit is 0 for 6 AHB clock cycles. + * At 19.2MHz, 1 AHB clock is ~60ns. + * We should enter this loop very, very rarely. + */ + ndelay(400); + ret = regmap_field_read(priv->rf[valid_idx], &valid); + if (ret) + return ret; + } } /* Valid bit is set, OK to read the temperature */ @@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; int hw_id = s->hw_id; - int last_temp = 0, ret; + int last_temp = 0, ret, trdy; + unsigned long timeout; - ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); - if (ret) - return ret; + timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); + do { + if (tsens_version(priv) == VER_0) { + ret = regmap_field_read(priv->rf[TRDY], &trdy); + if (ret) + return ret; + if (!trdy) + continue; + } - *temp = code_to_degc(last_temp, s) * 1000; + ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); + if (ret) + return ret; - return 0; + *temp = code_to_degc(last_temp, s) * 1000; + + return 0; + } while (time_before(jiffies, timeout)); + + return -ETIMEDOUT; } #ifdef CONFIG_DEBUG_FS @@ -738,19 +772,31 @@ int __init init_common(struct tsens_priv *priv) priv->tm_offset = 0x1000; } - res = platform_get_resource(op, IORESOURCE_MEM, 0); - tm_base = devm_ioremap_resource(dev, res); - if (IS_ERR(tm_base)) { - ret = PTR_ERR(tm_base); - goto err_put_device; + if (tsens_version(priv) >= VER_0_1) { + res = platform_get_resource(op, IORESOURCE_MEM, 0); + tm_base = devm_ioremap_resource(dev, res); + if (IS_ERR(tm_base)) { + ret = PTR_ERR(tm_base); + goto err_put_device; + } + + priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); + } else { /* VER_0 share the same gcc regs using a syscon */ + struct device *parent = priv->dev->parent; + + if (parent) + priv->tm_map = syscon_node_to_regmap(parent->of_node); } - priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); - if (IS_ERR(priv->tm_map)) { + if (IS_ERR_OR_NULL(priv->tm_map)) { ret = PTR_ERR(priv->tm_map); goto err_put_device; } + /* VER_0 have only tm_map */ + if (!priv->srot_map) + priv->srot_map = priv->tm_map; + if (tsens_version(priv) > VER_0_1) { for (i = VER_MAJOR; i <= VER_STEP; i++) { priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, @@ -769,6 +815,10 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[TSENS_EN]); goto err_put_device; } + /* in VER_0 TSENS need to be explicitly enabled */ + if (tsens_version(priv) == VER_0) + regmap_field_write(priv->rf[TSENS_EN], 1); + ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; @@ -791,6 +841,20 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + priv->rf[TSENS_SW_RST] = devm_regmap_field_alloc( + dev, priv->srot_map, priv->fields[TSENS_SW_RST]); + if (IS_ERR(priv->rf[TSENS_SW_RST])) { + ret = PTR_ERR(priv->rf[TSENS_SW_RST]); + goto err_put_device; + } + + priv->rf[TRDY] = + devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]); + if (IS_ERR(priv->rf[TRDY])) { + ret = PTR_ERR(priv->rf[TRDY]); + goto err_put_device; + } + /* This loop might need changes if enum regfield_ids is reordered */ for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -806,7 +870,7 @@ int __init init_common(struct tsens_priv *priv) } } - if (priv->feat->crit_int) { + if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) { /* Loop might need changes if enum regfield_ids is reordered */ for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -844,7 +908,11 @@ int __init init_common(struct tsens_priv *priv) } spin_lock_init(&priv->ul_lock); - tsens_enable_irq(priv); + + /* VER_0 interrupt doesn't need to be enabled */ + if (tsens_version(priv) >= VER_0_1) + tsens_enable_irq(priv); + tsens_debug_init(op); err_put_device: @@ -943,10 +1011,14 @@ static int tsens_register_irq(struct tsens_priv *priv, char *irqname, if (irq == -ENXIO) ret = 0; } else { - ret = devm_request_threaded_irq(&pdev->dev, irq, - NULL, thread_fn, - IRQF_ONESHOT, - dev_name(&pdev->dev), priv); + /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */ + ret = devm_request_threaded_irq( + &pdev->dev, irq, + tsens_version(priv) == VER_0 ? thread_fn : NULL, + tsens_version(priv) == VER_0 ? NULL : thread_fn, + tsens_version(priv) == VER_0 ? IRQF_TRIGGER_RISING : + IRQF_ONESHOT, + dev_name(&pdev->dev), priv); if (ret) dev_err(&pdev->dev, "%s: failed to get irq\n", __func__); @@ -975,6 +1047,19 @@ static int tsens_register(struct tsens_priv *priv) priv->ops->enable(priv, i); } + /* VER_0 require to set MIN and MAX THRESH + * These 2 regs are set using the: + * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C + * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C + */ + if (tsens_version(priv) < VER_0_1) { + regmap_field_write(priv->rf[CRIT_THRESH_0], + tsens_mC_to_hw(priv->sensor, 120000)); + + regmap_field_write(priv->rf[CRIT_THRESH_1], + tsens_mC_to_hw(priv->sensor, 0)); + } + ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); if (ret < 0) return ret; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f40b625f897e..8e6c1fd3ccf5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,6 +13,7 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define TIMEOUT_US 100 #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 @@ -25,7 +26,8 @@ struct tsens_priv; /* IP version numbers in ascending order */ enum tsens_ver { - VER_0_1 = 0, + VER_0 = 0, + VER_0_1, VER_1_X, VER_2_X, }; From patchwork Fri Mar 19 00:52:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 405166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83560C43333 for ; Fri, 19 Mar 2021 00:53:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56EEB64F10 for ; Fri, 19 Mar 2021 00:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233369AbhCSAxI (ORCPT ); Thu, 18 Mar 2021 20:53:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233320AbhCSAwx (ORCPT ); Thu, 18 Mar 2021 20:52:53 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ABA7C06174A; Thu, 18 Mar 2021 17:52:53 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id o19so8880461edc.3; Thu, 18 Mar 2021 17:52:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EDfaDBQwdj1r2Yr+BxzE8VnBhjB9D9cT/n8UjW/MV9w=; b=gUCdWsuLqwaPlkuEDt9Oop1znM7h12O8xPPcUuOQjNIJtPM+E3wGf1dSAAf8wUCGwF 0fBFkY2ne/n9nY22Xb1Nj5H04hc+tW9quqCK5puaExrZGAyMR//onn26gBFGCayipUfS 8Xz+InUrXzpc41ejkUsurzzgDLrZflrB/uhwYigO8IIdCRSjxaPA5xCxZ/eoWtU7YTqr PXv9U5ib8gm8+YlHyzZAC6vwFclUzfSd3EPZ0qU6tVSoZGx0lF1Y8P3wX/+FJmTzmJ89 z3wpRfaL5uktbPbZC6Y34Vku92xP9PT4MUZ2ixNrevwDnos1uyRHMucXcEba5RbwppsI W64A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EDfaDBQwdj1r2Yr+BxzE8VnBhjB9D9cT/n8UjW/MV9w=; b=OosEuh/v0ZQoeu75wF8gDRqDLqcaCmapv4TPfM0rLJzQ3r7UqgxCb8vDOOq8r1tFcs nzLnnZc87N1B5MJK0hLJlBia1BfIYX75kHdEAgHT8eoxv3s4wG9LnBMMU4UzWYUTIqQz Vv4kGHumUl9aeWYxjQWyYzabWxBqoFfc+dJqnWuhNBjKpDX0jUxAQctfmNCnAkyt/Vf8 djsOKCde5KmXIhWfAO4fCXODOH10VuHR7M2uTHJT2GEfONEnk8Jm5XvP/hJ0eFR3P1EG hfWcZaCj4VSESIHCSBn/VUdK/ZVC1DD8Db8brzUxEyFTVwWBHRWBK948zXkoD5IB1TuQ CMig== X-Gm-Message-State: AOAM533JV2a1zQkANQrd3TJVYCz6DMlAmhE3NM5M8X0lFF5kaI0ZB72W UM8kks2Nhz92jNe6G7bM7m0= X-Google-Smtp-Source: ABdhPJx8W9IVThfrUrd7Xx6hNNF7z66eirAkmHc2Wj+kxARx+gdqj8Q/FPBWB9ZNkN68r0/vdTnkQA== X-Received: by 2002:a50:eb8f:: with SMTP id y15mr6845942edr.115.1616115171947; Thu, 18 Mar 2021 17:52:51 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:52:51 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 4/9] drivers: thermal: tsens: Use init_common for msm8960 Date: Fri, 19 Mar 2021 01:52:22 +0100 Message-Id: <20210319005228.1250-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Use init_common and drop custom init for msm8960. Signed-off-by: Ansuel Smith Reviewed-by: Thara Gopinath --- drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------ 1 file changed, 1 insertion(+), 51 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 3f4fc1ffe679..86585f439985 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -173,56 +173,6 @@ static void disable_8960(struct tsens_priv *priv) regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); } -static int init_8960(struct tsens_priv *priv) -{ - int ret, i; - u32 reg_cntl; - - priv->tm_map = dev_get_regmap(priv->dev, NULL); - if (!priv->tm_map) - return -ENODEV; - - /* - * The status registers for each sensor are discontiguous - * because some SoCs have 5 sensors while others have more - * but the control registers stay in the same place, i.e - * directly after the first 5 status registers. - */ - for (i = 0; i < priv->num_sensors; i++) { - if (i >= 5) - priv->sensor[i].status = S0_STATUS_ADDR + 40; - priv->sensor[i].status += i * 4; - } - - reg_cntl = SW_RST; - ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl); - if (ret) - return ret; - - if (priv->num_sensors > 1) { - reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18); - reg_cntl &= ~SW_RST; - ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR, - CONFIG_MASK, CONFIG); - } else { - reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16); - reg_cntl &= ~CONFIG_MASK_8660; - reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660; - } - - reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT; - ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); - if (ret) - return ret; - - reg_cntl |= EN; - ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); - if (ret) - return ret; - - return 0; -} - static int calibrate_8960(struct tsens_priv *priv) { int i; @@ -346,7 +296,7 @@ static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = { }; static const struct tsens_ops ops_8960 = { - .init = init_8960, + .init = init_common, .calibrate = calibrate_8960, .get_temp = get_temp_8960, .enable = enable_8960, From patchwork Fri Mar 19 00:52:26 2021 Content-Type: text/plain; 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[95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:53:00 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 8/9] drivers: thermal: tsens: Add support for ipq8064-tsens Date: Fri, 19 Mar 2021 01:52:26 +0100 Message-Id: <20210319005228.1250-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add support for tsens present in ipq806x SoCs based on generic msm8960 tsens driver. Signed-off-by: Ansuel Smith Reviewed-by: Thara Gopinath --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 44bce16217db..1fd634f8f5d2 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -964,6 +964,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume); static const struct of_device_id tsens_table[] = { { + .compatible = "qcom,ipq8064-tsens", + .data = &data_8960, + }, { .compatible = "qcom,msm8916-tsens", .data = &data_8916, }, { From patchwork Fri Mar 19 00:52:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 405164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9DA1C433E0 for ; Fri, 19 Mar 2021 00:53:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEC3D64F1F for ; Fri, 19 Mar 2021 00:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233508AbhCSAxL (ORCPT ); Thu, 18 Mar 2021 20:53:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233425AbhCSAxE (ORCPT ); Thu, 18 Mar 2021 20:53:04 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81F56C06174A; Thu, 18 Mar 2021 17:53:04 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id k10so6912282ejg.0; Thu, 18 Mar 2021 17:53:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=21TRq5T7n/YlJzaiHd/rYW7/ONn9U06XAcWKZPDtNYI=; b=HfVgopGoETyq/qL91s46wIh+DPOYwlenzABf9SnprD/fPcZDwBJr/erbz2wJCHxPjf B2NuP6K1rNjWefJkzymM/3V6aEGeL15usMaiuNowsbuY99umQf6jw7hXi4OcBm8bCHki He0VBb7uPgnsWKmC1OLidSVRYzkT6IAy2V4sSeqk8agWhCsU43BybkyonRJ9Vd2R2Spy EEcczaCaGD7nnQRin07ma5REaxrUZ/EkSinRgaDTbocCQ9nVM2ywRvAZ9qQ+rirPbaeq Ijjrd4zQ7wmA1XcpIuJPee9bsy5earsCgM2aTiFoxJ+AI1BOM+hGh+j76aRmq4uYZGKP BP+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=21TRq5T7n/YlJzaiHd/rYW7/ONn9U06XAcWKZPDtNYI=; b=ID174VNhRKncsMfqXMN3OlFxFkTpLmdE8yZVo2h1wsWX+EJ4hBQZnFxkg36Dkpsu3Y msJziWnNx25qNKgIDnD3ioOkeVoYkWF/XxHZuzZGs/IenQo6HYDZNe1IvaTBbuo2slmI PNfblCy6Sw+Zx8ewqy/am1VbUK5mHiDdPhrwNjUEDCyQU17KtMQZ6t7WoEFN5RFyT+Zn 9snra+PVLl8TEXNGsWsa/+PZXkfuLLMcdTU7PjuTdvnaEOhYU5oa8ytHyJblrzqw837/ JaJ4KDt7gmi97p1ol14aZsS0REtrFn8Itr0uHL2cFyhTbwOTHUgQBdPHBlok2o57c01S j+2Q== X-Gm-Message-State: AOAM532BfPVrVJAbuF/TO5qTr3WGB59VBpS7QbHnrtvBdRazUHokvk9r n94po+oMMtRLnwTWg/0os4A= X-Google-Smtp-Source: ABdhPJyRp77kRe/bUrg00EgV0RbYbBbnjm25fQkgj9cvvya1zbaw+FdG0oFO5Xc+VlmduMkyytZLLQ== X-Received: by 2002:a17:907:77d4:: with SMTP id kz20mr1455770ejc.93.1616115183180; Thu, 18 Mar 2021 17:53:03 -0700 (PDT) Received: from Ansuel-xps.localdomain (host-95-233-52-6.retail.telecomitalia.it. [95.233.52.6]) by smtp.googlemail.com with ESMTPSA id q25sm3186976edt.51.2021.03.18.17.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 17:53:02 -0700 (PDT) From: Ansuel Smith To: Thara Gopinath Cc: Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 9/9] dt-bindings: thermal: tsens: Document ipq8064 bindings Date: Fri, 19 Mar 2021 01:52:27 +0100 Message-Id: <20210319005228.1250-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210319005228.1250-1-ansuelsmth@gmail.com> References: <20210319005228.1250-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document the use of bindings used for msm8960 tsens based devices. msm8960 use the same gcc regs and is set as a child of the qcom gcc. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- .../bindings/thermal/qcom-tsens.yaml | 56 ++++++++++++++++--- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 95462e071ab4..1785b1c75a3c 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -19,6 +19,11 @@ description: | properties: compatible: oneOf: + - description: msm9860 TSENS based + items: + - enum: + - qcom,ipq8064-tsens + - description: v0.1 of TSENS items: - enum: @@ -73,7 +78,9 @@ properties: maxItems: 2 items: - const: calib - - const: calib_sel + - enum: + - calib_backup + - calib_sel "#qcom,sensors": description: @@ -88,12 +95,20 @@ properties: Number of cells required to uniquely identify the thermal sensors. Since we have multiple sensors this is set to 1 +required: + - compatible + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - "#qcom,sensors" + allOf: - if: properties: compatible: contains: enum: + - qcom,ipq8064-tsens - qcom,msm8916-tsens - qcom,msm8974-tsens - qcom,msm8976-tsens @@ -114,17 +129,42 @@ allOf: interrupt-names: minItems: 2 -required: - - compatible - - reg - - "#qcom,sensors" - - interrupts - - interrupt-names - - "#thermal-sensor-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,tsens-v0_1 + - qcom,tsens-v1 + - qcom,tsens-v2 + + then: + required: + - reg additionalProperties: false examples: + - | + #include + // Example msm9860 based SoC (ipq8064): + gcc: clock-controller { + + /* ... */ + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + - | #include // Example 1 (legacy: for pre v1 IP):