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Fri, 19 Mar 2021 07:26:25 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: u-boot@lists.denx.de, uboot-imx@nxp.com, Peng Fan Subject: [PATCH 01/26] tools: imx image: fix write warning Date: Fri, 19 Mar 2021 15:56:53 +0800 Message-Id: <20210319075718.14181-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210319075718.14181-1-peng.fan@oss.nxp.com> References: <20210319075718.14181-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: MA1PR01CA0170.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::20) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by MA1PR01CA0170.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Fri, 19 Mar 2021 07:26:23 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c0d20488-6723-4ba0-6776-08d8eaa84de1 X-MS-TrafficTypeDiagnostic: DBAPR04MB7223: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1468; 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unsigned char *ptr; int tail; - int zero = 0; + uint64_t zero = 0; uint8_t zeros[4096]; int size, ret; diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 9985b95a98..11e40ccd94 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -248,7 +248,7 @@ static void copy_file(int ifd, const char *datafile, int pad, int offset, struct stat sbuf; unsigned char *ptr; int tail; - int zero = 0; + uint64_t zero = 0; uint8_t zeros[4096]; int size, ret; From patchwork Fri Mar 19 07:56:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 404740 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1140037jai; Fri, 19 Mar 2021 00:27:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFPErcRwC/M2wmtYNIg70ciyTKQxwt3HmdjBiLzMMZeZpbSVFfYIDupX0wOjYmBZGhIf4u X-Received: by 2002:a50:ef11:: with SMTP id m17mr7937447eds.151.1616138835911; Fri, 19 Mar 2021 00:27:15 -0700 (PDT) ARC-Seal: i=2; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: fxJ60IvZA4tAozTFtoW6suR+LYWLjbg1Y13crOPG6HeqsO5YVqOg4KsljJRTQnIwJwDyRdg6lOmPFSpXsYsev3zHbrVSNTwUV5Yy+QjGXK2qjDYC8yCqoJAa3KvwQDvnjjct4hxky7IELPwtpCPlhkxeMEhNJPhLG8NYouBoyTb8ID8U/eFl1NtKGk2KfU7a+js8zRc1Jek++ztf/IHRv7+1jYcIjNTKAoY9dBCM+ApCZ/mPaCHt5g09s0o+Ww3qYCwmarQzp/uaANjoqESXauFUEE4VABl8D9pnTKI1UtkpOPJGjKNEXzhJCNw/pqSST3QVxhlsAZbUBbPbhdlpdCj0aqKST16X/OQXyrNOPOuEnlo9KAsG0tKpEU+bqc0SrrHkHx6j4pswn6DOTqP9UkkBpt3k+HbkGPf7WMeeH41h2nAScgB9RUWNAxjUIsKHniyWn4iBc53soScuqWI6icf4nwLqCNkmbfOyCOoMEjlDOfZmfkZfjw8KZJJT5ylfiXuV4K/6fT40r2ZsdfxaKS8xj1F6n0Iqc9nTC/+YpVZPrw3BWGPX32LxMvU+XJVpFpN8WBvBIgKMwnGzLl38crnrYURJUoNCrRvnh133enksGoKWf4XHTDwJLsF3XItnzr4gKrSZzSOUIO45WOjLpRWwif6aVTP7D0MsgFixdr6VApYVRQNHnpVY73JaZ7OdcM3w7DEl5op2jyp0QLPNkv3/XPxnAP4Qb69VKp1QAI+LOE955w3XZHfYdq/A5N15m0flKnsQvQPMv6IUvrd9UZlRQ1MxKXaYdlIl9VO8X8cS8IQlsp1FIEnE6GmsneywYtQiY2jwlkMH00TpP4W8AyvHLa8zAQEAFDmoUvXIvwvL22ZTr/PCA+K8K0UxIA+5PXyAokbc7alz2+jEp7BT1H++iyfauOx73WnWrg2STJuzrXfz6pVsIglkGvxOk/1T8A6/qyS4PiY6MrGbsvFSFe277i42QPQMrw6VxE1zPs/R9HYn+ojVigTUy3/1WEOjo+aqlGsX3popB60beU2i99egCR2KtUIioTx+CztO2gFW/I1OiXzjAY66xSjJviMrZP4qI4xPsigETY8idYuRva55Q0zJVeTfZ+JzQmDTF7n8kDeU6j/6z46jumvhztNhwItNxIsqhPHGkAUCsEulFWhqdNOPQg3HOt1ZhJRfPex4zvbM24xoF96Rj5gCV7DeceV9kEEeRtrGRadbOJmYxz4x8jNUgF+RJldc04GQv194KKqddBnlq78bLhJefYEOr/yBVsoO+i1+8fMr7GhZFE0EuPAxQIjATNt90TyGlVMtyi7AI+vDgLIB9nmeCq5Z X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0831c0ee-ce18-465c-7064-08d8eaa85302 X-MS-Exchange-CrossTenant-AuthSource: DB6PR0402MB2760.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2021 07:26:34.3278 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Px0Yr3aG2ZXEzk9UvjBiQr4MUCNn1nMgpjPCA+0WagH6jRhtXq2eq4wYRUDSA3NFI0SQN94t+rQlnFp+iU0lHA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7223 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Peng Fan These files should not be in U-Boot repo Signed-off-by: Peng Fan --- board/freescale/imx8mm_evk/boot.cmd | 35 ----------------------------- board/freescale/imx8mp_evk/boot.cmd | 25 --------------------- 2 files changed, 60 deletions(-) delete mode 100644 board/freescale/imx8mm_evk/boot.cmd delete mode 100644 board/freescale/imx8mp_evk/boot.cmd -- 2.30.0 diff --git a/board/freescale/imx8mm_evk/boot.cmd b/board/freescale/imx8mm_evk/boot.cmd deleted file mode 100644 index fdfceec263..0000000000 --- a/board/freescale/imx8mm_evk/boot.cmd +++ /dev/null @@ -1,35 +0,0 @@ -setenv bootargs console=${console} root=${mmcroot}; - -for boot_target in ${boot_targets}; -do - if test "${boot_target}" = "mmc1" ; then - if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from SD card(mmc1); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - - if test "${boot_target}" = "mmc2" ; then - if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from eMMC(mmc2); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - - if test "${boot_target}" = "dhcp" ; then - if dhcp ${kernel_addr_r} ${serverip}:${image}; then - if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then - echo Load image and .dtb from net(dhcp); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - -done diff --git a/board/freescale/imx8mp_evk/boot.cmd b/board/freescale/imx8mp_evk/boot.cmd deleted file mode 100644 index 10bcced774..0000000000 --- a/board/freescale/imx8mp_evk/boot.cmd +++ /dev/null @@ -1,25 +0,0 @@ -setenv bootargs console=${console} root=${mmcroot}; - -for boot_target in ${boot_targets}; -do - if test "${boot_target}" = "mmc1" ; then - if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from SD card(mmc1); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - - if test "${boot_target}" = "mmc2" ; then - if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then - if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then - echo Load image and .dtb from eMMC(mmc2); - booti ${kernel_addr_r} - ${fdt_addr}; - exit; - fi - fi - fi - -done From patchwork Fri Mar 19 07:56:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 404741 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1140117jai; Fri, 19 Mar 2021 00:27:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEhTlSbE3OvT26468/L9v9h0GLzs4AW1ettxU7Wo0DL0TIddBtVPIt4iJaGE8EnE+WBoPw X-Received: by 2002:a17:907:75d9:: with SMTP id jl25mr2732065ejc.452.1616138844292; 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Fri, 19 Mar 2021 07:26:58 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: u-boot@lists.denx.de, uboot-imx@nxp.com, Peng Fan , Ye Li Subject: [PATCH 12/26] imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage Date: Fri, 19 Mar 2021 15:57:04 +0800 Message-Id: <20210319075718.14181-13-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210319075718.14181-1-peng.fan@oss.nxp.com> References: <20210319075718.14181-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: MA1PR01CA0170.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::20) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by MA1PR01CA0170.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Fri, 19 Mar 2021 07:26:56 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 3f3023f9-6965-44d5-7a8c-08d8eaa86175 X-MS-TrafficTypeDiagnostic: DBAPR04MB7223: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: no1kej8Gw1LC6yYktsa6NmR7U0T/MSGSgk/MpIEYqWY6sazlTXE0M6rLccEKVITAoezwcE5F4eyYlr/VYHDyCzEGbvXbaDpUFqrgxxIgOkGXSmMV882STqiz3vCKPK+G/VrraBy5hBnuaDV44Ygg8+Jtwmve4ZljYEhOxw/LWSHGeJdESJjcLGN6X0TKG9YqO4ougKtoRqoxbMVhEtJKuXdo+jiDBHaFBAUJczZKzvkB/EXZQUVOQR6cJYbrkaotjc1e4koeJaPMRy5knO07H7tN7qgkT85yic8jkNPO8ewRqyfipA7XcHn0PTjwQ/a4kG41+/hAFOGTMyDhEzfQm30DMkUhRsYAvhZsPhABqWF9F5gc8i9Wu2nd+slAnMRhB4I2PONUEu/Waq4XPlrhlJS1Ryde0iGm7JW2Amgr7jlUP3QgeUIxtV6vmJgJusS8jaJ0hWn1jqSVy+E8Mf3sMtYAlStnsI4wOS8LjdCuDgV4Qqys4AUZY8sw9t8GtIjlmYPmQ+GZ9GdO1TKPjbvJpEqZ0VMrRg+Qn1m8Z9lt6fxooGffh+z1GcZY581OQE/UAC6Yc9C96umbPYegJOHx6RZAx8mRBd5JSXFxE5Zjc7t9M/WAAAiX/AcEB2coLSzNxdZD+XiDRy+A0dIsNSwH+wM9HJ5z1LQQUFDNaEyX6Sxh+ScBoa53vrQZbH39HWcLsGHmDrfPCiFlpiIEMv4a/iJKXtIVy79Ays1r/orrG0hI+CsCKuDCGLw94dGHz8edZMrq7zFRf7fNtaZbFMrrnajT8Df9QD9KuOi3qJYa4TMTWHn6lkb/7k/7X/TvH6Rl5Zya4Gsj+WtGrRnOA4B1Q89Buv4aSWgOsSTgrLNHEk+z955fts2C0vtU6GEzYkA/PPcLX0gBlwAvdx0jKmF6Nhl9ziKX1lzka8K840GvRbce1N/w38stKXSITkR3jSXnFfdHYmfuq09C2dWenmnthvrx2R6bN0KaaHfBmnvDpV/IQC5VJtbCGN5iQ0jQbtBuMSyAVOKbV1iSGcyAu8/T7KeMHbYIV5nWpnV+1NaQ8pm5MCxo6yUNrxJQBQo+29fizsG6OottRgGPZhy7qXwxJsOT1qJ9FKmuq5yB68hPJ1mQY00MlVOtg45vDDaUDQNn5pyPTFh/S+DW7CBDaZjl+Dt7BhD0eNbnZPtpwgZqh64uWfqBKHR7QxtvrDrTDOwxE5D9tXQ02XA4494FBwYyXlCkM2GKFEDhV9HZGUJBUxHA9vY9Dv81Mm9KgvyDRDwvpyGzbGBHa4LoePNVr7UZtRx25vQQrEWOgqPoDBVM7WdtGmeL9gDF4NmVHAjt+NuN38GBaEJlB59nqqg2mkB/oA== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3f3023f9-6965-44d5-7a8c-08d8eaa86175 X-MS-Exchange-CrossTenant-AuthSource: DB6PR0402MB2760.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2021 07:26:58.6018 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4l4C5u5WM8IVEq28NWykND6yhyjSD4sfMJS8OVNgRzFihwBixhVLb1swD7uoATrmJ7rETpF/WuU3TgaL0rBURw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7223 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Peng Fan There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM. Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus clocks to OD frequency before it increases ARM voltage. So to conform to the limitation, we'd better increases VDD_ARM to OD voltage in SPL. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/spl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.30.0 diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index ef14cfc227..6ccf5ac8fa 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -35,6 +35,16 @@ void spl_dram_init(void) void spl_board_init(void) { + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + puts("Normal Boot\n"); } @@ -84,6 +94,10 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + /* set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); From patchwork Fri Mar 19 07:57:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 404745 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1141355jai; Fri, 19 Mar 2021 00:29:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycTo+uZte1n221wK1j6w9dmYW+wmBCjtKpvBKVTzoKxfqWFLDSP4gXJGrxYz44Z58qATHm X-Received: by 2002:a05:6402:b70:: with SMTP id cb16mr7999865edb.11.1616138961910; Fri, 19 Mar 2021 00:29:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1616138961; cv=pass; d=google.com; s=arc-20160816; b=EZnLx1Jg1EXdSF834jfJ60ez1xl8zpcqMaKdexBD5qq2SI9FeBjlEXQO24RpYpIjZs c9woTir3vXKY8n7gew4R76Mh2XHHc7wSwTudBdKE/G7EFWdnvdrmswpUi5DklGjOpq6O hexpMcrAGoytsMaCo5SxQxrkBpB69qbR8LSwg4qqYb0JWLbpZn3WQ6yKZhs+VWcgg0nR Oz4wUTmjnteVPKULF0NEep/Bg81vDsa46moYW3e8bw1313LeCNsOL+GVv2n/Lv9h3VDx eACV6YhVYa/4SUpp4nPjFQ51N7gz7+J525shmKbJrQOxxg6Z7aX2FafEOwKC+cmFdgx2 /+mw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=fvM/EC/D4inCublty5wThFfmRmp0hhQWBVr3uhEc/UI=; b=W40htOPAdauwZEnSzwoTR8oyNOiT+yUTZGKKdnX+AYh+9y87mPtFO9gxr9HCODu0xs BWMxYQZOg3es3kipu8AVNcstvFrUKrIUPKKUdqrEwnqNC7NS7LnFNbOxmLtBBNHjg0no 3oEdWlDbNRkZe9lilwxN3YKitAeTVvua5QjFJOuhEjzHZiDp2FVlAK52CwYsOJq65AnF QfqY/9vAzMCTZsfKEm12xEPZ3z+LGC7vmtNrMrtSNGMwDLP8fSZ5NAjmRAEpq/snp9mi 2DRVSbkAYoDCGAb6ARoyKeKomKg9zm+nTBGKkTMqWYiEY/hkIsmKq6l8TICMz0hnDUwE zs2A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=fWgBZe5x; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Fri, 19 Mar 2021 07:27:04 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: u-boot@lists.denx.de, uboot-imx@nxp.com, Peng Fan Subject: [PATCH 14/26] power: pca9450: add a new parameter for power_pca9450_init Date: Fri, 19 Mar 2021 15:57:06 +0800 Message-Id: <20210319075718.14181-15-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210319075718.14181-1-peng.fan@oss.nxp.com> References: <20210319075718.14181-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: MA1PR01CA0170.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::20) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by MA1PR01CA0170.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Fri, 19 Mar 2021 07:27:02 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c4adf419-9992-475f-0c9f-08d8eaa86509 X-MS-TrafficTypeDiagnostic: DBAPR04MB7223: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:883; 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Signed-off-by: Peng Fan --- board/freescale/imx8mp_evk/spl.c | 2 +- board/phytec/phycore_imx8mp/spl.c | 2 +- drivers/power/pmic/pmic_pca9450.c | 4 ++-- include/power/pca9450.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) -- 2.30.0 Reviewed-by: Jaehoon Chung diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 6ccf5ac8fa..a7564e9b1a 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -70,7 +70,7 @@ int power_init_board(void) struct pmic *p; int ret; - ret = power_pca9450_init(I2C_PMIC); + ret = power_pca9450_init(I2C_PMIC, 0x25); if (ret) printf("power init failed"); p = pmic_get("PCA9450"); diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index eefdd7fdda..f9fa8d1e12 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -53,7 +53,7 @@ int power_init_board(void) struct pmic *p; int ret; - ret = power_pca9450_init(0); + ret = power_pca9450_init(0, 0x25); if (ret) printf("power init failed"); p = pmic_get("PCA9450"); diff --git a/drivers/power/pmic/pmic_pca9450.c b/drivers/power/pmic/pmic_pca9450.c index d4f27428bd..8c4d0a9230 100644 --- a/drivers/power/pmic/pmic_pca9450.c +++ b/drivers/power/pmic/pmic_pca9450.c @@ -11,7 +11,7 @@ static const char pca9450_name[] = "PCA9450"; -int power_pca9450_init(unsigned char bus) +int power_pca9450_init(unsigned char bus, unsigned char addr) { struct pmic *p = pmic_alloc(); @@ -23,7 +23,7 @@ int power_pca9450_init(unsigned char bus) p->name = pca9450_name; p->interface = PMIC_I2C; p->number_of_regs = PCA9450_REG_NUM; - p->hw.i2c.addr = 0x25; + p->hw.i2c.addr = addr; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/power/pca9450.h b/include/power/pca9450.h index 5a9a697d62..27703bb1f9 100644 --- a/include/power/pca9450.h +++ b/include/power/pca9450.h @@ -54,6 +54,6 @@ enum { PCA9450_REG_NUM, }; -int power_pca9450_init(unsigned char bus); +int power_pca9450_init(unsigned char bus, unsigned char addr); #endif From patchwork Fri Mar 19 07:57:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 404746 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1141467jai; Fri, 19 Mar 2021 00:29:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYhTAasgFwxLWkF2mBr2ZDs+TPL+/qiFvzBEkjJR9Dg/7sqCU4vi2iudHqYNhGXZu9DbXJ X-Received: by 2002:a17:906:25c4:: with SMTP id n4mr2804171ejb.359.1616138977649; Fri, 19 Mar 2021 00:29:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1616138977; cv=pass; d=google.com; s=arc-20160816; b=yhSd/jMnqrCk48K8YNLxMC+ItLOPpH8V/rS/qIS2hXSZqRyt71MNCVI1tjs5nBe+sU iExNh990KRPYmKUednwQauVK3XgRUyNjpTAo/bh95gzPe9lV387UBvd0u2yBsNQQ5DFI kCGSSXYYyZ1fbPudi4iBak6uT2O2w4vlg8LTFw3NcNOgJcQY0re6MQMZ2upM1Das0szf uNnygfgloECC6wbh9IenKXIWWXtAfxYGkqEG5z5Fa3PArVFpqQ59UgDF5tMIE27J6NaA b81wnX3kfZZTATbAXXhUnQSAJfgB91s/lYz1pVPvMaRmOURwyElSLP4ONQHmdoJ+AKRU NIeA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=DQzy21U0TGKv43Vu1yV732/9FqE/gAvsafLAklrHKAE=; b=dkTKGdweC4MjmDnbLxRBV9TxuFKqvmW1OpmLlUYThszro2bpIQYXYYQwR8i8jm60Tw 6JqR2gRvBKh0e7Qa/Q1Lqw20gibnnEb8aLof6ml2XSxcJTyrVGr4cgtcR70ZlOuxeqYA YCXmJ2KntcF6xgnFw4qWei7DzEIJuHWdfpfB7fXkzof+FWsK08DpxWtkYL/Dx1Cd0YQ+ o3GcYXpvJWDm8Q80Z0mVMT8DVvO3NOeX2PvvhtL2GLuWFlSKX4kgvxOLCsMnAaUnw9o3 h62Wye+CLlPQOrNzhzz8fQVsafY4cw+qDxouoe7C8GJVRcLcXk0+Aqct7Hc6BGjUKFZy Fh9w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=lMzh2Q1X; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Peng Fan --- board/freescale/imx8mn_evk/spl.c | 2 -- 1 file changed, 2 deletions(-) -- 2.30.0 diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 6d5c7a5b46..80f79ce888 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -84,8 +84,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - init_uart_clk(1); - return 0; } From patchwork Fri Mar 19 07:57:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 404747 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1141606jai; Fri, 19 Mar 2021 00:29:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxR4citocNi8kZir/Uje6DUkfsvrg40f854bG1aWzhGsNmbFbKjhfkjeLA/e9wZkAS5RNWa X-Received: by 2002:aa7:dd4d:: with SMTP id o13mr8206206edw.53.1616138997982; Fri, 19 Mar 2021 00:29:57 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1616138997; cv=pass; d=google.com; s=arc-20160816; b=G2Jg/y8MjyxNKxpxuQLNBowKRN8R/z9zYyAJKPwA99WFiIrzhwgTmlK9ZKELsz7f6t ImDM5Ix0D0Gd0K6jKSRGmGgCUA8kcta2opi9OFaDA4lTlKGlW5AUPFyXEX6XsPZgFX/o EU9geDi6C9c2GbK5xvqEXrUbjI1WajwSAHQzLSBxE231rLU4+HVIs93voJXHit0KWrbX /XNhCCGbn4Cq0D7JqcuI6nYeaoLeUQcLzbPP4/F7Q5KoVP8wSKxnlyKIFbmhUWYRlFtZ 03eV2tYGTFMQenc8emqMbHos75YUuhdamlK0+TOcjHuubpJWLPlUJVKuQDuZD9XMYceu JHSQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=RJbLqOY6PQpp98yCwBWX9r2w6yiS8/eSsVFGqte9/2M=; b=A7u38XFMrP3nVRuk6iDVcrelKxV6imCiyiIWwkB+0mO46yNH3eJbF1nSAZ0pCswAQr U2LKrLUpg9muNyFhXND0+6ucw7lv7koj2SXCe6uLALJkdGdzBZdHmfiyoOM3VEqgR5O5 N6Uaa/F/dMPaD1jOLA3JTN4gEUKlSJr2ulO/maKfYdqLzimYPv1TeajrDrSLsIFIxcam +VOb61NbF42+irH1+n//Eqbpb743Z050yk96y+XnQIt8o1ahNodEV1q3VxsufZfLZie2 JvFfel9M0CCcAuziUI/2yleild2DkNbxM/HasxDZmr01rG9jeqqk1rLWU+KBunxX5BIi LYNQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=MAIhr+VV; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 3 + arch/arm/dts/imx8mn-evk-u-boot.dtsi | 26 + arch/arm/dts/imx8mn-evk.dts | 128 ++ arch/arm/mach-imx/imx8m/Kconfig | 6 + board/freescale/imx8mn_evk/Kconfig | 2 +- board/freescale/imx8mn_evk/Makefile | 1 + board/freescale/imx8mn_evk/lpddr4_timing.c | 1587 ++++++++++++++++++++ board/freescale/imx8mn_evk/spl.c | 43 + configs/imx8mn_evk_defconfig | 93 ++ 10 files changed, 1889 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mn-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-evk.dts create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing.c create mode 100644 configs/imx8mn_evk_defconfig -- 2.30.0 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c6710826a0..8cd7c5d2dc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -797,6 +797,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-verdin.dtb \ phycore-imx8mm.dtb \ imx8mn-ddr4-evk.dtb \ + imx8mn-evk.dtb \ imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 025090fff4..8cd15be7a8 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -19,6 +19,9 @@ &clk { u-boot,dm-spl; u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; }; &osc_24m { diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi new file mode 100644 index 0000000000..2730ff6a81 --- /dev/null +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mn-ddr4-evk-u-boot.dtsi" + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts new file mode 100644 index 0000000000..cd11fb28f5 --- /dev/null +++ b/arch/arm/dts/imx8mn-evk.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model = "NXP i.MX8MNano EVK board"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + pmic: pca9450@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1{ + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 12b8d0d831..59a45f7b01 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -49,6 +49,12 @@ config TARGET_IMX8MM_VENICE select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MN_EVK + bool "imx8mn LPDDR4 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" select IMX8MN diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 048fb7d97f..ace6fc1e39 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MN_DDR4_EVK +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK config SYS_BOARD default "imx8mn_evk" diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile index 9511a70c31..5d7dbe6628 100644 --- a/board/freescale/imx8mn_evk/Makefile +++ b/board/freescale/imx8mn_evk/Makefile @@ -8,5 +8,6 @@ obj-y += imx8mn_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o endif diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c new file mode 100644 index 0000000000..671e924132 --- /dev/null +++ b/board/freescale/imx8mn_evk/lpddr4_timing.c @@ -0,0 +1,1587 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000d0000, 0x00000000}, + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, + {0x00020060, 0x00000002}, + {0x000d0000, 0x00000001}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 80f79ce888..5d4c2ac4c9 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -25,6 +25,12 @@ #include #include #include +#include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +58,43 @@ void spl_board_init(void) printf("Failed to find clock node. Check device tree\n"); } +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ + /* Set DVS1 to 0.85v for suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* enable LDO4 to 1.2v */ + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} +#endif + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig new file mode 100644 index 0000000000..c53dc968c8 --- /dev/null +++ b/configs/imx8mn_evk_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_WATCHDOG=y From patchwork Fri Mar 19 07:57:13 2021 Content-Type: text/plain; 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Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.30.0 diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 6f7f093e87..c447ea2ab9 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -628,7 +628,8 @@ static int disable_mipi_dsi_nodes(void *blob) "/mipi_dsi_bridge@30A00000", "/dsi_phy@30A00300", "/soc@0/bus@30800000/mipi_dsi@30a00000", - "/soc@0/bus@30800000/dphy@30a00300" + "/soc@0/bus@30800000/dphy@30a00300", + "/soc@0/bus@30800000/mipi-dsi@30a00000", }; return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); @@ -656,7 +657,8 @@ static int check_mipi_dsi_nodes(void *blob) { static const char * const lcdif_path[] = { "/lcdif@30320000", - "/soc@0/bus@30000000/lcdif@30320000" + "/soc@0/bus@30000000/lcdif@30320000", + "/soc@0/bus@30000000/lcd-controller@30320000" }; static const char * const mipi_dsi_path[] = { "/mipi_dsi@30A00000", @@ -664,11 +666,13 @@ static int check_mipi_dsi_nodes(void *blob) }; static const char * const lcdif_ep_path[] = { "/lcdif@30320000/port@0/mipi-dsi-endpoint", - "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint" + "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint", + "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint" }; static const char * const mipi_dsi_ep_path[] = { "/mipi_dsi@30A00000/port@1/endpoint", - "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint" + "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint", + "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0" }; int lookup_node; @@ -776,7 +780,8 @@ static int low_drive_gpu_freq(void *blob) int disable_gpu_nodes(void *blob) { static const char * const nodes_path_8mn[] = { - "/gpu@38000000" + "/gpu@38000000", + "/soc@/gpu@38000000" }; return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn)); From patchwork Fri Mar 19 07:57:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 404749 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1142587jai; Fri, 19 Mar 2021 00:31:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyt6sDlnlsSBt2OwSmj82uQNrQkCZFwMPio7IdtoP/J4wl8B2VHYr1CdMUAOS38Nun8DXhp X-Received: by 2002:a17:906:1155:: with SMTP id i21mr2788788eja.218.1616139101542; Fri, 19 Mar 2021 00:31:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1616139101; cv=pass; d=google.com; s=arc-20160816; b=a9R8W0AOEGOxOi7q0kC1Ydahyz3sEGRkK9VhKiXij7V6+Q3sAS+8C2BlL8HvLUoNEu 87LcYsZu6zzS3J4sHnfLL/xVxV4+2j+FweBSzY7+3GLlHTWdo/I7IeQB3e5q0boQV11t Us7yzL/+z18gbffX/nvu5ALQW8e3KyorndY/pjOp/C4R2CCWA9wDPuRodXAah2vWuZvo SOtSh7VpoUBwWvXoMYn9QXU12s1DzoniIYRFb4cO5w09wyOnVTKDd4Y4ASe187Ud+dG5 WyE+dnkAzJEo4DGOnMjeSj4BNidnpIsspRhPyvhnQ/DwtCvYpabdFtTqV6aa8Vp0Bqxs eIfg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=y4WO38fgJ8diluNNq0K20Fo4Bytx4s1YiozloVua9wk=; b=I1sMq41YiGHoQDMe0oc2H6B3Dx43GnKjf3r/YceP44brR4i6sHRfmuKjIz5bO/sUIp y3fJkscOkmH8NEwMvdG6UFSf5ugl/RbKeOdFg54braYnOfv8weDrIRrhVh20JmjST+0E 6yHiLL5/79fxScQUW+F53s4gmqWR3Y4opssqjl1BGf2yKKxP7DJSGnbDNr1xP5ILmiAI r2sAUmDzlJnYewxBt6C8QAeVGpoBfISff4XEjCABjytUGtxzuSBx8zpo/lzubTIFlFkj tggVX0sHRlvYV0Hh8ZfEFZHlYhTF8bUUGXDbhzlfyXwbcptd+Y6yL7xm5hMTCXMAeOvf WwTA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=G6sI+VJh; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: lCJoLGoJlxS+dtGNMn20YVlYENVqFVqCUn3GYST2ze1R6BeWJAEhe9JvNeN7aSsTm/en9ANItuFdhV9luZDA52jMQtajRSbpsAej/h0Y1es8GTkk4S081N/kL7f+CGsisU8XbGWGAxpuU/CYNa/NgEdRKxRekbQPbMthrWjVsoGroz+/3+/gTvITi2+h+tRud2SS1zY8tYFnwbp/Vyo3Gp5feGddzgIUEICrKoX+lyDAi1iSdWb+TrzdF6xYLBOJfjTaTCmiF9UinZeD81eNqGptpFzvc8O8dSLoivgSc/6NSP0GShSIpsJfXrbk1ZOFMmrGySmYFDVYcFLJJ37N1qzbnsD1tUa6Xcuc0aOZafbtlurDE01GufV/IAjkaC0HCjMqHpBpPpTA5z2cqBkfX9hs1NEnF1+EIpjmpUIT2Af7Clxb/l1I5Ko1qnRtqst8fKtmZDpqeAkYPPhg8Eba1Xi0mGKqwpawFTV1Ib+eyasn5YBljDrLfzP03pq2HyOuMxZMHA6bBPt3trnnWsk4goC2P4BW4PzeQZEXQpjmHYGqhx6sdIwFV4jyZluA14+HgIk6OC2mMa9JFsttBu1gw6gXsTFTGtNHh9B2A3zhniWOVzZeDCuGy7gs6lRSqIQOYVmDVxo8Qh7orGJS7LtIkJpXjUHE17VRLpFFnsnf/JJ8tJkZ5SpmunAO8OTTQvuJ1LW2I14wXkRMOviT7xp9JD3uKgtClUfn3fUTkv5gP+QkDTmX1nMRs69X8vFZVvtSavu2Z4HRj5NJ2VNSfBw/8quTwGYg+U8T98upKk+NQue94qhs+g3TLpfXIfRHIdPk8lgYfy2Qvo9h1cKM9BR5jgGvDcDDkFIOm6wfMeLvN77nnVWqb1EZDvw2tuFykyTgTrlNN10gHBZS3M7YNgd+Ijh9yzrhNY6xMZVZ4+gw0zcSn6w2QVASv2TyYiyGaBOuIUk1BNWyYdt2R3e6++R4CQCItzQYRX7R9BU7oZuktFTcxoqX4uziwHMBgswjVLJglpRD8ryiaZtvnldHHeG1lvf3HwNjxCuIVu5GmXTbBGZvYbQ6HIhL6z0D44PIl8kNdWD1aZ9otPlVHEOuHchCRFkljIEJ5BQirCM3RaBrilTSP6sdRjDtfVkJHe31NGYgo2Su4LHLdUx9R8iVUh8sQFEJ6B00i9ctBOUVDnEr9f2J0SuQHRYTS01TROE8o23EEuvkCtaH48KwktNE9TI2liLhxsUcM3mEtpe2CLrJ+zy6N6ZaOPykX7oBxp//8aZOve6PhywELMa9zmxQA55+q3p/mu23quvsqnzFAIfcz1xiO1RjatuCM+sObIDOObNzU4jY+JS+oUh1rWdyQuV4PA== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43220d80-adae-476b-8ef4-08d8eaa8754f X-MS-Exchange-CrossTenant-AuthSource: DB6PR0402MB2760.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2021 07:27:31.9797 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HcOI2ty+SJyDdThTZzEinY0PbC+WFfYiDICWsufAvXBSKeKam+zWX4ggDkzFK30QBMsB1iLmwKG8wRF5M5ZsEA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6714 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Peng Fan The value of Unique ID in uboot and kernel is different for iMX8MP: serial#=02e1444a0002aaff root@imx8mpevk:/sys/devices/soc0# cat soc_uid D699300002E1444A The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and 0x430. Reviewed-by: Ye Li Signed-off-by: Alice Guo Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 3f50014618..49bac8c1fa 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -120,6 +120,16 @@ struct ocotp_regs { } bank[0]; }; +#ifdef CONFIG_IMX8MP +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[7]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[3]; +}; +#else struct fuse_bank0_regs { u32 lock; u32 rsvd0[3]; @@ -128,6 +138,7 @@ struct fuse_bank0_regs { u32 uid_high; u32 rsvd2[7]; }; +#endif struct fuse_bank1_regs { u32 tester3;