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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH v3 1/8] RISC-V: Enable CPU_IDLE drivers Date: Thu, 18 Mar 2021 18:35:05 +0530 Message-Id: <20210318130512.1025416-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210318130512.1025416-1-anup.patel@wdc.com> References: <20210318130512.1025416-1-anup.patel@wdc.com> X-Originating-IP: [122.167.155.94] X-ClientProxiedBy: MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.167.155.94) by MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Thu, 18 Mar 2021 13:05:41 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 4cb4b010-1d19-4070-1f59-08d8ea0e8bb5 X-MS-TrafficTypeDiagnostic: DM5PR04MB0826: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xS9w+NSYIRyJjyXY7adJzS+9gCDTk44yhVjCDIhCn/BIm7vlbRtNY2msOzR+GFgA/i7n2Xxb2/qPRjPG+9dhMa+K9jYhkCrex9fVu6SqWxs4kEiunwi12vVp1FE8CGAILUqobpcvtSGUjymIQ88QQhcgJavg/QD88BQ/yaO4yrIAoQbAwTpasWPS9rwFbwpth3B7kUSgD9mFUQhYUSuCYTekJ9BZoWbPPswfGDuqhbvK6AwD/ASCb+k8c5omm1pfZ5fWw/SDSNKaJRCbG1Sv/8vbluVhwqXBy1n19XxwipCSnpw0gvHFCfqNjkdTonfZupk87TJEvi586Ain686ahtnsQtOM7tO5jlyflF4IFb309bETtXkNsfqsNWssnrSjHLqODQbUfYL9ydVdkXCFU/XV/zzCDJ2Ryquv7EbNHtvccJhNLngL+wawv28Ti04OKiqovsh51vyw3nkjS9AUHgv374p/MD9Oh+q7zK/1IaR1QgYxhUi3hUFoobPPnh+wJkL+Zwpxywy9p7mWmXmewe0iTRGMps4qZp44ll6K09IVi4Wv3puDxdQGABDn1E5YWKj6PYGaR3qZnoTgdiPrdI+IJoeh7yJYgw3EOxQhBlYA/iujr6qFNL5UpIXZliGd X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(136003)(39860400002)(4326008)(86362001)(44832011)(2906002)(186003)(36756003)(478600001)(110136005)(1076003)(38100700001)(316002)(956004)(55016002)(2616005)(8936002)(8886007)(26005)(7416002)(54906003)(66556008)(5660300002)(16526019)(8676002)(66946007)(6666004)(66476007)(7696005)(83380400001)(52116002); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: e4uymjveWFmNiTKiMEj/SB7woqljYOp82k9CjfpwVQLNANHcNY4FTphVG05orxCir+ugHDoQGyL1Skt5VsoZrhuHXSobjYunVbkWPwhv2J6HfxVLeq4duOL/EKqIvVZJwCrWeLCI5zsXOvk8oFzX2RNAz55KFi93cuYU5xR22FJf0wEIECw2wusfvpOLFoF5OMViEZBNCn2JzA+l47D0dBmV6VchmzJhLqShH78TAoDK7aCg1dxryiMvIqzbyAgFtOxVUqfi9E2MMb7dV6A6d8Gcm3aeonXHyMo1rPL1L244jePww63R1ANde1oBLif57w2YjDI/W75KvfytGTvMzykael7h3RVXsnHH07myrmK/hYAF7diHVnfEjiMJitMV00uqL9SpOHvFbQZSBvsLtn9iZcOxIjXIUdVqSsqWxIrcb3Tl0CySjKX929QeW+5/W4KkKm3Bc3+dvL/NiifZDgYI7Zavj9UB74JVnsxZjR1Ki1odbHxxkumH3sdfxSc/id1HcVar59CAsQiJDqxyGJj29zCI6VzP0qhfPyOfCQqhYIl3ppCTweIQWclcDcc8qPZgRna7qgK9o76ub6CZJakYTcAb5hmlY6M9zVxgHID1Dj/4u2xQo8KZsdd7xsNAbAEFioiObbBewhrDtA3El8pdjiLtFBqf2NIeJ/5geGBFPlSGWoxq5IkPs8EqZ8yJnHyE1hY6HbK33A99yna2S7w+noiGKWMjgqxBgnIC94O80ddSYqKr8pC2QkCHXjH3VN6VapXpilcTH8S811Et0SNEfyYQVsE2vDO5RJdxFCgffK3q7CoYWoI7R0A9rZPiYEURCTasupEv+9EwRp1bafVGku6YLDTXCd3+RW8p3E7oQR6og/3jwwOTd1+5BQnb9jT+R0veHC4TgB5io0OA0yJ8PtWWCo2/SMymG9H+Fd1CiLCYfmbDXFLNKvUya9E1BMT+GaebMYdPLxIRb4OsXkF3ZzbPX1pemwI9iemTWiUS7Ajj1B0DXNdl+576kF4uKXW6mYvwpdI7RKC415/4zNlYjTmYzczJ4uvoKdiCbRPs0/Y0fxenlq60ZXM9lidXVp/KmnY9BBVJnSyTj+FHZ2/TKSBcPNMIOel7vqdtPeOA4jchhGcizkdz8uPBwTFREgdex/3vEibwhaHEII4Ov2f3+QcP6FSWFEeFKPboMVoLQAkXliX9/9OfaCkRPgBa/0JvAySjmOvqUvrWw1G4zFc/PTwKlDJVbkHovh1+2DBSzOpr9txRHkIEd3DgbpZ2zvVVXpKtDJ2MzqjkJaV67HRf3GntxCdOaZaHoCV9h560Uof4SndHhuGIjspWA983 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4cb4b010-1d19-4070-1f59-08d8ea0e8bb5 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2021 13:05:46.9068 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sIl2+K+VK1t43E7LcMXPsmhPmsQdISpRCRlPWMVq3BV401rgapfKHoMnke1kev08+U/J3X+CmBQQP5LI+kAF1g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0826 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We force select CPU_PM and provide asm/cpuidle.h so that we can use CPU IDLE drivers for Linux RISC-V kernel. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/configs/defconfig | 7 +++---- arch/riscv/configs/rv32_defconfig | 4 ++-- arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++ arch/riscv/kernel/process.c | 3 ++- 5 files changed, 38 insertions(+), 7 deletions(-) create mode 100644 arch/riscv/include/asm/cpuidle.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 468642c4e92f..19c9ae909001 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -37,6 +37,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK + select CPU_PM if CPU_IDLE select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT @@ -475,4 +476,10 @@ source "kernel/power/Kconfig" endmenu +menu "CPU Power Management" + +source "drivers/cpuidle/Kconfig" + +endmenu + source "drivers/firmware/Kconfig" diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 6c0625aa96c7..dc4927c0e44b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -13,11 +13,13 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -65,10 +67,9 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_SPI=y CONFIG_SPI_SIFIVE=y +# CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIOLIB=y CONFIG_GPIO_SIFIVE=y -# CONFIG_PTP_1588_CLOCK is not set -CONFIG_POWER_RESET=y CONFIG_DRM=y CONFIG_DRM_RADEON=y CONFIG_DRM_VIRTIO_GPU=y @@ -132,5 +133,3 @@ CONFIG_DEBUG_BLOCK_EXT_DEVT=y # CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y -# CONFIG_SYSFS_SYSCALL is not set -CONFIG_EFI=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 8dd02b842fef..332e43a4a2c3 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -13,12 +13,14 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -67,7 +69,6 @@ CONFIG_HW_RANDOM_VIRTIO=y CONFIG_SPI=y CONFIG_SPI_SIFIVE=y # CONFIG_PTP_1588_CLOCK is not set -CONFIG_POWER_RESET=y CONFIG_DRM=y CONFIG_DRM_RADEON=y CONFIG_DRM_VIRTIO_GPU=y @@ -131,4 +132,3 @@ CONFIG_DEBUG_BLOCK_EXT_DEVT=y # CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y -# CONFIG_SYSFS_SYSCALL is not set diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h new file mode 100644 index 000000000000..71fdc607d4bc --- /dev/null +++ b/arch/riscv/include/asm/cpuidle.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Allwinner Ltd + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_CPUIDLE_H +#define _ASM_RISCV_CPUIDLE_H + +#include +#include + +static inline void cpu_do_idle(void) +{ + /* + * Add mb() here to ensure that all + * IO/MEM accesses are completed prior + * to entering WFI. + */ + mb(); + wait_for_interrupt(); +} + +#endif diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 6f728e731bed..dd2ef18517f4 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -22,6 +22,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -36,7 +37,7 @@ extern asmlinkage void ret_from_kernel_thread(void); void arch_cpu_idle(void) { - wait_for_interrupt(); + cpu_do_idle(); raw_local_irq_enable(); } From patchwork Thu Mar 18 13:05:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 404419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0E5BC433DB for ; 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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM5PR04MB0826.namprd04.prod.outlook.com (2603:10b6:3:100::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18; Thu, 18 Mar 2021 13:06:06 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868%7]) with mapi id 15.20.3955.018; Thu, 18 Mar 2021 13:06:06 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH v3 4/8] RISC-V: Add SBI HSM suspend related defines Date: Thu, 18 Mar 2021 18:35:08 +0530 Message-Id: <20210318130512.1025416-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210318130512.1025416-1-anup.patel@wdc.com> References: <20210318130512.1025416-1-anup.patel@wdc.com> X-Originating-IP: [122.167.155.94] X-ClientProxiedBy: MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.167.155.94) by MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Thu, 18 Mar 2021 13:06:00 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 0eb86908-9e85-4be1-a228-08d8ea0e96e9 X-MS-TrafficTypeDiagnostic: DM5PR04MB0826: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:220; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /5SnMrKD/rlMYBE+8PaxIidfRJIHtmveScoIQyZWerx+8YwgMm/IP0ep/3kWQWN6AAzu2al3M7yjZrN7iYIoshkyP4ImMjxg7lse63RResDR57+oetmu3w48DndJQJjO68Faqnb/i8aM+FaufEdVTsz+vtmLstB0Rkq+6iXgAGypIlQy33W9PXq7uHckjPOTfy4K85w9aZP86f5BfxSBRp7kyl1px3v4C0d9uEOEu4Ke8bjC0I32Yb124yMI+fwTMTNm+PBTVmC37hIBhIpqqMw14emN3Ap5g8eQ01Ce1JVaGl36pzQWSKstfJbf0P1as9aDOLbKN05yYsu/0hL4gdSCdFHBPeKDoIv0DL4oQcjSsUXfDgfsx918H6UTqUZuwVRqMJMEmC16CzEzrxwse2kL59UVUHBZ0hPuElgDvwC6ZU265uZ08epmdSvcB7AmOy2PlxnA/9Tbk4QE3C3zB+W4cbUb34jIRKS2obtyOZAPNCsq7xdqyXsJZVyCPNoFzCeQIhG5k7XY/H8DTSfdn7idRh4UU7PGUwazzDjFK3Q769j61vVafrkgBHl+Sj3HWn3p9/iGzdbJ+ABEirs8hdne9E9DjVcSuD8VjPbt4iM= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(136003)(39860400002)(4326008)(15650500001)(86362001)(44832011)(2906002)(186003)(36756003)(478600001)(110136005)(1076003)(38100700001)(316002)(956004)(55016002)(2616005)(8936002)(8886007)(26005)(7416002)(54906003)(66556008)(5660300002)(16526019)(8676002)(66946007)(66476007)(7696005)(83380400001)(52116002); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: Nn+zBHQek2GdmXrIp8pbiuKMv2kh/dexVk3dIvkUaboI3s7sz2DZdiBiRzkHbhhdwRbPDMWT0HYVE66l1z/chkUhpzXD/XT0ijIuhLXkTlF/rgiF3U+lsstKZNlh/MkM9T1oihJxl9w4WCzKk/NEivJQhEzf8PQ0Zooem5un2YvV77XXZFsfNbi7VaT8QbwsV8KC+wBDDVlXF1bmZ6ERjxcv5fs+o5pyqRtaB7tPUw1QUp/fSJjxv2c/DEajwja1zbyY4qDp+1N7i+I35KxD/GiPUoU1GfdT0Ou+ku7QBicFHZ5NU9fF4iqyptxjNiAutSsfxtfe/uQjx8x7XDvi2gNvpWXolnMTKVW6F5LiH94g47eJEOD0LPidZafSO5s1f5Eb9omsGbJSp/Ab79uBXUHR0NIyet+vTP2WMifvkW8G2Mewla6SPFJMV/cmaf/p7IoE4HSpxtaiy/0rJ+w68KQFehjKy6y6OHstiZlsR7wCxQrxiWFkyIktxWTMSW+oXicnBdGRmLL+68xhTumM075kDZruINhcBT76yojuHD4YEPvfYZNqHfo/UezkQNcmow5ufdY0hRg904+Q7/SffbZVolS3lEDlqQErgLRogSRTxPBwZU21utX0TbMy03ILQe+hQkt6Rr9/ae4oEonJgkw5qU42J3CleGiCk0G6yvGcFzwTu433RY/TFEzKuFCsyX/8PiY7Z9C99ztxTmkm2NCwfVJ8hNn1pzeTXfoSsW9t8O9GaLua231DvMJ0TqrBBlEyHvIT60KSpu4W+oo+WOUemGCCbfOggR5fTMPx1BpQF3NsgxwpeXSTP6xBBgwIj5Hq3JAqXXgWGCJUSBAEAwRlgt0jE0ytYnRs+7sr6OZ4Zus3Fr2dSCPiIa7dw8pnmiCdDJ7b7z2cGmQudTbYpgpANENHCLsIRX0atXf3UeN8xJeVTxCP0N8kqybqTl8oe5z1QU/YyHWLEuanZ6F5m1E9Uau9hN6/9mzhOC9cz88ABu4RvVtlliv/MDV6a9j0cvSJh7gvyG5bsMagFP7k5Nb8zk3LVvHs5+4lH72C7W0WwDpaqWqfRWlZ0mkzMJTnkGUb8y2Uq4nVH5Vh7Hu1SqwuwS0SMa8h/MjcmCctLJ5a/O8WJWZK9IbK9xqguLnPccZTpHzN9/i2QFdCnHL642FyzOsRA2ZbfO6O7UOwSadF2qzVTH+4FcAaNyBLXFGY8+SrYd908kq0160eH2FejoKKR3UuxlfvswKg3+1DEm0BRc4hBoUGJNMKyOlyfe8TVemNAowz4jDmHdP5g2e3gTliyfV+IXAh6H4eJwtvicV+aFhuD7qgIt3gYxMWWcpx X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0eb86908-9e85-4be1-a228-08d8ea0e96e9 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2021 13:06:05.9637 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bSustxIbpvPQFHhC3fKY2pK9G7o0fGmfLgQS2FrmKgeXkwLbamzYY1Jv9NPCVepwi/X+v7wdphbdCHzQS7dmsg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0826 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We add defines related to SBI HSM suspend call and also update HSM states naming as-per latest SBI specification. Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 27 ++++++++++++++++++++++----- arch/riscv/kernel/cpu_ops_sbi.c | 2 +- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 79fa9f28b786..4bdccec77a84 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -62,15 +62,32 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_START = 0, SBI_EXT_HSM_HART_STOP, SBI_EXT_HSM_HART_STATUS, + SBI_EXT_HSM_HART_SUSPEND, }; -enum sbi_hsm_hart_status { - SBI_HSM_HART_STATUS_STARTED = 0, - SBI_HSM_HART_STATUS_STOPPED, - SBI_HSM_HART_STATUS_START_PENDING, - SBI_HSM_HART_STATUS_STOP_PENDING, +enum sbi_hsm_hart_state { + SBI_HSM_STATE_STARTED = 0, + SBI_HSM_STATE_STOPPED, + SBI_HSM_STATE_START_PENDING, + SBI_HSM_STATE_STOP_PENDING, + SBI_HSM_STATE_SUSPENDED, + SBI_HSM_STATE_SUSPEND_PENDING, + SBI_HSM_STATE_RESUME_PENDING, }; +#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff +#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 +#define SBI_HSM_SUSP_PLAT_BASE 0x10000000 + +#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 +#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE +#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK +#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT +#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ + SBI_HSM_SUSP_PLAT_BASE) +#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ + SBI_HSM_SUSP_BASE_MASK) + enum sbi_ext_srst_fid { SBI_EXT_SRST_RESET = 0, }; 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH v3 6/8] cpuidle: Add RISC-V SBI CPU idle driver Date: Thu, 18 Mar 2021 18:35:10 +0530 Message-Id: <20210318130512.1025416-7-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210318130512.1025416-1-anup.patel@wdc.com> References: <20210318130512.1025416-1-anup.patel@wdc.com> X-Originating-IP: [122.167.155.94] X-ClientProxiedBy: MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.167.155.94) by MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Thu, 18 Mar 2021 13:06:12 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 74da500f-7461-4e22-c7ea-08d8ea0e9e40 X-MS-TrafficTypeDiagnostic: DM5PR04MB0826: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: liVaOLrpiO7tPKAdnTxW84cq+L8uxkGF3Bj+ICvzzPmE4TkIflBw7AJDVmuciAdJlOimaF7TkpUFQ9rcIBrFG41oD/IVLwa6Wo3JoTnZBTZ2cFsu5f0AKZxcpDPTTiSAYXCcygO8XJjXwu3SR0A1H/N1Oizge0tMGGyfj5ZzappNiNeWagVJ5XsM1MgechqNiPlnYiVy52gHoXk664irPbXYaXFByhLf/Zelhact1vO7n5zjiBK77albxF7av4j1rBkTtPPcuqRgquHasDx5llCvl/kULB+kgiLR9FCCP9CxusvmDSd8ZKmd3VMavpngmsdiimxfOkaUR8LR36IZKA8p2OPhA5ggk+CtVSXakGtEqN+Q011YStshWNDM3tgaNsttaWWxGI25S1M/QJNY0fm7z7rdHYFAjboWx9c0bjdTgF30UctOM8WXLS2luDbuEBexjymO66hjb0UnEvZTUTPzn3V/CtxwW18F4p/Z9yhrYMUEv1mLkf4UISm6jSNcfqhm1vpZNF2uqxgqVeH59rCnH7PKfYkK3zRgcCyaKmLiXBGCg7t4M8FcMXJ7oxBjJa1ildvTh1L1vNImD81zF2rOLXi7DYpr82T2D3Jdzb5xX84pZecG4pPdlnZbA5YU X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(136003)(39860400002)(4326008)(86362001)(44832011)(30864003)(2906002)(186003)(36756003)(478600001)(110136005)(1076003)(38100700001)(316002)(956004)(55016002)(2616005)(8936002)(8886007)(26005)(7416002)(54906003)(66556008)(5660300002)(16526019)(8676002)(66946007)(66476007)(7696005)(83380400001)(52116002); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: qBQ44aQSG8R2TsM/z453s9TP/P5SyjIWynzln8M/a+xNjT2BWfH3T8Rw25Ef2/pcEZqC/iaYwejq5H9/X0sxWJvNAOLlfc4vX8Id0y55Npabo9xgCwSyS7Ebxg4shSkxL7NXNGCkuHOSD2Nptgv7Kf+xlp9OzbfwpOavGgUVzNRxok0SsgjfbDijfZCbmB633w6B1xpvB1QeWZUcuAKl0+89NYuek5W4U21/8OMJaVK3pOEM6pcgIofkMpJ3WmdLJYE4oivNeuE3znOPrZXBb1vOebvxbrJarfKZYD4geHLFw3SBSbFlRrPh8YsI1Bv4C4nmWrZHWEOGO1OlSszMyshbsC9RYzqTI2RFJI28C13rETQLLPu3zsP+ajoUVtyRL2F2nUH7yM2d4Nt9E44O7Ihz3Lj5PBoKD/zvkz2XH/v2OHoOdCmIL+EFvw4HuJKtFFM+U579SoUIwuAh9tIXsEfp8xB78qLt1wlWgQ+BZVFW+CjysSMh85HorfvFt2WS2ighX/cwgJz0v+kry3fkqnadS4OEXgWVMnDj73xY1chcGE7htplKHK2r/msTvEWsVfvYnCgq+FeSXLI+GfnPzB7PcFxptI4XxUH9/tXuqueQlKzbNd+dvWw7YuhMiD5l3wiVJNALTLEc+xK/99Q9FCE4DBraMyiva9ycHP3CxB2aJbOYq+oz0Ac/2T466Cj0cnUnlewPHMO9f3xZcaEDh7Fhkzg2HIywDdWFVimaSF+ogPyysO39dUvXzvpLh70HWGu6T8x1f6l1m6VaLU1UgXiIDYie85CbiES55faVUQVZHcgGXeaX8cg8Vb1tYMyho3nWfpExO+SJ0d3s8zzvw00f7X9i/ei0yCgix+cEOoMzu+KrcrTPvfJwC9DKDlHRTW59FIAgtcLmk1bPq2+pb5um7qNBnYZHFMSJZoxxR/IZ2Wh7eWxU1TymYlU6zH/Z4wrv0UQ/kL6b/1eUUbivHSUFGQRobtJhcDkRn+S0bO6+QOwbkrqzemJPZcJ1rgUzK7WWgWsN781ZfCkrCaC0CgcYRNuyERJB38YsYN1Os+3np8JIe56+jRSvbpEfVRswt3HElSCSYKPB0kQXmqn367dfPSX0HSKAAwIBGrKCTg8c0anOpa8IJ30f6G9N996MgCbb/CholV5hSrnaK3qkrXLsHGv2OEWBoThIw5yPKCPdzol9iqL5xiW1BK0wE2iom4z7Ce3lnTJF2eNxIn9YoDy4rreOmSGiaOxR1LRbAyBOguYTN2wO4OenVYvPe42GjcOxA4Pg8HIhiWgHeghyb26mqs8QO2ehFl8mzxXCa7v4qaYCZzARslFUTExafdQZ X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74da500f-7461-4e22-c7ea-08d8ea0e9e40 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2021 13:06:18.0121 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cXxfK6dE30gek8OMwJrcjTrps02diMQ0+HSaSavYSg19YVrsADBFPtdFEOFdsXYALlG3QO7QeXL+e7EmCZ9CGA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0826 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The RISC-V SBI HSM extension provides HSM suspend call which can be used by Linux RISC-V to enter platform specific low-power state. This patch adds a CPU idle driver based on RISC-V SBI calls which will populate idle states from device tree and use SBI calls to entry these idle states. Signed-off-by: Anup Patel --- MAINTAINERS | 8 + drivers/cpuidle/Kconfig | 5 + drivers/cpuidle/Kconfig.riscv | 15 + drivers/cpuidle/Makefile | 4 + drivers/cpuidle/cpuidle-sbi.c | 502 ++++++++++++++++++++++++++++++++++ 5 files changed, 534 insertions(+) create mode 100644 drivers/cpuidle/Kconfig.riscv create mode 100644 drivers/cpuidle/cpuidle-sbi.c diff --git a/MAINTAINERS b/MAINTAINERS index aa84121c5611..4954112efdb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4679,6 +4679,14 @@ S: Supported F: drivers/cpuidle/cpuidle-psci.h F: drivers/cpuidle/cpuidle-psci-domain.c +CPUIDLE DRIVER - RISC-V SBI +M: Anup Patel +R: Sandeep Tripathy +L: linux-pm@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/cpuidle/cpuidle-sbi.c + CRAMFS FILESYSTEM M: Nicolas Pitre S: Maintained diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig index f1afe7ab6b54..ff71dd662880 100644 --- a/drivers/cpuidle/Kconfig +++ b/drivers/cpuidle/Kconfig @@ -66,6 +66,11 @@ depends on PPC source "drivers/cpuidle/Kconfig.powerpc" endmenu +menu "RISC-V CPU Idle Drivers" +depends on RISCV +source "drivers/cpuidle/Kconfig.riscv" +endmenu + config HALTPOLL_CPUIDLE tristate "Halt poll cpuidle driver" depends on X86 && KVM_GUEST diff --git a/drivers/cpuidle/Kconfig.riscv b/drivers/cpuidle/Kconfig.riscv new file mode 100644 index 000000000000..78518c26af74 --- /dev/null +++ b/drivers/cpuidle/Kconfig.riscv @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RISC-V CPU Idle drivers +# + +config RISCV_SBI_CPUIDLE + bool "RISC-V SBI CPU idle Driver" + depends on RISCV_SBI + select DT_IDLE_STATES + select CPU_IDLE_MULTIPLE_DRIVERS + select DT_IDLE_GENPD if PM_GENERIC_DOMAINS_OF + help + Select this option to enable RISC-V SBI firmware based CPU idle + driver for RISC-V systems. This drivers also supports hierarchical + DT based layout of the idle state. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 11a26cef279f..a36922c18510 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -35,3 +35,7 @@ obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o # POWERPC drivers obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o + +############################################################################### +# RISC-V drivers +obj-$(CONFIG_RISCV_SBI_CPUIDLE) += cpuidle-sbi.o diff --git a/drivers/cpuidle/cpuidle-sbi.c b/drivers/cpuidle/cpuidle-sbi.c new file mode 100644 index 000000000000..47938fff61e1 --- /dev/null +++ b/drivers/cpuidle/cpuidle-sbi.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V SBI CPU idle driver. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#define pr_fmt(fmt) "cpuidle-sbi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dt_idle_states.h" +#include "dt_idle_genpd.h" + +struct sbi_cpuidle_data { + u32 *states; + struct device *dev; +}; + +struct sbi_domain_state { + bool available; + u32 state; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct sbi_cpuidle_data, sbi_cpuidle_data); +static DEFINE_PER_CPU(struct sbi_domain_state, domain_state); +static bool sbi_cpuidle_use_osi; +static bool sbi_cpuidle_use_cpuhp; +static bool sbi_cpuidle_pd_allow_domain_state; + +static inline void sbi_set_domain_state(u32 state) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + data->available = true; + data->state = state; +} + +static inline u32 sbi_get_domain_state(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + return data->state; +} + +static inline void sbi_clear_domain_state(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + data->available = false; +} + +static inline bool sbi_is_domain_state_available(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + return data->available; +} + +static int sbi_suspend_finisher(unsigned long suspend_type, + unsigned long resume_addr, + unsigned long opaque) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND, + suspend_type, resume_addr, opaque, 0, 0, 0); + + return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0; +} + +static int sbi_suspend(u32 state) +{ + if (state & SBI_HSM_SUSP_NON_RET_BIT) + return cpu_suspend(state, sbi_suspend_finisher); + else + return sbi_suspend_finisher(state, 0, 0); +} + +static int sbi_cpuidle_enter_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + u32 *states = __this_cpu_read(sbi_cpuidle_data.states); + + return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, idx, states[idx]); +} + +static int __sbi_enter_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx, + bool s2idle) +{ + struct sbi_cpuidle_data *data = this_cpu_ptr(&sbi_cpuidle_data); + u32 *states = data->states; + struct device *pd_dev = data->dev; + u32 state; + int ret; + + ret = cpu_pm_enter(); + if (ret) + return -1; + + /* Do runtime PM to manage a hierarchical CPU toplogy. */ + rcu_irq_enter_irqson(); + if (s2idle) + dev_pm_genpd_suspend(pd_dev); + else + pm_runtime_put_sync_suspend(pd_dev); + rcu_irq_exit_irqson(); + + if (sbi_is_domain_state_available()) + state = sbi_get_domain_state(); + else + state = states[idx]; + + ret = sbi_suspend(state) ? -1 : idx; + + rcu_irq_enter_irqson(); + if (s2idle) + dev_pm_genpd_resume(pd_dev); + else + pm_runtime_get_sync(pd_dev); + rcu_irq_exit_irqson(); + + cpu_pm_exit(); + + /* Clear the domain state to start fresh when back from idle. */ + sbi_clear_domain_state(); + return ret; +} + +static int sbi_enter_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + return __sbi_enter_domain_idle_state(dev, drv, idx, false); +} + +static int sbi_enter_s2idle_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int idx) +{ + return __sbi_enter_domain_idle_state(dev, drv, idx, true); +} + +static int sbi_cpuidle_cpuhp_up(unsigned int cpu) +{ + struct device *pd_dev = __this_cpu_read(sbi_cpuidle_data.dev); + + if (pd_dev) + pm_runtime_get_sync(pd_dev); + + return 0; +} + +static int sbi_cpuidle_cpuhp_down(unsigned int cpu) +{ + struct device *pd_dev = __this_cpu_read(sbi_cpuidle_data.dev); + + if (pd_dev) { + pm_runtime_put_sync(pd_dev); + /* Clear domain state to start fresh at next online. */ + sbi_clear_domain_state(); + } + + return 0; +} + +static void sbi_idle_init_cpuhp(void) +{ + int err; + + if (!sbi_cpuidle_use_cpuhp) + return; + + err = cpuhp_setup_state_nocalls(CPUHP_AP_CPU_PM_STARTING, + "cpuidle/sbi:online", + sbi_cpuidle_cpuhp_up, + sbi_cpuidle_cpuhp_down); + if (err) + pr_warn("Failed %d while setup cpuhp state\n", err); +} + +static const struct of_device_id sbi_cpuidle_state_match[] = { + { .compatible = "riscv,idle-state", + .data = sbi_cpuidle_enter_state }, + { }, +}; + +static bool sbi_suspend_state_is_valid(u32 state) +{ + if (state > SBI_HSM_SUSPEND_RET_DEFAULT && + state < SBI_HSM_SUSPEND_RET_PLATFORM) + return false; + if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT && + state < SBI_HSM_SUSPEND_NON_RET_PLATFORM) + return false; + return true; +} + +static int sbi_dt_parse_state_node(struct device_node *np, u32 *state) +{ + int err = of_property_read_u32(np, "riscv,sbi-suspend-param", state); + + if (err) { + pr_warn("%pOF missing riscv,sbi-suspend-param property\n", np); + return err; + } + + if (!sbi_suspend_state_is_valid(*state)) { + pr_warn("Invalid SBI suspend state %#x\n", *state); + return -EINVAL; + } + + return 0; +} + +static int sbi_dt_cpu_init_topology(struct cpuidle_driver *drv, + struct sbi_cpuidle_data *data, + unsigned int state_count, int cpu) +{ + /* Currently limit the hierarchical topology to be used in OSI mode. */ + if (!sbi_cpuidle_use_osi) + return 0; + + data->dev = dt_idle_genpd_attach_cpu(cpu, "sbi"); + if (IS_ERR_OR_NULL(data->dev)) + return PTR_ERR_OR_ZERO(data->dev); + + /* + * Using the deepest state for the CPU to trigger a potential selection + * of a shared state for the domain, assumes the domain states are all + * deeper states. + */ + drv->states[state_count - 1].enter = sbi_enter_domain_idle_state; + drv->states[state_count - 1].enter_s2idle = sbi_enter_s2idle_domain_idle_state; + sbi_cpuidle_use_cpuhp = true; + + return 0; +} + +static int sbi_cpuidle_dt_init_states(struct device *dev, + struct cpuidle_driver *drv, + unsigned int cpu, + unsigned int state_count) +{ + struct sbi_cpuidle_data *data = per_cpu_ptr(&sbi_cpuidle_data, cpu); + struct device_node *state_node; + struct device_node *cpu_node; + u32 *states; + int i, ret; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + return -ENODEV; + + states = devm_kcalloc(dev, state_count, sizeof(*states), GFP_KERNEL); + if (!states) { + ret = -ENOMEM; + goto fail; + } + + /* Parse SBI specific details from state DT nodes */ + for (i = 1; i < state_count; i++) { + state_node = of_get_cpu_state_node(cpu_node, i - 1); + if (!state_node) + break; + + ret = sbi_dt_parse_state_node(state_node, &states[i]); + of_node_put(state_node); + + if (ret) + return ret; + + pr_debug("sbi-state %#x index %d\n", states[i], i); + } + if (i != state_count) { + ret = -ENODEV; + goto fail; + } + + /* Initialize optional data, used for the hierarchical topology. */ + ret = sbi_dt_cpu_init_topology(drv, data, state_count, cpu); + if (ret < 0) + return ret; + + /* Store states in the per-cpu struct. */ + data->states = states; + +fail: + of_node_put(cpu_node); + + return ret; +} + +static void sbi_cpuidle_deinit_cpu(int cpu) +{ + struct sbi_cpuidle_data *data = per_cpu_ptr(&sbi_cpuidle_data, cpu); + + dt_idle_genpd_detach_cpu(data->dev); + sbi_cpuidle_use_cpuhp = false; +} + +static int sbi_cpuidle_init_cpu(struct device *dev, int cpu) +{ + struct cpuidle_driver *drv; + unsigned int state_count = 0; + int ret = 0; + + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); + if (!drv) + return -ENOMEM; + + drv->name = "sbi_cpuidle"; + drv->owner = THIS_MODULE; + drv->cpumask = (struct cpumask *)cpumask_of(cpu); + + /* RISC-V architectural WFI to be represented as state index 0. */ + drv->states[0].enter = sbi_cpuidle_enter_state; + drv->states[0].exit_latency = 1; + drv->states[0].target_residency = 1; + drv->states[0].power_usage = UINT_MAX; + strcpy(drv->states[0].name, "WFI"); + strcpy(drv->states[0].desc, "RISC-V WFI"); + + /* + * If no DT idle states are detected (ret == 0) let the driver + * initialization fail accordingly since there is no reason to + * initialize the idle driver if only wfi is supported, the + * default archictectural back-end already executes wfi + * on idle entry. + */ + ret = dt_init_idle_driver(drv, sbi_cpuidle_state_match, 1); + if (ret <= 0) { + pr_debug("HART%ld: failed to parse DT idle states\n", + cpuid_to_hartid_map(cpu)); + return ret ? : -ENODEV; + } + state_count = ret + 1; /* Include WFI state as well */ + + /* Initialize idle states from DT. */ + ret = sbi_cpuidle_dt_init_states(dev, drv, cpu, state_count); + if (ret) { + pr_err("HART%ld: failed to init idle states\n", + cpuid_to_hartid_map(cpu)); + return ret; + } + + ret = cpuidle_register(drv, NULL); + if (ret) + goto deinit; + + cpuidle_cooling_register(drv); + + return 0; +deinit: + sbi_cpuidle_deinit_cpu(cpu); + return ret; +} + +static int sbi_cpuidle_pd_power_off(struct generic_pm_domain *pd) +{ + struct genpd_power_state *state = &pd->states[pd->state_idx]; + u32 *pd_state; + + if (!state->data) + return 0; + + if (!sbi_cpuidle_pd_allow_domain_state) + return -EBUSY; + + /* OSI mode is enabled, set the corresponding domain state. */ + pd_state = state->data; + sbi_set_domain_state(*pd_state); + + return 0; +} + +static void sbi_cpuidle_domain_sync_state(struct device *dev) +{ + /* + * All devices have now been attached/probed to the PM domain + * topology, hence it's fine to allow domain states to be picked. + */ + sbi_cpuidle_pd_allow_domain_state = true; +} + +static struct dt_idle_genpd_ops sbi_genpd_ops = { + .parse_state_node = sbi_dt_parse_state_node, +}; + +static int sbi_cpuidle_probe(struct platform_device *pdev) +{ + int cpu, ret; + struct cpuidle_driver *drv; + struct cpuidle_device *dev; + struct device_node *np, *pds_node; + + /* Detect OSI support based on CPU DT nodes */ + sbi_cpuidle_use_osi = true; + for_each_possible_cpu(cpu) { + np = of_cpu_device_node_get(cpu); + if (np && + of_find_property(np, "power-domains", NULL) && + of_find_property(np, "power-domain-names", NULL)) { + continue; + } else { + sbi_cpuidle_use_osi = false; + break; + } + } + + if (sbi_cpuidle_use_osi) + sbi_genpd_ops.power_off = sbi_cpuidle_pd_power_off; + + /* Populate generic power domains from DT nodes */ + pds_node = of_find_node_by_path("/cpus/power-domains"); + if (pds_node) { + ret = dt_idle_genpd_probe(&sbi_genpd_ops, pds_node); + of_node_put(pds_node); + if (ret) + return ret; + } + + /* Initialize CPU idle driver for each CPU */ + for_each_possible_cpu(cpu) { + ret = sbi_cpuidle_init_cpu(&pdev->dev, cpu); + if (ret) { + pr_debug("HART%ld: idle driver init failed\n", + cpuid_to_hartid_map(cpu)); + goto out_fail; + } + } + + /* Setup CPU hotplut notifiers */ + sbi_idle_init_cpuhp(); + + pr_info("idle driver registered for all CPUs\n"); + + return 0; + +out_fail: + while (--cpu >= 0) { + dev = per_cpu(cpuidle_devices, cpu); + drv = cpuidle_get_cpu_driver(dev); + cpuidle_unregister(drv); + sbi_cpuidle_deinit_cpu(cpu); + } + + return ret; +} + +static struct platform_driver sbi_cpuidle_driver = { + .probe = sbi_cpuidle_probe, + .driver = { + .name = "sbi-cpuidle", + .sync_state = sbi_cpuidle_domain_sync_state, + }, +}; + +static int __init sbi_cpuidle_init(void) +{ + int ret; + struct platform_device *pdev; + + /* + * The SBI HSM suspend function is only available when: + * 1) SBI version is 0.3 or higher + * 2) SBI HSM extension is available + */ + if ((sbi_spec_version < sbi_mk_version(0, 3)) || + sbi_probe_extension(SBI_EXT_HSM) <= 0) { + pr_info("HSM suspend not available\n"); + return 0; + } + + ret = platform_driver_register(&sbi_cpuidle_driver); + if (ret) + return ret; + + pdev = platform_device_register_simple("sbi-cpuidle", + -1, NULL, 0); + if (IS_ERR(pdev)) { + platform_driver_unregister(&sbi_cpuidle_driver); + return PTR_ERR(pdev); + } + + return 0; +} +device_initcall(sbi_cpuidle_init); From patchwork Thu Mar 18 13:05:12 2021 Content-Type: text/plain; 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Thu, 18 Mar 2021 13:06:29 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH v3 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Date: Thu, 18 Mar 2021 18:35:12 +0530 Message-Id: <20210318130512.1025416-9-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210318130512.1025416-1-anup.patel@wdc.com> References: <20210318130512.1025416-1-anup.patel@wdc.com> X-Originating-IP: [122.167.155.94] X-ClientProxiedBy: MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.167.155.94) by MA1PR01CA0148.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3955.18 via Frontend Transport; Thu, 18 Mar 2021 13:06:24 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c519e9d6-c061-457b-d1f9-08d8ea0ea544 X-MS-TrafficTypeDiagnostic: DM5PR04MB0826: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:849; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kg2XBt+QiTNqyzxa/riM/jfTPJvlFpcmR7DqVBdgpH9LiL2IzkOYirh/q1VhceXMJxNWugQrnmdKKBkMUysfh2ki4O95KZjEFx+Ut1tQiJUykJQJcNWYnEpnDWSNJLLJJSGULFCUYdIhTKMZuPbl0VvkgdAHyfQyn0b83EWD+ehQ0Uj+2eqzOYHtA4DccExjYWRL0khxEx8YVWqQ/uyi8o3iAHz670+rBLhwAKnppgyZYTPp8YmU1pG3YlBg1wSDV0WVXNGHXfePQov8I0RAftNbZz9JTfpfnJefyPnWoPnJ/CPZHIYlS4eOUpGDx6KVAcuXZ7KLGppTy0OguCxU0R/53k5oI714ss01QW7ft4thLOEyr9N+hDqjg/R3ES2F7Dmm7S6W0L9sHw1QQv1aBMG2yJs6YNyEjuv/+WDE1xqhYsUm9S8WyGvhaFRO4c03bfRPwrhv+DeWXuQajQf6taaTK3+q/G5CoDB/fSz4YkHwHeBmeL46kMly5O7y4iic8V1kFO0DfaRDmIYafMWbfQ5o/74eqetxpYPZkwsYgpehCRUsYfxaicZaBvyqd8BuvHxKlz2LtX+T2m82XudXV0Qvi3M3vobuR9ky2RdS1ZKk45kHV8hhfLYX0QWvmp0d X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(136003)(39860400002)(4326008)(86362001)(44832011)(2906002)(186003)(36756003)(478600001)(110136005)(1076003)(38100700001)(316002)(956004)(55016002)(2616005)(8936002)(8886007)(26005)(7416002)(54906003)(66556008)(5660300002)(16526019)(8676002)(66946007)(6666004)(66476007)(7696005)(52116002); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: R6RsAhR5LNGueJwe3aJIV0gw5ggbeL1nA1OGpiBNcegBQsiiRmVfWgGVYUtdqzE3ka56umuupHAjBgleVqhE5efnqXvZWNVbrZtcfinZTDiZEqm+7HWCWgnZXcDv9ZdLD/vzXuWRHpexN4DWdJ8uQpGVgbtIQp7CxWxJ8k9mJxXIMzZdB5DW5+PtCIAjmEPBVpGTiFm9hmSYy4Ox362E85L1v1NEY+U99xVJDriMbwOPvc52apkrwyw1W0WuxUd5DDEl8/aTTLpAkeGhACPc2Rm7iMOcJOzSHunvOuZpQ83keDRF37ZziQGL049oFLjGbmTVO492Gs4rCjOJdfh4e7PfwsG3N8pwyo86dJjXN9IxG6ZFGQPxnbt2Po2GIJ1Y27EMlvci+8qBUtioM7eGzPqnJJothsLpp/VrQQf0y0v6lRGZGNRoLv0Me2hf6ZK8EBrDqpFL6GwihJo89mbsaJ9ML2YbpUJpqgTzlIwrsMrY70hSWSoqx/u7whz9J9LZaqORVhhd6P/uoKnyy0LvJU2ACFdyBD3hatQp6OP6i1pbm14xGkf2JaYV187Y9lCg13W9zHu5Sz8IYbW6IJBR3NVTgBqRc2tbntTuOWP8Ni6bauhqE4LknyRrPMtYvrk1bgWxCoDtJ1/r96IgHciHP0JrNw/c3Bsx92F2Xe6UpqrgiTbcolEAbAJu0v9GhNR4kbk1cY6EXjwKluLrUdBO5sQ2WdWXSXOnPCh4zPwAeZX5Uu1eSRCtyijq1Yv/K9tklHrXRaPqE5AnK1gSmpGEic1Szz8MlNzilK32rJ4yQwZ2pa00K+pAI4I9R+D7kEtXCnafBypvUTMUZwNU7r4CE9+fG/Ab0O7svwkar3/dfZn0TQ2v2fYgXRgJU39tq5OawnMP0pGCIWoQfWBmgIFW3PzJBk2z+QczcYo2jWZJgT1Gl8sd1N3J5GSOQCN21nguiridNQz2zPwt4gqckdXPIxd1uVcCWUwxVEvDF5PP2KrBJttsEqjTrQG59hU885EYBxRNbrC/Dscddft35A2ptm1jBPKM7Slcj6HORdgKphi3TlnOVrciaJ0iLQMr5F3XJKtwdA8eq9kGdTX9zJ/wtjBUqguqEPk02FhkoZKCY4nxBTdlvSkB8XYvwnJKaZjQNwL0egiiJ9k16WiCHL5LbbcOlM9pJG4C98mtfHCvd8ANACiLmtGtPe8O/NUhMgBdwEjJLMfKvbEk91Pxe31HscmOn/CNmpRYM0f8hANvTTpBFB1Z5PtKZhQk/toyM0Sm5xJYSw6/u/H6ZgBQVLfQPDYaEVT5FcFBiE0Jf7lmx5p+yLIg7hTZZbxCj09AsPHx X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: c519e9d6-c061-457b-d1f9-08d8ea0ea544 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2021 13:06:29.7906 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0jVU5bnbWfrZYm8ThksBuPJWNRNYcSw0h43etuAzmtbZqYs1AWinU6OVAE8IzZjwv4WoBkEwkS1yscDEdSy0yA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0826 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test SBI HSM Supend on QEMU. Signed-off-by: Anup Patel --- arch/riscv/Kconfig.socs | 3 +++ arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 7efcece8896c..efdf6fbe18dd 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -19,6 +19,9 @@ config SOC_VIRT select GOLDFISH select RTC_DRV_GOLDFISH if RTC_CLASS select SIFIVE_PLIC + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select RISCV_SBI_CPUIDLE if CPU_IDLE help This enables support for QEMU Virt Machine. diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index dc4927c0e44b..aac26c20bbf5 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -19,6 +19,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 332e43a4a2c3..2285c95e34b3 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y