From patchwork Thu Mar 18 05:40:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 405036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9A39C433E0 for ; Thu, 18 Mar 2021 05:42:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF8D264EED for ; Thu, 18 Mar 2021 05:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229624AbhCRFmH (ORCPT ); Thu, 18 Mar 2021 01:42:07 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:40895 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229519AbhCRFlp (ORCPT ); Thu, 18 Mar 2021 01:41:45 -0400 X-UUID: d2e9787ddddf4ff18bc5197643a03aa6-20210318 X-UUID: d2e9787ddddf4ff18bc5197643a03aa6-20210318 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 938610287; Thu, 18 Mar 2021 13:41:41 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Mar 2021 13:41:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Mar 2021 13:41:40 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Pi-Hsun Shih , Jitao Shi Subject: [v5, 1/2] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid Date: Thu, 18 Mar 2021 13:40:55 +0800 Message-ID: <1616046056-29068-2-git-send-email-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1616046056-29068-1-git-send-email-rex-bc.chen@mediatek.com> References: <1616046056-29068-1-git-send-email-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. Signed-off-by: Pi-Hsun Shih Signed-off-by: Rex-BC Chen Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index b05f900d9322..0b427ad0cd9b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -120,6 +120,7 @@ struct mtk_dpi_yc_limit { struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; + u32 max_clock_khz; bool edge_sel_en; }; @@ -557,9 +558,23 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) mtk_dpi_set_display_mode(dpi, &dpi->mode); } +static enum drm_mode_status +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .attach = mtk_dpi_bridge_attach, .mode_set = mtk_dpi_bridge_mode_set, + .mode_valid = mtk_dpi_bridge_mode_valid, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, }; @@ -668,17 +683,20 @@ static unsigned int mt8183_calculate_factor(int clock) static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 300000, }; static const struct mtk_dpi_conf mt2701_conf = { .cal_factor = mt2701_calculate_factor, .reg_h_fre_con = 0xb0, .edge_sel_en = true, + .max_clock_khz = 150000, }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 100000, }; static int mtk_dpi_probe(struct platform_device *pdev) From patchwork Thu Mar 18 05:40:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 404196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1311C433DB for ; Thu, 18 Mar 2021 05:42:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D88864F06 for ; Thu, 18 Mar 2021 05:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229558AbhCRFmI (ORCPT ); Thu, 18 Mar 2021 01:42:08 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:41043 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229559AbhCRFly (ORCPT ); Thu, 18 Mar 2021 01:41:54 -0400 X-UUID: d1a0ebb0985c430d883ae05cce2b6da5-20210318 X-UUID: d1a0ebb0985c430d883ae05cce2b6da5-20210318 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1556378434; Thu, 18 Mar 2021 13:41:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Mar 2021 13:41:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Mar 2021 13:41:41 +0800 From: Rex-BC Chen To: , CC: , , , , , Rex-BC Chen , Jitao Shi Subject: [v5,2/2] drm/mediatek: mtk_dpi: Add dpi config for mt8192 Date: Thu, 18 Mar 2021 13:40:56 +0800 Message-ID: <1616046056-29068-3-git-send-email-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1616046056-29068-1-git-send-email-rex-bc.chen@mediatek.com> References: <1616046056-29068-1-git-send-email-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add dpi config setting and compatible for MT8192 Signed-off-by: Rex-BC Chen Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 0b427ad0cd9b..88ad58ca4115 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -699,6 +699,12 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, }; +static const struct mtk_dpi_conf mt8192_conf = { + .cal_factor = mt8183_calculate_factor, + .reg_h_fre_con = 0xe0, + .max_clock_khz = 150000, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -819,6 +825,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, + { .compatible = "mediatek,mt8192-dpi", + .data = &mt8192_conf, + }, { }, };