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Tue, 16 Mar 2021 23:20:02 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 23:20:01 +0000 Received: from vdi.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 23:20:00 +0000 From: Liming Sun To: Adrian Hunter , Ulf Hansson , Khalil Blaiech CC: Liming Sun , , Subject: [PATCH v2] mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoC Date: Tue, 16 Mar 2021 19:19:57 -0400 Message-ID: <1615936797-245197-1-git-send-email-limings@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 942f6a75-f928-4e74-b6a9-08d8e8d2067b X-MS-TrafficTypeDiagnostic: DM5PR12MB1628: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:341; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2021 23:20:02.0893 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 942f6a75-f928-4e74-b6a9-08d8e8d2067b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1628 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This commit adds ACPI support in the sdhci-of-dwcmshc driver for BlueField-3 SoC. It has changes to only use the clock hierarchy for Deviec Tree since the clk is not supported by ACPI. Instead, ACPI can define 'clock-frequency' which is parsed by existing sdhci_get_property(). This clock value will be returned in function dwcmshc_get_max_clock(). Signed-off-by: Liming Sun Reviewed-by: Khalil Blaiech --- v1->v2: Changes for comments from Adrian Hunter : - Make changes in sdhci-of-dwcmshc instead. v1: Initial version which was done in sdhci-acpi.c --- drivers/mmc/host/sdhci-of-dwcmshc.c | 50 ++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 59d8d96..bf5037a 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -7,6 +7,7 @@ * Author: Jisheng Zhang */ +#include #include #include #include @@ -51,6 +52,16 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, sdhci_adma_write_desc(host, desc, addr, len, cmd); } +static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + if (pltfm_host->clk) + return sdhci_pltfm_clk_get_max_clock(host); + else + return pltfm_host->clock; +} + static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, struct mmc_request *mrq) { @@ -104,7 +115,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = dwcmshc_set_uhs_signaling, - .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .get_max_clock = dwcmshc_get_max_clock, .reset = sdhci_reset, .adma_write_desc = dwcmshc_adma_write_desc, }; @@ -117,6 +128,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, static int dwcmshc_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct sdhci_pltfm_host *pltfm_host; struct sdhci_host *host; struct dwcmshc_priv *priv; @@ -131,7 +143,7 @@ static int dwcmshc_probe(struct platform_device *pdev) /* * extra adma table cnt for cross 128M boundary handling. */ - extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M); + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); if (extra > SDHCI_MAX_SEGS) extra = SDHCI_MAX_SEGS; host->adma_table_cnt += extra; @@ -139,19 +151,21 @@ static int dwcmshc_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); - pltfm_host->clk = devm_clk_get(&pdev->dev, "core"); - if (IS_ERR(pltfm_host->clk)) { - err = PTR_ERR(pltfm_host->clk); - dev_err(&pdev->dev, "failed to get core clk: %d\n", err); - goto free_pltfm; + if (dev->of_node) { + pltfm_host->clk = devm_clk_get(dev, "core"); + if (IS_ERR(pltfm_host->clk)) { + err = PTR_ERR(pltfm_host->clk); + dev_err(dev, "failed to get core clk: %d\n", err); + goto free_pltfm; + } + err = clk_prepare_enable(pltfm_host->clk); + if (err) + goto free_pltfm; + + priv->bus_clk = devm_clk_get(dev, "bus"); + if (!IS_ERR(priv->bus_clk)) + clk_prepare_enable(priv->bus_clk); } - err = clk_prepare_enable(pltfm_host->clk); - if (err) - goto free_pltfm; - - priv->bus_clk = devm_clk_get(&pdev->dev, "bus"); - if (!IS_ERR(priv->bus_clk)) - clk_prepare_enable(priv->bus_clk); err = mmc_of_parse(host->mmc); if (err) @@ -239,11 +253,19 @@ static int dwcmshc_resume(struct device *dev) }; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); +#ifdef CONFIG_ACPI +static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { + { .id = "MLNXBF30" }, + {} +}; +#endif + static struct platform_driver sdhci_dwcmshc_driver = { .driver = { .name = "sdhci-dwcmshc", .probe_type = PROBE_PREFER_ASYNCHRONOUS, .of_match_table = sdhci_dwcmshc_dt_ids, + .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), .pm = &dwcmshc_pmops, }, .probe = dwcmshc_probe,