From patchwork Tue Mar 16 09:08:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 401893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E00F4C433DB for ; Tue, 16 Mar 2021 09:11:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C4A06500D for ; Tue, 16 Mar 2021 09:11:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232304AbhCPJKv (ORCPT ); Tue, 16 Mar 2021 05:10:51 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:54484 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231753AbhCPJK0 (ORCPT ); Tue, 16 Mar 2021 05:10:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1615885827; x=1647421827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vooiXHRAN/ACdm/aZ2hlaMMqq5pvNY4gIzvnzSpHoY8=; b=U3CM7rnehW4+tkFeFjwx8SFxiF+Gr7IiAyedb9sEyRrmUCeBQ+BNDfKT A+3Wpp+k/yq2U7jUbgmFu9VmpuB8wk0AA3yZKkmWNa1pPObn2hntiQ9GZ GSjEw0EG30TRKtXYqlPMJdgJUldChPVHB9Bh9rtfXUwnYOZxyMCaDa6qt PQV5L2tqyryKDU+BCX3Cql7hpv8jyhdTtkSwYAdFL/IdVvwd3+AXJVVZz l/EIdJR6k/f3czR8llqnlBok+DNMO8Rr9299QdtlROOJ5g3vN9HCz44ZM I41sW44obXZl6tsemVm1M9yW9YiToPoalg8MQ2N4K4YeQMa/a2WWP6xbN g==; IronPort-SDR: C1P9I08+0b/SQzgHmh8kodcfXW7jkqj6ktzbivIJp1NhT4DZzk1mRw8n69rYEMt8Qvy1C9K1e8 9PS8CEK3xqVFtANpo7uoJAnjJJQHmvIdemUbQlLmMZR+CMGKAeBiAZ38KD1tcrU6TyVUwRg5za 62eeOPEbKj+iYD8IXvDPTz/KjMph5+cQgROEIb/azwf6w2U3FuKZ1t5eeE8JIXSfdQXQv3swVB EEkgUNTaxALqamlullf5KXRSc+7iW9V46s6HJ6dVlSRa83yk58Mob4p2d2plUIcSogGxbpWU/Z 0/8= X-IronPort-AV: E=Sophos;i="5.81,251,1610434800"; d="scan'208";a="110146008" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Mar 2021 02:08:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 16 Mar 2021 02:08:51 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Tue, 16 Mar 2021 02:08:49 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , Subject: [PATCH v8 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Date: Tue, 16 Mar 2021 10:08:37 +0100 Message-ID: <20210316090839.3207930-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210316090839.3207930-1-steen.hegelund@microchip.com> References: <20210316090839.3207930-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the Sparx5 reset device driver bindings The driver uses a syscon and an IO range on sparx5 for access to the reset control and the reset status. Sparx5 will no longer use the existing Ocelot chip reset driver, but use this new switch reset driver as it has the reset controller interface that allows the first client to perform the reset on behalf of all the Sparx5 component drivers. Signed-off-by: Steen Hegelund Reviewed-by: Rob Herring --- .../bindings/reset/microchip,rst.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..370579aeeca1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund + - Lars Povlsen + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + items: + - description: global control block registers + + reg-names: + items: + - const: gcb + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + - cpu-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@11010008 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + From patchwork Tue Mar 16 09:08:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 403454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47594C433E9 for ; Tue, 16 Mar 2021 09:11:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1923665001 for ; Tue, 16 Mar 2021 09:11:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231526AbhCPJK5 (ORCPT ); Tue, 16 Mar 2021 05:10:57 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:15506 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231733AbhCPJK0 (ORCPT ); Tue, 16 Mar 2021 05:10:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1615885826; x=1647421826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2Key+2iKL38M/BSOAh81U/K72xgggpmsGs3yXXt3WQE=; b=gzRLJiqwpRewYCpANX2QivgnvO2Adlc0x33Z3+zopAvUwugGQn5x5kuO OzifIOwTWN4VCNYIwKp8AFHELCxBI6j92vMa42J8RfSvmAyLzCGez1dgG nkEH5rPYN9EBF7E/vnEe6PUti2CBBX0ccj8fDB1n5bkCmuFPfk/x9t7F6 cANKLFJsMbLrysxhdi6yO1e9/BL5PnKca5wkcwQS5uTWuM38gEc8o8kGa Ciq1rAlpl5jShlejG3d8AtdPEkkEmgcFY1e5njodWIIM4OOeNZQPljNWr J4diCk1pV9WCVIacOLfDJp0SCuH7bgGa1coI+jExO5Sm7KxgkCJeBBN7H A==; IronPort-SDR: cPYFzHQH/xRbNznlMbvR00a9jgdOzuouB3dWYtHCEGiGh6Dhnj5/OIiOZuqokhrCvMGmEQNgsV M/QssLNFjsaNym+nfKMhuxToefhDNmpLFxDRjV0tEKckaWPYOujihiVTWq38ydm08OtNX/hWx6 Px0FAlh7ytlQDoBMDSzek+1NOVTFuabUi5oqskz0Yp+c5+q5sRvo7AoCLpebJ0IuQ3h453zsWJ zqPz2H5GiB+PuBQWmvFUGZCUSj2IwUNLTEaXl5TEZC4H2j3EZ0JvLrAc9UGdVO6FcFaGuGIa4T xtA= X-IronPort-AV: E=Sophos;i="5.81,251,1610434800"; d="scan'208";a="47683728" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Mar 2021 02:08:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 16 Mar 2021 02:08:56 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Tue, 16 Mar 2021 02:08:54 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , Subject: [PATCH v8 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver Date: Tue, 16 Mar 2021 10:08:39 +0100 Message-ID: <20210316090839.3207930-4-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210316090839.3207930-1-steen.hegelund@microchip.com> References: <20210316090839.3207930-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This provides reset driver support for the Microchip Sparx5 PCB134 and PCB135 reference boards. The Sparx5 Switch will no longer use the Ocelot Chip Reset Driver (with the compatible string "microchip,sparx5-chip-reset"), but use a separate driver that exposes a reset controller interface and has the compatiple string "microchip,sparx5-switch-reset". Eventually the Sparx5 reset support will be removed from the Ocelot chip reset driver. Signed-off-by: Steen Hegelund Reviewed-by: Alexandre Belloni --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 380281f312d8..dc3ada5cf9fc 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -132,9 +132,12 @@ mux: mux-controller { }; }; - reset@611010008 { - compatible = "microchip,sparx5-chip-reset"; + reset: reset-controller@611010008 { + compatible = "microchip,sparx5-switch-reset"; reg = <0x6 0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; }; uart0: serial@600100000 {