From patchwork Tue Mar 16 22:07:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 401732 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4690795jai; Tue, 16 Mar 2021 15:07:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeqSp1eIu6PgTyADNJic7oPcodAV6L9IB4pVcqXRzef0jQPVQq6PxbT712BnaWAIwieFV4 X-Received: by 2002:a25:2c01:: with SMTP id s1mr1322524ybs.170.1615932473379; Tue, 16 Mar 2021 15:07:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615932473; cv=none; d=google.com; s=arc-20160816; b=pCzRs7P39mwEb4Rbogvpe/ZGlGW9n+nhbSMt66QPxUCrEH9vWky3lvwhsSnad8NFvT MM34Lj/Q6dmwVXpJGkRZ840ZC8olfitNSIaaCvDc64wSr+Luf4ZsKQ9KEHkd23yVuLMm /kR0w/vTtUunY4zNss2GW9pKnnUMZemPIBJAMnpnCAWg0/vHj3BnwWZ0uf1vNanso/57 7RGhv415RCxGPvnstiKIEQIUqgfHzOSk2e+graaJrREHwzihWa/wHTjXq9r0gRDxnggZ nV5WVZlS/Y5GqCC3JyeYcgzPL87wDBCRdaHMt2wEjh7oNkLmwbv9qoyi+Cdo0gMRPZmZ llUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7jz3fcXEB4BDzmBRZPOge0wYOIF8sZ5RLLGp4QiFaR4=; b=gSDtvvlry814EVQB8m7VMtwcL/RcPjYdwQ0WxFe7BqxNeNedgu3/ZwgCfGZQU9skob wRloXi9CW47OqJ8+kVV+T6+rDQET90WoH6xUKO/Grs7dhm16EDtJai5INXeI/mcCiqhi eCce35oL6wZB5/vCNFxs4jl1iM/0lrfdjqYc7b6oLCDJzlEEZ8+qM4PV/Yn6+9ZHDLFJ UDiOuSW5yzy4wlLNbNhOZpfYhvbgZ5KXcyUjmafX6DRKvtnFmqTeVOyWiMwYpSflgt5g 1pq1wkHalcpFeK3GB5b+x4GQDSlPv0JIRBn/B2MjlKULqXADO3OBdz5jm/uVH/XXnL/x U6/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tRmeLBiV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id n77sm16546918qkn.128.2021.03.16.15.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 15:07:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/5] tcg: Decode the operand to INDEX_op_mb in dumps Date: Tue, 16 Mar 2021 16:07:31 -0600 Message-Id: <20210316220735.2048137-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> References: <20210316220735.2048137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/tcg.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 2991112829..23a94d771c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2415,6 +2415,85 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) arg_label(op->args[k])->id); i++, k++; break; + case INDEX_op_mb: + { + TCGBar membar = op->args[k]; + const char *b_op, *m_op; + + switch (membar & TCG_BAR_SC) { + case 0: + b_op = "none"; + break; + case TCG_BAR_LDAQ: + b_op = "acq"; + break; + case TCG_BAR_STRL: + b_op = "rel"; + break; + case TCG_BAR_SC: + b_op = "seq"; + break; + default: + g_assert_not_reached(); + } + + switch (membar & TCG_MO_ALL) { + case 0: + m_op = "none"; + break; + case TCG_MO_LD_LD: + m_op = "rr"; + break; + case TCG_MO_LD_ST: + m_op = "rw"; + break; + case TCG_MO_ST_LD: + m_op = "wr"; + break; + case TCG_MO_ST_ST: + m_op = "ww"; + break; + case TCG_MO_LD_LD | TCG_MO_LD_ST: + m_op = "rr+rw"; + break; + case TCG_MO_LD_LD | TCG_MO_ST_LD: + m_op = "rr+wr"; + break; + case TCG_MO_LD_LD | TCG_MO_ST_ST: + m_op = "rr+ww"; + break; + case TCG_MO_LD_ST | TCG_MO_ST_LD: + m_op = "rw+wr"; + break; + case TCG_MO_LD_ST | TCG_MO_ST_ST: + m_op = "rw+ww"; + break; + case TCG_MO_ST_LD | TCG_MO_ST_ST: + m_op = "wr+ww"; + break; + case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_LD: + m_op = "rr+rw+wr"; + break; + case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST: + m_op = "rr+rw+ww"; + break; + case TCG_MO_LD_LD | TCG_MO_ST_LD | TCG_MO_ST_ST: + m_op = "rr+wr+ww"; + break; + case TCG_MO_LD_ST | TCG_MO_ST_LD | TCG_MO_ST_ST: + m_op = "rw+wr+ww"; + break; + case TCG_MO_ALL: + m_op = "all"; + break; + default: + g_assert_not_reached(); + } + + col += qemu_log("%s%s:%s", (k ? "," : ""), b_op, m_op); + i++, k++; + } + break; default: break; } From patchwork Tue Mar 16 22:07:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 401735 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4698937jai; Tue, 16 Mar 2021 15:22:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/Ryh7ZIi5lDFTgf7pgakTJ1Md3oiVH9o10/uEgp0zB7UPnDk5cngrVLkKSSBEynLWh/LN X-Received: by 2002:a25:3cd:: with SMTP id 196mr1514018ybd.456.1615933321688; Tue, 16 Mar 2021 15:22:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615933321; cv=none; d=google.com; s=arc-20160816; b=ovSn46v4E7r7Sw2vxRlS8PdIlMSiYxNzhleTsO28TITF/MK98up9OPgj48nlYKtWu3 QQ1DKJS4yyUIUeeatf3PbPpfScLlY3duN16HOdXWG3mPg9pIr26/OisWQ4GUJyoZezFE tGWw0um6tGcu2EB8wxez0wA2LsbnrNMBjdg+Oos8jsrHG4WIPaexHJIAL4+ORZyPxT7l Sq7mB2bg6Kyfx1ZB6oHBVe9qOPbpIS5noZieaSmg5WWUaFSEAt7TX+xM31ui8iPrpeEk WeBJnEZPQ1FzJFgx+KQ4b+kk/WFA+pSi4BC4VYRlPMGm01vO8AyRPiSdHgRzuflurAnV uGfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yPAAjWDyig+xlHGQhaJtz36xF4S8yrbGq7nm4d8cwIk=; b=Yns/MBIHnzVDmhxUkIZR/CTg63Ja656We67aGB3sSnyMdeJssBeh7Do5LBesNXHTiJ YAX/0tVU6QaL8QKoU69L321EH+38c67DjuRD4qpUU5YCf9tlOlDKXRvRzO4xx7OX1D2G CvGsW+egBiSqQUNT6YiiOXNfF9BEiBYECw6QQbAnAwy1SQj6rpQSoixElSKzHH/Yio8j V2urce1IsudS37enT5PhoaQfWOsSKBAs7Dh2t6rgVyTaZ5CQ9YeOe5xZNDNiAUYU/Im1 He1DocStdrknMxDcV1srDtzQhCqZEYR47lsmgu9wC6NMZPfidvLeh4aNAd4CgVmdSvjS W+zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vLhsWJLZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id n77sm16546918qkn.128.2021.03.16.15.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 15:07:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/5] tcg: Do not elide memory barriers for CF_PARALLEL Date: Tue, 16 Mar 2021 16:07:32 -0600 Message-Id: <20210316220735.2048137-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> References: <20210316220735.2048137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The virtio devices require proper memory ordering between the vcpus and the iothreads. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 70475773f4..76dc7d8dc5 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -97,9 +97,13 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx->tb_cflags & CF_PARALLEL) { - tcg_gen_op1(INDEX_op_mb, mb_type); - } + /* + * It is tempting to elide the barrier in a single-threaded context + * (i.e. !(tb_cflags & CF_PARALLEL)), however, even with a single cpu + * we have i/o threads running in parallel, and lack of memory order + * can result in e.g. virtio queue entries being read incorrectly. + */ + tcg_gen_op1(INDEX_op_mb, mb_type); } /* 32 bit ops */ From patchwork Tue Mar 16 22:07:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 401736 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4699542jai; Tue, 16 Mar 2021 15:23:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtO4eyQ8SeduQqewQZ/tL/7aRAtM82TltH8uyUCnW/WLqpB95woXLEKMq9zaRGGTfgRlc3 X-Received: by 2002:a25:b206:: with SMTP id i6mr1260163ybj.499.1615933389101; Tue, 16 Mar 2021 15:23:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615933389; cv=none; d=google.com; s=arc-20160816; b=ZkHycq7GmfArwgZNF2Xvj85Tlxo/+zdHKkdj5xHcXuEDy5ZQygBwV8q76CxmOz4NBv jOyuriqfquQlzVbnYXdqVy141B0FIEn5R/dTxh+kozqaIw5z0BaR5tLto1LN0RjYvmoi sEHOrz24OO0JVAkjLACsQUnGIhJhoWCOlPgCw+42tXBFS05Ofswy02g+RkfUYlZhhCrY Kag8paibiJm6q/XXQOjGHWhq+g1DstyyQpMubNMn28z52i3KRSH0jZLRUj3gqrsgwB39 SbY5wc/0thkP+4RXlgcY9xY6D6boVQ9X4YxAGEULCGCcBTQ1/FAd2VbY7xJAsQQ6ADC5 m1gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iXb9BKT3Yzc//BOI+yvFmKmzMLx3jVzBVYijM2bLOWU=; b=fZy8CG9fZ+heYYHoRuNYlgDld1zKf7QQuC7RNxhl9yM3W5bllnXSuOjSz9Ckg6yJo9 wl67/JXsHIzjZFdIQwcHKpMCaUL3kVDfbh3zjCqeVI91mCYbOX+nQmzEcqJlVOYwkZpM 9Dw1RBxwjtjjACbje5mG83srPue33dEza62G4jH3dp+SBDrcCLMNgxVTL2/RrkUYu9GU SoXUjCqmK2msV7GUNMf4Xcw1lt1lIxk1DitaGbKidH+x9H2+sK5nbGGSRHfU9vQQsqUj jrmoyDD4Z5zyFt7wuWZULIN4+z194RbFXy4hDMomoyZtWJCjNsycRgNVqktNv3YEtjmB F7CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FzWY50mQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id n77sm16546918qkn.128.2021.03.16.15.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 15:07:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/5] tcg: Elide memory barriers implied by the host memory model Date: Tue, 16 Mar 2021 16:07:33 -0600 Message-Id: <20210316220735.2048137-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> References: <20210316220735.2048137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x834.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reduce the set of required barriers to those needed by the host right from the beginning. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 76dc7d8dc5..c8501508c2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -102,8 +102,13 @@ void tcg_gen_mb(TCGBar mb_type) * (i.e. !(tb_cflags & CF_PARALLEL)), however, even with a single cpu * we have i/o threads running in parallel, and lack of memory order * can result in e.g. virtio queue entries being read incorrectly. + * + * That said, we can elide anything which the host provides for free. */ - tcg_gen_op1(INDEX_op_mb, mb_type); + mb_type &= ~TCG_TARGET_DEFAULT_MO; + if (mb_type & TCG_MO_ALL) { + tcg_gen_op1(INDEX_op_mb, mb_type); + } } /* 32 bit ops */ From patchwork Tue Mar 16 22:07:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 401737 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4700824jai; Tue, 16 Mar 2021 15:25:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0i8v8COUzF/AK1GY4tzqjH570C0exL0+Egm6e/+uU65+ufOhEyocT0GsWKoCH/aRv6InJ X-Received: by 2002:a5b:5c7:: with SMTP id w7mr1431975ybp.164.1615933534246; Tue, 16 Mar 2021 15:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615933534; cv=none; d=google.com; s=arc-20160816; b=SECS3VqScPL4ZNcGcBRyzmfyqi03tPPt62x6RwUyRt5Jw07CFOTdJfG6aJv3BED2UV Df/ebPvZ5Lg0VuycDLif07BnvxJgEEYu/5oNRUyPr4aB+zFkp1N5fJX41/AAHK70SPvF L1E2sz0VpxvO8rZg4cUzUKChVb8PUSuDTAGItLkd3YbV5Y1RAzSjeKwfQbIKIsb+GBoj rYMYaLxb+LSrfzIiIEk9EakFrXJu3GosFuIfHgbHMoXHmk3z+7oNhKl4KNumZd2Ga/5G kPJB2j5bK/FkuieQ/pI478ZcdDSqTWVJlulAo0UNnv9eFqT7zjz1ViHQH5NOO2Zg0oRR TJOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4FGwbzRDCgp0mZG0M4BZazahJWTIBClTRPajuLNeTjw=; b=hK0DXxH/gs5UBugCjHsU018b+ZYDn5f6EhpqWubJwd7l/spH3bIpgWMp2vBRjbTYzv feQJStaGhMmpE0Yx8ZrNoGflSn9V3cKCb8XKzjlymvIDipDZkiU9e63GlbH/qgMX8LUu b/ac1ToupfhoA2k2ZUFR3ggZwz4nJgeWXWpquxAtsGM3oWfEnwwkysh06h2SMxaCV3ki B45ZfvCU18IAEihYH8WvKccHYXyQZNpxgmqYMWGGoS4S9hW9o8EOvdhZNqSTct+pX0pK Vvi+q1siSSCnPE5Sqwl/3IkEx0yhDEooVuCprrr27ta8vab2+9k6WPOSzBLum3Obc8qz cjVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ei+lY0aN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id n77sm16546918qkn.128.2021.03.16.15.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 15:07:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/5] tcg: Create tcg_req_mo Date: Tue, 16 Mar 2021 16:07:34 -0600 Message-Id: <20210316220735.2048137-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> References: <20210316220735.2048137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out the logic to emit a host memory barrier in response to a guest memory operation. Do not provide a true default for TCG_GUEST_DEFAULT_MO because the defined() check will still be useful for determining if a guest has been updated for MTTCG. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 20 ++++++++++++++++++++ accel/tcg/tcg-all.c | 6 +----- tcg/tcg-op.c | 8 +------- 3 files changed, 22 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0f0695e90d..395b3b6964 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1245,6 +1245,26 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) return oi & 15; } +/** + * tcg_req_mo: + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + * + * If TCG_GUEST_DEFAULT_MO is not defined, assume that the + * guest requires strict alignment. + * + * This is a macro so that it's constant even without optimization. + */ +#ifdef TCG_GUEST_DEFAULT_MO +# define tcg_req_mo(type) \ + ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) +#else +# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) +#endif + /** * tcg_qemu_tb_exec: * @env: pointer to CPUArchState for the CPU diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index e378c2db73..6ae51e3476 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -69,11 +69,7 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, static bool check_tcg_memory_orders_compatible(void) { -#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) - return (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) == 0; -#else - return false; -#endif + return tcg_req_mo(TCG_MO_ALL) == 0; } static bool default_mttcg_enabled(void) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c8501508c2..12fc8a1b17 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2796,13 +2796,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, static void tcg_gen_req_mo(TCGBar type) { -#ifdef TCG_GUEST_DEFAULT_MO - type &= TCG_GUEST_DEFAULT_MO; -#endif - type &= ~TCG_TARGET_DEFAULT_MO; - if (type) { - tcg_gen_mb(type | TCG_BAR_SC); - } + tcg_gen_mb(tcg_req_mo(type) | TCG_BAR_SC); } static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) From patchwork Tue Mar 16 22:07:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 401733 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4691348jai; Tue, 16 Mar 2021 15:08:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSa1es3MjZteQNtPTGXIm9Ed+dReYmTLGwVPxv4VaFm+4lbZYMJP4C6PW6YF+nCRREe4/2 X-Received: by 2002:a25:ab32:: with SMTP id u47mr1366507ybi.46.1615932525797; Tue, 16 Mar 2021 15:08:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615932525; cv=none; d=google.com; s=arc-20160816; b=bqjIUu9Zq2Ify1+lo50SeadIgLozAN4g6C/86C4IGkBdY4t5YP4jO0CP0z41JccjRn S4PitDlVdE7dAD54QuMORhei3hf1xJg9byFB/6BPLZjdCga+GC+fujS3/lK+Agtvfael HSXg910TfdHwBqVCYi/kbAey2mg9krmHfHVgArmHWWOyrQ84JZlxxCAH0zriWnTM4MYD 5Kz2MQaFlPca2BQdxkn2AQEWpbbaktxRrk7cXNMXwapdtiP/BNeUyaP8DtjgPuKOem9A uufkUdUq74XYSYa6RyhOTbUG7E44VtQaPlp/XlQoskRgLzjbhrEZMnGwV709jj/ame0U Yrjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MNghjrViS6cE79RQ44HsI/7snhIGTmTSZYfbhec9QPE=; b=m9dd34U/hidqWZVkjf9Cc/OnrxZbJTVwoKgARS6mLEE7+5fipPyw2OhQuChyC9KwYf PxKcCUFLHjGNwKCNp5qfyn9/7+KAGRDn7ph88ZlYFcVLnXIlAwMy3BdC5HrXWQ9/Dx5Y O1Y9XjaQMrXH0gYwE8pjsAtvdPZ9xZ/5G+EIlcJB/7EeTHpEMXe8ri9LVVRgY3TUVkEK 7svCyOhXUdlsiTp2VV/UwfGzJ5TlSCuNNO9sajqpiY3pxJrvonAGSmInC2pU8KVva263 Wfvhmy48+Vbx8P448kjM4giftvnWB4LQZ5Deqf3t10GjtxQMddrybrkSmqaDQGwU9Oyp fSvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z64y44Hm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id n77sm16546918qkn.128.2021.03.16.15.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 15:07:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/5] tcg: Add host memory barriers to cpu_ldst.h interfaces Date: Tue, 16 Mar 2021 16:07:35 -0600 Message-Id: <20210316220735.2048137-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210316220735.2048137-1-richard.henderson@linaro.org> References: <20210316220735.2048137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Bring the majority of helpers into line with the rest of tcg in respecting guest memory ordering. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 7 +++++++ accel/tcg/cputlb.c | 2 ++ accel/tcg/user-exec.c | 17 +++++++++++++++++ 3 files changed, 26 insertions(+) -- 2.25.1 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ce6ce82618..f0ab79fe3c 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -169,6 +169,13 @@ void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); +#define cpu_req_mo(type) \ + do { \ + if (tcg_req_mo(type)) { \ + smp_mb(); \ + } \ + } while (0) + #if defined(CONFIG_USER_ONLY) extern __thread uintptr_t helper_retaddr; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270..a3503eaa71 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2100,6 +2100,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr, meminfo = trace_mem_get_info(op, mmu_idx, false); trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); op &= ~MO_SIGN; oi = make_memop_idx(op, mmu_idx); ret = full_load(env, addr, oi, retaddr); @@ -2542,6 +2543,7 @@ cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, meminfo = trace_mem_get_info(op, mmu_idx, true); trace_guest_mem_before_exec(env_cpu(env), addr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); oi = make_memop_idx(op, mmu_idx); store_helper(env, addr, val, oi, retaddr, op); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0d8cc27b21..34f6dfcef4 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -843,6 +843,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldub_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -854,6 +855,7 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldsb_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -865,6 +867,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = lduw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -876,6 +879,7 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldsw_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -887,6 +891,7 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldl_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -898,6 +903,7 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldq_be_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -909,6 +915,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = lduw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -920,6 +927,7 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldsw_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -931,6 +939,7 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldl_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -942,6 +951,7 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); ret = ldq_le_p(g2h(env_cpu(env), ptr)); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); return ret; @@ -1052,6 +1062,7 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stb_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } @@ -1061,6 +1072,7 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stw_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } @@ -1070,6 +1082,7 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stl_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } @@ -1079,6 +1092,7 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stq_be_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } @@ -1088,6 +1102,7 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stw_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } @@ -1097,6 +1112,7 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stl_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); } @@ -1106,6 +1122,7 @@ void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); + cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); stq_le_p(g2h(env_cpu(env), ptr), val); qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); }