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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/17] target/ppc: Move helper_regs.h functions out-of-line Date: Mon, 15 Mar 2021 12:45:59 -0600 Message-Id: <20210315184615.1985590-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the functions to a new file, helper_regs.c. Note int_helper.c was relying on helper_regs.h to indirectly include qemu/log.h. Signed-off-by: Richard Henderson --- target/ppc/helper_regs.h | 184 ++---------------------------------- target/ppc/helper_regs.c | 197 +++++++++++++++++++++++++++++++++++++++ target/ppc/int_helper.c | 1 + target/ppc/meson.build | 1 + 4 files changed, 207 insertions(+), 176 deletions(-) create mode 100644 target/ppc/helper_regs.c -- 2.25.1 Reviewed-by: Cédric Le Goater diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index efcc903427..4148a442b3 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -20,184 +20,16 @@ #ifndef HELPER_REGS_H #define HELPER_REGS_H -#include "qemu/main-loop.h" -#include "exec/exec-all.h" -#include "sysemu/kvm.h" +void hreg_swap_gpr_tgpr(CPUPPCState *env); +void hreg_compute_mem_idx(CPUPPCState *env); +void hreg_compute_hflags(CPUPPCState *env); +void cpu_interrupt_exittb(CPUState *cs); +int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); -/* Swap temporary saved registers with GPRs */ -static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) -{ - target_ulong tmp; - - tmp = env->gpr[0]; - env->gpr[0] = env->tgpr[0]; - env->tgpr[0] = tmp; - tmp = env->gpr[1]; - env->gpr[1] = env->tgpr[1]; - env->tgpr[1] = tmp; - tmp = env->gpr[2]; - env->gpr[2] = env->tgpr[2]; - env->tgpr[2] = tmp; - tmp = env->gpr[3]; - env->gpr[3] = env->tgpr[3]; - env->tgpr[3] = tmp; -} - -static inline void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - -static inline void hreg_compute_hflags(CPUPPCState *env) -{ - target_ulong hflags_mask; - - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; - /* Merge with hflags coming from other registers */ - env->hflags |= env->hflags_nmsr; -} - -static inline void cpu_interrupt_exittb(CPUState *cs) -{ - if (!kvm_enabled()) { - return; - } - - if (!qemu_mutex_iothread_locked()) { - qemu_mutex_lock_iothread(); - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); - qemu_mutex_unlock_iothread(); - } else { - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); - } -} - -static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, - int alter_hv) -{ - int excp; -#if !defined(CONFIG_USER_ONLY) - CPUState *cs = env_cpu(env); -#endif - - excp = 0; - value &= env->msr_mask; -#if !defined(CONFIG_USER_ONLY) - /* Neither mtmsr nor guest state can alter HV */ - if (!alter_hv || !(env->msr & MSR_HVB)) { - value &= ~MSR_HVB; - value |= env->msr & MSR_HVB; - } - if (((value >> MSR_IR) & 1) != msr_ir || - ((value >> MSR_DR) & 1) != msr_dr) { - cpu_interrupt_exittb(cs); - } - if ((env->mmu_model & POWERPC_MMU_BOOKE) && - ((value >> MSR_GS) & 1) != msr_gs) { - cpu_interrupt_exittb(cs); - } - if (unlikely((env->flags & POWERPC_FLAG_TGPR) && - ((value ^ env->msr) & (1 << MSR_TGPR)))) { - /* Swap temporary saved registers with GPRs */ - hreg_swap_gpr_tgpr(env); - } - if (unlikely((value >> MSR_EP) & 1) != msr_ep) { - /* Change the exception prefix on PowerPC 601 */ - env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; - } - /* - * If PR=1 then EE, IR and DR must be 1 - * - * Note: We only enforce this on 64-bit server processors. - * It appears that: - * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS - * exploits it. - * - 64-bit embedded implementations do not need any operation to be - * performed when PR is set. - */ - if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { - value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); - } -#endif - env->msr = value; - hreg_compute_hflags(env); -#if !defined(CONFIG_USER_ONLY) - if (unlikely(msr_pow == 1)) { - if (!env->pending_interrupts && (*env->check_pow)(env)) { - cs->halted = 1; - excp = EXCP_HALTED; - } - } -#endif - - return excp; -} - -#if !defined(CONFIG_USER_ONLY) -static inline void check_tlb_flush(CPUPPCState *env, bool global) -{ - CPUState *cs = env_cpu(env); - - /* Handle global flushes first */ - if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { - env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; - env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; - tlb_flush_all_cpus_synced(cs); - return; - } - - /* Then handle local ones */ - if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { - env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; - tlb_flush(cs); - } -} -#else +#ifdef CONFIG_USER_ONLY static inline void check_tlb_flush(CPUPPCState *env, bool global) { } +#else +void check_tlb_flush(CPUPPCState *env, bool global); #endif #endif /* HELPER_REGS_H */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c new file mode 100644 index 0000000000..5e18232b84 --- /dev/null +++ b/target/ppc/helper_regs.c @@ -0,0 +1,197 @@ +/* + * PowerPC emulation special registers manipulation helpers for qemu. + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "sysemu/kvm.h" +#include "helper_regs.h" + +/* Swap temporary saved registers with GPRs */ +void hreg_swap_gpr_tgpr(CPUPPCState *env) +{ + target_ulong tmp; + + tmp = env->gpr[0]; + env->gpr[0] = env->tgpr[0]; + env->tgpr[0] = tmp; + tmp = env->gpr[1]; + env->gpr[1] = env->tgpr[1]; + env->tgpr[1] = tmp; + tmp = env->gpr[2]; + env->gpr[2] = env->tgpr[2]; + env->tgpr[2] = tmp; + tmp = env->gpr[3]; + env->gpr[3] = env->tgpr[3]; + env->tgpr[3] = tmp; +} + +void hreg_compute_mem_idx(CPUPPCState *env) +{ + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + if (env->mmu_model & POWERPC_MMU_BOOKE) { + env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; + env->immu_idx += msr_is ? 2 : 0; + env->dmmu_idx += msr_ds ? 2 : 0; + env->immu_idx += msr_gs ? 4 : 0; + env->dmmu_idx += msr_gs ? 4 : 0; + } else { + env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; + env->immu_idx += msr_ir ? 0 : 2; + env->dmmu_idx += msr_dr ? 0 : 2; + env->immu_idx += msr_hv ? 4 : 0; + env->dmmu_idx += msr_hv ? 4 : 0; + } +} + +void hreg_compute_hflags(CPUPPCState *env) +{ + target_ulong hflags_mask; + + /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ + hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | + (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); + hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; + hreg_compute_mem_idx(env); + env->hflags = env->msr & hflags_mask; + /* Merge with hflags coming from other registers */ + env->hflags |= env->hflags_nmsr; +} + +void cpu_interrupt_exittb(CPUState *cs) +{ + if (!kvm_enabled()) { + return; + } + + if (!qemu_mutex_iothread_locked()) { + qemu_mutex_lock_iothread(); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + qemu_mutex_unlock_iothread(); + } else { + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + } +} + +int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) +{ + int excp; +#if !defined(CONFIG_USER_ONLY) + CPUState *cs = env_cpu(env); +#endif + + excp = 0; + value &= env->msr_mask; +#if !defined(CONFIG_USER_ONLY) + /* Neither mtmsr nor guest state can alter HV */ + if (!alter_hv || !(env->msr & MSR_HVB)) { + value &= ~MSR_HVB; + value |= env->msr & MSR_HVB; + } + if (((value >> MSR_IR) & 1) != msr_ir || + ((value >> MSR_DR) & 1) != msr_dr) { + cpu_interrupt_exittb(cs); + } + if ((env->mmu_model & POWERPC_MMU_BOOKE) && + ((value >> MSR_GS) & 1) != msr_gs) { + cpu_interrupt_exittb(cs); + } + if (unlikely((env->flags & POWERPC_FLAG_TGPR) && + ((value ^ env->msr) & (1 << MSR_TGPR)))) { + /* Swap temporary saved registers with GPRs */ + hreg_swap_gpr_tgpr(env); + } + if (unlikely((value >> MSR_EP) & 1) != msr_ep) { + /* Change the exception prefix on PowerPC 601 */ + env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; + } + /* + * If PR=1 then EE, IR and DR must be 1 + * + * Note: We only enforce this on 64-bit server processors. + * It appears that: + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS + * exploits it. + * - 64-bit embedded implementations do not need any operation to be + * performed when PR is set. + */ + if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { + value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); + } +#endif + env->msr = value; + hreg_compute_hflags(env); +#if !defined(CONFIG_USER_ONLY) + if (unlikely(msr_pow == 1)) { + if (!env->pending_interrupts && (*env->check_pow)(env)) { + cs->halted = 1; + excp = EXCP_HALTED; + } + } +#endif + + return excp; +} + +#ifndef CONFIG_USER_ONLY +void check_tlb_flush(CPUPPCState *env, bool global) +{ + CPUState *cs = env_cpu(env); + + /* Handle global flushes first */ + if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { + env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; + env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; + tlb_flush_all_cpus_synced(cs); + return; + } + + /* Then handle local ones */ + if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { + env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; + tlb_flush(cs); + } +} +#endif diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 429de28494..a44c2d90ea 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" +#include "qemu/log.h" #include "exec/helper-proto.h" #include "crypto/aes.h" #include "fpu/softfloat.h" diff --git a/target/ppc/meson.build b/target/ppc/meson.build index bbfef90e08..4079d01ee3 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -6,6 +6,7 @@ ppc_ss.add(files( 'excp_helper.c', 'fpu_helper.c', 'gdbstub.c', + 'helper_regs.c', 'int_helper.c', 'mem_helper.c', 'misc_helper.c', From patchwork Mon Mar 15 18:46:00 2021 Content-Type: text/plain; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/17] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags Date: Mon, 15 Mar 2021 12:46:00 -0600 Message-Id: <20210315184615.1985590-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Keep all hflags computation in one place, as this will be especially important later. Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when LE should be taken from HID0. This appears to be set if and only if POWERPC_FLAG_RTC_CLK is set, but we're not short of bits and having both names will avoid confusion. Note that this was the only user of hflags_nmsr, so we can perform a straight assignment rather than mask and set. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 2 ++ target/ppc/helper_regs.c | 13 +++++++++++-- target/ppc/misc_helper.c | 8 +++----- target/ppc/translate_init.c.inc | 4 ++-- 4 files changed, 18 insertions(+), 9 deletions(-) -- 2.25.1 Reviewed-by: Cédric Le Goater diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..061d2eed1b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -581,6 +581,8 @@ enum { POWERPC_FLAG_TM = 0x00100000, /* Has SCV (ISA 3.00) */ POWERPC_FLAG_SCV = 0x00200000, + /* Has HID0 for LE bit (601) */ + POWERPC_FLAG_HID0_LE = 0x00400000, }; /*****************************************************************************/ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5e18232b84..95b9aca61f 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -96,8 +96,17 @@ void hreg_compute_hflags(CPUPPCState *env) hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env); env->hflags = env->msr & hflags_mask; - /* Merge with hflags coming from other registers */ - env->hflags |= env->hflags_nmsr; + + if (env->flags & POWERPC_FLAG_HID0_LE) { + /* + * Note that MSR_LE is not set in env->msr_mask for this cpu, + * and so will never be set in msr or hflags at this point. + */ + uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); + env->hflags |= le << MSR_LE; + /* Retain for backward compatibility with migration. */ + env->hflags_nmsr = le << MSR_LE; + } } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 5d6e0de396..63e3147eb4 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -194,16 +194,14 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) target_ulong hid0; hid0 = env->spr[SPR_HID0]; + env->spr[SPR_HID0] = (uint32_t)val; + if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ - env->hflags &= ~(1 << MSR_LE); - env->hflags_nmsr &= ~(1 << MSR_LE); - env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); - env->hflags |= env->hflags_nmsr; + hreg_compute_hflags(env); qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } - env->spr[SPR_HID0] = (uint32_t)val; } void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index c03a7c4f52..049d76cfd1 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -5441,7 +5441,7 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data) pcc->excp_model = POWERPC_EXCP_601; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; } #define POWERPC_MSRR_601v (0x0000000000001040ULL) @@ -5485,7 +5485,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) #endif pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; } static void init_proc_602(CPUPPCState *env) From patchwork Mon Mar 15 18:46:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400532 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3679022jai; Mon, 15 Mar 2021 11:58:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykASwP7ex/DFLSD7/sDtp0xb8EW5PaZUpRVU6qyEKzWsbjPa9tlXzBLxokHVyfFe04gTUN X-Received: by 2002:a92:d981:: with SMTP id r1mr837747iln.98.1615834729139; Mon, 15 Mar 2021 11:58:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615834729; cv=none; d=google.com; s=arc-20160816; b=nsnVLUDDVOAXc9KRdmf0VDHkhLy+xmwALGlJJORYo+tlVjr9ggG901LaaZADWdiBjd pS8ehxi1zToe/eBhxft7MHXElzVetOK7YU8knAanNADn9r0RT3AMJASmin/aZqIL65NP svVK3DtuMnvvCfPe57HtcaVLF6MifMnlQ7+eB8H+qUrCIoNHpXG6oo/WUECJTxvddo2r 1RHE87acQYDj38XjWFhfHBkD0DeeLFlG1rs9rX33cdrmRxV7AipwyNxuAHydZrejFtMQ Z+LnQNcQ5+9WaVwSDJ7Wplm/Rxqyfe3VqNgXQLYsBMVgCoA0aL9P5N3K36Owe5whQbxk NPTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rBNBEOcSDYR+VlJXpnn63cl+iKupYCFGcFqK74D/RBs=; b=k34KSPPqz+W+K7ZpjYzs8tYdgcChJ38KIBfS4bwesJcH+RAluGEOY+MJNM/cbnMXbU 3mYtgzkNjY8vLt1tWV8ZAGeEF7lnQNfBpiS7jSkiZ4BEOXY9Lqfloe//8LVJrH6Uizga 9VjUe/vh2KcO7A7DXRnVpTRRpUh6r9fRCb2DDNn/zTY9zmG4ecKHXpWih8v1qHJvvjy3 qmOYP47dU9ZH+m/B2PUuXbke/EtIpBP1I6Thg9EfUgwHZDRZ4o/CfQHcORN4Pxuw40qz AgHALnRjbWw2ZZgVlhzctI0JmLr5zBKjyJ6ZYj/62Dg0p51Jm7mRiCKJHCwb1Kg5D38x 7RPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wZm8jMEd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/17] target/ppc: Properly sync cpu state with new msr in cpu_load_old Date: Mon, 15 Mar 2021 12:46:01 -0600 Message-Id: <20210315184615.1985590-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Match cpu_post_load in using ppc_store_msr to set all of the cpu state implied by the value of msr. Do not restore hflags or hflags_nmsr, as we recompute them in ppc_store_msr. Signed-off-by: Richard Henderson --- target/ppc/machine.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Cédric Le Goater diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 283db1d28a..87d7bffb86 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -21,6 +21,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) int32_t slb_nr; #endif target_ulong xer; + target_ulong msr; for (i = 0; i < 32; i++) { qemu_get_betls(f, &env->gpr[i]); @@ -111,11 +112,19 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_betls(f, &env->ivpr_mask); qemu_get_betls(f, &env->hreset_vector); qemu_get_betls(f, &env->nip); - qemu_get_betls(f, &env->hflags); - qemu_get_betls(f, &env->hflags_nmsr); + qemu_get_sbetl(f); /* Discard unused hflags */ + qemu_get_sbetl(f); /* Discard unused hflags_nmsr */ qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused power_mode */ + /* + * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB + * before restoring. Note that this recomputes hflags and mem_idx. + */ + msr = env->msr; + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); + ppc_store_msr(env, msr); + /* Recompute mmu indices */ hreg_compute_mem_idx(env); From patchwork Mon Mar 15 18:46:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400537 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3682718jai; Mon, 15 Mar 2021 12:03:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9LIcND7MbPfRHbXUbGjtoZ3Q3Kd9EZZLWSttHK3X+6nsUIVkrbLcXwPWRj4YPj+4KKZ12 X-Received: by 2002:a5d:6b50:: with SMTP id x16mr1025830wrw.379.1615835004549; Mon, 15 Mar 2021 12:03:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835004; cv=none; d=google.com; s=arc-20160816; b=Y+5J4Sk6XfPmSfu30tPlzFmDTUdUEzDR+oTvzcI0YM+BCBg/eCz+T6ZEs4ckukpaCD 5f+je7r5w3Bz3UTqF40iZl0OrMej5X6cUjUF1P5wti6a7OUAb5hkcw5STPj21oq+7imo MX2Gg9Fopqibt/VQnNwslQxKG+9fSFCIYp0wnrCxJO/sbC6HJj/alpeZPc0AgfY/50EE 2KLrIIsrhAAGomCSBinT7NnZ9hjFsi+AkFPKMwDsXZ3lCepkc07h2kbEBN/E/DmoRG5/ VxDz05AluHnraRyHWgi6yxfkv/fpFBi5X0QzC3Yoo4swAdlGwC3eXyZn6JoeHQ8ZkmI7 +ajg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+NXtQw9hpPp+VCgrduDja0oQSnznjQ9crwR/vZ//mYY=; b=V+G44YmbxgS+Pz6OHVoCq0auxykxnxOEGRNUjZJApYo4e6PdvcmHbAw2zm3DFCP/RP ZeFJiFXk92m1sDZ/+I9ul82YgYUvfxDUQjDSIZRypB3kJb5fmv8DdB/MjL9SQDW7bIux NhNzRuQbjVKzBDtYXhIaE8+YY/Um01HnI9MZArlbs7Tow4rKOlEbFQW3TeAFAvr1dmcF liJu/RYSNeBu4gpr3ChXXE07uwnQmBrW5W77sjJKIwtDkrXUG1fBsstJO5JGy4gmGxTK 3CKoCJRbHP/UMR3rRhrt5HFJ2xpaxwCd5UngvcYNDHG3F0tV9WPKGjz7UIuzcDqQzphi h2ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f6qxrE6o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/17] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr Date: Mon, 15 Mar 2021 12:46:02 -0600 Message-Id: <20210315184615.1985590-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In ppc_store_msr we call hreg_compute_hflags, which itself calls hreg_compute_mem_idx. Rely on ppc_store_msr to update everything required by the msr update. Signed-off-by: Richard Henderson --- target/ppc/machine.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.25.1 Reviewed-by: Cédric Le Goater diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 87d7bffb86..f6eeda9642 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -125,9 +125,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - /* Recompute mmu indices */ - hreg_compute_mem_idx(env); - return 0; } @@ -418,14 +415,12 @@ static int cpu_post_load(void *opaque, int version_id) /* * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring + * before restoring. Note that this recomputes hflags and mem_idx. */ msr = env->msr; env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - hreg_compute_mem_idx(env); - return 0; } From patchwork Mon Mar 15 18:46:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400540 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3684884jai; Mon, 15 Mar 2021 12:05:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxph3a8yQ3qluOdiLRn5eMpp76nvhqvtHTM/zSXx7kgriBD2lgw3Ege60GOGeUlU6aXm2h7 X-Received: by 2002:a05:6808:904:: with SMTP id w4mr415352oih.1.1615835158928; Mon, 15 Mar 2021 12:05:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835158; cv=none; d=google.com; s=arc-20160816; b=wnWX16Jm4N11olbP09bydDuzkdRIGO51JFbzAN954o6lUOlPzGnvmjHyjPGBot69Sr 4ELwPZZRKjT1gARiS7lND9UFg2FAaii00pxKKRBKP+RTykq3S7wDqpCX+UwuhrneIFIm TNyLIcDyUf31v8BYzS3ek9XfQDPjXe0MRCV95ocD8FnePVryvwDzuOksESJOZZ3DIivA gWmh53vRW+W1f2LVYKahy6doPBQW7RXAx/h9q6IIEqC/XjidHAjHCPYkGgjwypHhuDJ+ g9A7KfmJbg3liQx4acuPRNkPaSE0RGFMsYqDMUQ9ZIPHRKMKs3K2qzU0axNGT9A8s/Lu WByw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rHSsmMGgFTbVP+9XKxjAVaBht/aShtydPxFkUYIpqOM=; b=tWVsMGQJuXltHDG+UKpliUZ38Xz6BODaaOTysHwSvs5fWUesA8POVZO0Dkxba/sO/G 32Odsy5v11WqysaQjCKF/VyyrBwbHI17hkxQbJfquzj6SdDzMJwlq+xo/m4319rJ5sfO 9KiMt6VxNV1s1wrrzkSw3g9DWxwefOHgNRSHUwcKxx5YVvaWfY5sZRX+DBYHyLftF1Rc BpI1sx9pKerwP12zfZYw/KqCEuSovjF5FY8n5Gb9Es2LVPwJcTxNW3NYZWN6LTfULWhK /fhDRKmOlAUV3ydISqgzhmiN6HF6HHvKtba+qv/4WIuBeHtNjBc8zXcUsWKIdJKgR5ke 8ugQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gO66qMzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/17] target/ppc: Retain hflags_nmsr only for migration Date: Mon, 15 Mar 2021 12:46:03 -0600 Message-Id: <20210315184615.1985590-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have eliminated all normal uses of hflags_nmsr. We need not even compute it except when we want to migrate. Rename the field to emphasize this. Remove the fixme comment for migrating access_type. This value is only ever used with the current executing instruction, and is never live when the cpu is halted for migration. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/helper_regs.c | 2 -- target/ppc/machine.c | 9 ++++++--- 3 files changed, 8 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Cédric Le Goater diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 061d2eed1b..79c4033a42 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1105,8 +1105,8 @@ struct CPUPPCState { #endif /* These resources are used only in QEMU core */ - target_ulong hflags; /* hflags is MSR & HFLAGS_MASK */ - target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ + target_ulong hflags; + target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 95b9aca61f..a87e354ca2 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -104,8 +104,6 @@ void hreg_compute_hflags(CPUPPCState *env) */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); env->hflags |= le << MSR_LE; - /* Retain for backward compatibility with migration. */ - env->hflags_nmsr = le << MSR_LE; } } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index f6eeda9642..1f7a353c78 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -310,6 +310,10 @@ static int cpu_pre_save(void *opaque) } } + /* Retain migration compatibility for pre 6.0 for 601 machines. */ + env->hflags_compat_nmsr = (env->flags & POWERPC_FLAG_HID0_LE + ? env->hflags & MSR_LE : 0); + return 0; } @@ -829,9 +833,8 @@ const VMStateDescription vmstate_ppc_cpu = { /* Supervisor mode architected state */ VMSTATE_UINTTL(env.msr, PowerPCCPU), - /* Internal state */ - VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), - /* FIXME: access_type? */ + /* Backward compatible internal state */ + VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU), /* Sanity checking */ VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), From patchwork Mon Mar 15 18:46:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400542 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3686008jai; Mon, 15 Mar 2021 12:07:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0N7CmgW8+i9ilRIw8wzUvjFPrfomdJ21kw5g33Je5h3mubdAMyFCKmO1lQO4zf+KnuxEG X-Received: by 2002:a05:6808:5c2:: with SMTP id d2mr474946oij.60.1615835240146; Mon, 15 Mar 2021 12:07:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835240; cv=none; d=google.com; s=arc-20160816; b=OB3Zg5LAxgMF3DP8Yh36mVfPkF9OMD4aEMurh55ougkbTYnsWStAiKr3LfF8Y/DX/R eO4MhYgop4Emd762LLST+EY/Iec01yn5LFBFsEjfGWsNbnOwPxhmKSL8wjirk2jJqw6L 6XoY2e7EK9IApXg4hwsb2GHIKfNKoPop6ifQa5EoMnI2Fs2YqsQOO8B23wVSjQTyYHfZ kE6NgAmNvmIxtX+OoOAfomYHvTfrp68uIaR0KNlL90bis1zy0pBs7S4/4CkiXH/3Wh02 0T9qNIfQpbiutBMxdLF3V/hG/QNgzNzlyD8WVqhxu+8cgLDIlI6u7HDU6cY5LgRhnj9n XWSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pYpOKcKLH+90rQBuRerzfXX/ETf/I2egL2u0VDsDgAk=; b=EnTQnRQVODXb54xDusv8/rBcYljzhD7zBU3UgDidd/9uAcd1iq8fkAu/qGT6ZJjn6J xfkXAxgoHbEuLiEV4XCPt23BRfVsAmnNGvswCRSc+o3yueSEQ2K0PGUTYA9krMdNydIo 1/5HYUZRmF0QQi3L/+TspXhGCzugRxVK+Qe+y1eIryumWYJ2wywJKLp1gFw2s2ZZTmPQ uDfkuND5vIlYZBeonkSf5rL3WPt8GddG0wIXwgLQXwi9GU+GBZ+gTUE0Asb2cRlEnbhD jXEpGMTOcAd+qo+lJOP32bnuGi8It2dScjUaLejDczap8Ye59VEpEY85RXRH39uKowqO 1UuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DodCnvCq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/17] target/ppc: Fix comment for MSR_FE{0,1} Date: Mon, 15 Mar 2021 12:46:04 -0600 Message-Id: <20210315184615.1985590-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As per hreg_compute_hflags: We 'forget' FE0 & FE1: we'll never generate imprecise exceptions remove the hflags marker from the respective comments. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Cédric Le Goater diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 79c4033a42..fd13489dce 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -322,13 +322,13 @@ typedef struct ppc_v3_pate_t { #define MSR_PR 14 /* Problem state hflags */ #define MSR_FP 13 /* Floating point available hflags */ #define MSR_ME 12 /* Machine check interrupt enable */ -#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ +#define MSR_FE0 11 /* Floating point exception mode 0 */ #define MSR_SE 10 /* Single-step trace enable x hflags */ #define MSR_DWE 10 /* Debug wait enable on 405 x */ #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ #define MSR_BE 9 /* Branch trace enable x hflags */ #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ -#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ +#define MSR_FE1 8 /* Floating point exception mode 1 */ #define MSR_AL 7 /* AL bit on POWER */ #define MSR_EP 6 /* Exception prefix on 601 */ #define MSR_IR 5 /* Instruction relocate */ From patchwork Mon Mar 15 18:46:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400546 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3687865jai; Mon, 15 Mar 2021 12:10:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy66lGnYXX4UpZGgtAoYnvRip38qAmVPwpfkzhPDjmkcbxr79cUamOAxGrtfoPux8ShhP2i X-Received: by 2002:a92:cc4f:: with SMTP id t15mr785167ilq.299.1615835400016; Mon, 15 Mar 2021 12:10:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835400; cv=none; d=google.com; s=arc-20160816; b=pq0Xip3gApsj6KDj2G1JVL9gCxTNcWlWi/2aJsASRWNCmwwRAum/PVmDcJk2XzzCgC ZnrNqLZZP08gI+ehCrEo4JNL4rWKF6RSpY4I60ohJDk8fYbK3NAtfcOrXVVzxkEdoV1q yYXj93AE/LEgsIQFj9CNOtsWKCk6ZKnY8/ojj9OJ8FT3q0543chg9Z1G4F+KBvody8wy w4xF/C6kxOGmDrhdWQ3VjoThol8+EoJmf20LZ5DIB9QvBKIu9SPN2R2M8lRwDFRqn76T 9MsD1sBs1UHDBsVZCV1Cx287dKSf3IWafzvvnMrVxR2Fz7c5u++Ji1/ChZs/xxZi6qDh UEvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hY92A/8JkW6zB37HSUC6YiwaXy9HOEDWasRA8S9xbcA=; b=P8VPB5zzgZ/Icqf5JQ8KTGYBkegCrKBdTeMy1yfFrbj4HRbvsglsC+Sr+JokJQ8iOq aOA9ff92J5LLukiEwz62GaNm5wmjh/ASR35PsZaGGkRaKzhISu5eziEQ63h6hExftLPo UqPpgiwUauJBEKb6m476QAogAnXImbF77UL+3MNPDJBJPiI+R6jPt67iU07+niL1l+Iu mIwSFnSjhmQvCY6VOeERB+zUtAxdJJ2fxvHjeOy5kpvQjLXxw52E5BE1hV/X3UfMVDfn 6ZQGU6MdeoXZ0KQzu97dRuAQsxmj3IQtESxsgsIQI4zmZ71blQ89jNxQga8YEimOLJah EhxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CXs0OcHg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/17] target/ppc: Disconnect hflags from MSR Date: Mon, 15 Mar 2021 12:46:05 -0600 Message-Id: <20210315184615.1985590-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ivan Warren , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copying flags directly from msr has drawbacks: (1) msr bits mean different things per cpu, (2) msr has 64 bits on 64 cpus while tb->flags has only 32 bits. Create a enum to define these bits. Document the origin of each bit. This fixes the truncation of env->hflags to tb->flags, because we no longer have hflags bits set above bit 31. Most of the code in ppc_tr_init_disas_context is moved over to hreg_compute_hflags. Some of it is simple extractions from msr, some requires examining other cpu flags. Anything that is moved becomes a simple extract from hflags in ppc_tr_init_disas_context. Several existing bugs are left in ppc_tr_init_disas_context, where additional changes are required -- to be addressed in future patches. Remove a broken #if 0 block. Reported-by: Ivan Warren Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 24 ++++++++++++++++++ target/ppc/helper_regs.c | 55 ++++++++++++++++++++++++++++++++-------- target/ppc/translate.c | 55 ++++++++++++---------------------------- 3 files changed, 84 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fd13489dce..39f35b570c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -585,6 +585,30 @@ enum { POWERPC_FLAG_HID0_LE = 0x00400000, }; +/* + * Bits for env->hflags. + * + * Most of these bits overlap with corresponding bits in MSR, + * but some come from other sources. Be cautious when modifying. + */ +enum { + HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */ + HFLAGS_HV = 1, /* computed from MSR_HV and other state */ + HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ + HFLAGS_PR = 3, /* MSR_PR */ + HFLAGS_DR = 4, /* MSR_DR */ + HFLAGS_IR = 5, /* MSR_IR */ + HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ + HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ + HFLAGS_TM = 8, /* computed from MSR_TM */ + HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ + HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ + HFLAGS_FP = 13, /* MSR_FP */ + HFLAGS_SA = 22, /* MSR_SA */ + HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ +}; + /*****************************************************************************/ /* Floating point status and control register */ #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index a87e354ca2..0a746bffd7 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" @@ -87,24 +88,56 @@ void hreg_compute_mem_idx(CPUPPCState *env) void hreg_compute_hflags(CPUPPCState *env) { - target_ulong hflags_mask; + target_ulong msr = env->msr; + uint32_t ppc_flags = env->flags; + uint32_t hflags = 0; + uint32_t msr_mask; - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; + /* Some bits come straight across from MSR. */ + msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | + (1 << MSR_DR) | (1 << MSR_IR) | + (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); - if (env->flags & POWERPC_FLAG_HID0_LE) { + if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* * Note that MSR_LE is not set in env->msr_mask for this cpu, - * and so will never be set in msr or hflags at this point. + * and so will never be set in msr. */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); - env->hflags |= le << MSR_LE; + hflags |= le << MSR_LE; } + + if (ppc_flags & POWERPC_FLAG_BE) { + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + msr_mask |= 1 << MSR_SE; + } + + if (msr_is_64bit(env, msr)) { + hflags |= 1 << HFLAGS_64; + } + if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { + hflags |= 1 << HFLAGS_SPE; + } + if (ppc_flags & POWERPC_FLAG_VRE) { + msr_mask |= 1 << MSR_VR; + } + if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { + hflags |= 1 << HFLAGS_VSX; + } + if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { + hflags |= 1 << HFLAGS_TM; + } + +#ifndef CONFIG_USER_ONLY + if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { + hflags |= 1 << HFLAGS_HV; + } +#endif + + env->hflags = hflags | (msr & msr_mask); + hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..a9325a12e5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7879,67 +7879,48 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUPPCState *env = cs->env_ptr; + uint32_t hflags = ctx->base.tb->flags; int bound; ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; - ctx->pr = msr_pr; + ctx->pr = (hflags >> HFLAGS_PR) & 1; ctx->mem_idx = env->dmmu_idx; - ctx->dr = msr_dr; -#if !defined(CONFIG_USER_ONLY) - ctx->hv = msr_hv || !env->has_hv_mode; -#endif + ctx->dr = (hflags >> HFLAGS_DR) & 1; + ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; ctx->insns_flags2 = env->insns_flags2; ctx->access_type = -1; ctx->need_access_type = !mmu_is_64bit(env->mmu_model); - ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); + ctx->le_mode = (hflags >> HFLAGS_LE) & 1; ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; ctx->flags = env->flags; #if defined(TARGET_PPC64) - ctx->sf_mode = msr_is_64bit(env, env->msr); + ctx->sf_mode = (hflags >> HFLAGS_64) & 1; ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B || env->mmu_model == POWERPC_MMU_601 || env->mmu_model & POWERPC_MMU_64; - ctx->fpu_enabled = !!msr_fp; - if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { - ctx->spe_enabled = !!msr_spe; - } else { - ctx->spe_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { - ctx->altivec_enabled = !!msr_vr; - } else { - ctx->altivec_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx->vsx_enabled = !!msr_vsx; - } else { - ctx->vsx_enabled = false; - } + ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; + ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; + ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; + ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; if ((env->flags & POWERPC_FLAG_SCV) && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { ctx->scv_enabled = true; } else { ctx->scv_enabled = false; } -#if defined(TARGET_PPC64) - if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx->tm_enabled = !!msr_tm; - } else { - ctx->tm_enabled = false; - } -#endif + ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); - if ((env->flags & POWERPC_FLAG_SE) && msr_se) { - ctx->singlestep_enabled = CPU_SINGLE_STEP; - } else { - ctx->singlestep_enabled = 0; + + ctx->singlestep_enabled = 0; + if ((hflags >> HFLAGS_SE) & 1) { + ctx->singlestep_enabled |= CPU_SINGLE_STEP; } - if ((env->flags & POWERPC_FLAG_BE) && msr_be) { + if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } if ((env->flags & POWERPC_FLAG_DE) && msr_de) { @@ -7956,10 +7937,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } -#if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr_se = 1; -#endif bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns = MIN(ctx->base.max_insns, bound); From patchwork Mon Mar 15 18:46:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400541 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3685785jai; Mon, 15 Mar 2021 12:07:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFBlx/FLUbIgQWFpPxbdHFj6EpnGdFvmMbr63PFblh5fxVzovVLSQr7JPc76tjlVhKJd8a X-Received: by 2002:a05:6e02:156e:: with SMTP id k14mr869607ilu.200.1615835222927; Mon, 15 Mar 2021 12:07:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835222; cv=none; d=google.com; s=arc-20160816; b=aqKCyRtomFqSzatG7ZnbHSMbwVkipdsAG4F8RLb9obzTAmCAd/vC7OFPFLLXxxKzQ6 7BEkBpoLDhUACgx6lr6YTwf9l1neXjUQMqXvijF2y+4eKkTE1tCR1NTy3o+u6YfRGIBO cvVDRBBwnwsP4jBlwUvTRVr5LDrqJcPDjsmRIN3e51DIOrsHQsxk+dYPQEl+SdxNwNzf cEvbspFpFyyaHBGQdHkSOE4aWvqC0lJXq0GdVtRanqI1Jrp4Zu/O/5Gvky3PMckbYdCv SrWdolVxFtYZ3+mgIzNBZYjIAdXbSK0z2MJ93e+6KKfhaYcUfBbfNSqGteo9NBFFthcy dsMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/W2WFobHDD4oLw5DS+3Y+2H+mE4fKJy/+HfV/Ly0jXA=; b=txXQvyo23EihHbOnf32xdcunSxn7rsCcUEwwQiAln1qTo9wMr63NXVktE7InHZ/Uvv ECr5x7VJdVbcEBFg3Qagk4xqnnGqlqV5lBuJC4Ym3e0R5ayMv6OsDFvb4LiElyOW0Jel nUVCXLl5FfViSPpbiZRSldrKIsRTt8G0mGqOiLIl/nyxHVsnJv90pH08+HMz2BatT9Ef U6rSmIRu3ijXu+OD5Lpvzm31P9XBRwCsqInIcJFN5+9ejqAZGQ8SJTQirRAGymXFmueF R3Jsb3VPz65+oZlNjPYFCOzi8060NqPIfvLSTp4ef+0Buqd+qz2lM26f8pdn1BSo4aYy 207w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mxm7evbx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/17] target/ppc: Reduce env->hflags to uint32_t Date: Mon, 15 Mar 2021 12:46:06 -0600 Message-Id: <20210315184615.1985590-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It will be stored in tb->flags, which is also uint32_t, so let's use the correct size. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/misc_helper.c | 2 +- target/ppc/translate.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Cédric Le Goater Reviewed-by: David Gibson diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 39f35b570c..2abaf56869 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1128,8 +1128,8 @@ struct CPUPPCState { bool resume_as_sreset; #endif - /* These resources are used only in QEMU core */ - target_ulong hflags; + /* These resources are used only in TCG */ + uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 63e3147eb4..b04b4d7c6e 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -199,7 +199,7 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ hreg_compute_hflags(env); - qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, + qemu_log("%s: set endianness to %c => %08x\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a9325a12e5..a85b890bb0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7657,7 +7657,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->nip, env->lr, env->ctr, cpu_read_xer(env), cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " - TARGET_FMT_lx " iidx %d didx %d\n", + "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, env->immu_idx, env->dmmu_idx); #if !defined(NO_TIMER_DUMP) From patchwork Mon Mar 15 18:46:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400544 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3687104jai; Mon, 15 Mar 2021 12:08:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzS0vpE955kaS1aOyy8c6j1Ii0dxPfyHCb3dIrJlBG97u8xapTwT6mx4wn9ralz4MI1twZ0 X-Received: by 2002:a4a:be86:: with SMTP id o6mr409937oop.70.1615835330936; Mon, 15 Mar 2021 12:08:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835330; cv=none; d=google.com; s=arc-20160816; b=ckz3JHYh9/2eheYpX7wU92o23kTGH7YN9Ls0kvWFIVQro5fDxMokwVdQGRpaaDxnRH 0OoAu61ocJtb04cNwGYwLrvB0StK/5BObK4Brz88dACXq8tRUaHvZFdvcsH9LSeuQlm4 xiFra4LQjrk5X+LY2cPm5uW5I1mn0MI2rZDfxJgzPcweMF/fVlTdp97sRgL1psXvchYG etdZ2QOLMGsEDOQn1EtnlH6l//JtXr2Pt1rzs0ErmdXeIfmm/8lhyhfOOLe3mkhYrn0C T0wszAWYw27C3Kr8+JCfojY/SRW8s3UpkzYKnxAt/HEfEaL7913RAoRvwOF4q99ytOr+ rGPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LL8bkt3cpcyBMDK/LZ6QT2j+SFhG/YMWEf75uL1t8Es=; b=qoM3bYT5P1IBfFh5J8OYne/MO91ew5vllhNDlnab2abOyQd1L9Ch73/Iz/ohJ8tLe+ sH+2Vo2q0HmcXsyOcn90UG57UJq41jyQncCR5g4Fam347vYdfHHW9Hd4Nbs4SeNSUrn9 wBhIZpCWJSuNPt849WkfQmu4uP99XSUN341bcRiyLXHCSrzbFuJFmslG+ZswA0zINOJ5 GP4VPkYi/amePNSaxnDoU+vsbjcFGclWtUepMRyBKYH+AaGhVgcgtqbDJr3+WognpN2u 3rbtlzeFd9vXUtP1Cv/v6G6Pn26+V0S/oqPKgGX1wxdFzqvkDzy8tO+54ewAf7n3nNp4 FJww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gXj5sWNH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/17] target/ppc: Put dbcr0 single-step bits into hflags Date: Mon, 15 Mar 2021 12:46:07 -0600 Message-Id: <20210315184615.1985590-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because these bits were not in hflags, the code generated for single-stepping on BookE was essentially random. Recompute hflags when storing to dbcr0. Signed-off-by: Richard Henderson --- target/ppc/helper_regs.c | 20 +++++++++++++++----- target/ppc/misc_helper.c | 3 +++ target/ppc/translate.c | 11 ----------- 3 files changed, 18 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: David Gibson diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 0a746bffd7..c735540333 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -107,11 +107,21 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= le << MSR_LE; } - if (ppc_flags & POWERPC_FLAG_BE) { - msr_mask |= 1 << MSR_BE; - } - if (ppc_flags & POWERPC_FLAG_SE) { - msr_mask |= 1 << MSR_SE; + if (ppc_flags & POWERPC_FLAG_DE) { + target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; + if (dbcr0 & DBCR0_ICMP) { + hflags |= 1 << HFLAGS_SE; + } + if (dbcr0 & DBCR0_BRT) { + hflags |= 1 << HFLAGS_BE; + } + } else { + if (ppc_flags & POWERPC_FLAG_BE) { + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + msr_mask |= 1 << MSR_SE; + } } if (msr_is_64bit(env, msr)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index b04b4d7c6e..a5ee1fd63c 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { + /* Bits 26 & 27 affect single-stepping */ + hreg_compute_hflags(env); + /* Bits 28 & 29 affect reset or shutdown. */ store_40x_dbcr0(env, val); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a85b890bb0..7912495f28 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } - if ((env->flags & POWERPC_FLAG_DE) && msr_de) { - ctx->singlestep_enabled = 0; - target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if (dbcr0 & DBCR0_ICMP) { - ctx->singlestep_enabled |= CPU_SINGLE_STEP; - } - if (dbcr0 & DBCR0_BRT) { - ctx->singlestep_enabled |= CPU_BRANCH_STEP; - } - - } if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } From patchwork Mon Mar 15 18:46:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400548 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3690116jai; Mon, 15 Mar 2021 12:13:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwAwt2KJl1b+DbAU47DKg1tQPosRBaqVVKVdWjhC/wluJGuQCPCgTXnZ5gQmPVMgUsIa13 X-Received: by 2002:a92:c147:: with SMTP id b7mr924849ilh.6.1615835601227; Mon, 15 Mar 2021 12:13:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835601; cv=none; d=google.com; s=arc-20160816; b=FiQVjctwC9dgBO09HP7bPZxdxiuFbrCXmVDvXtucUyasMRnnIiIQRHGLRMOMkrI1EF OchE/l48rB216aSwim4+ZEZkXBG7WvR0SaxbdmFJgRwmuZU5JcxCScSqZQLimWi43vMe JG5FDMeTo0jhI260NR7mfKJRfTuM/WwOoyChLrGHH8WFRNLmEyRD9sFteuva25OAJ4ye 8oM2DTLAy10Qe+3jXgGVQz/NIzEOIoSuGfRMduSXwhGLP3vct/EclbxdGLrKUwPqDs+I mWXCkENnzH048aS2UXBmViyQpEKOcDQprHLlhOxW2tqQPVagkGzkZXOxZsSpK0duWjRB zhrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nDEzeJHZqdUXe/dXYq7qR5PEy35VBqTIPDXHrdEdgcc=; b=qeMOj4k3Ne0mA2k9H715kgpyTGGPTIRE/r8j/RxhMY+gwxb2jaayPYG2uIiKhGVPLz /rMPozw8FFepwc/GFEJqeLpo+miH0CJKGaqsKBAPXye7sYC1y1FADR7CGzRXScsYWXhu 7g+F+N2OheaYL0WKwsjcvckJcxfANjgfmGw1ElxFrmDrIPKLZ7pSzxx8Px6So/8ROX9S 9DiFXY/rDcnZdTFxByzXvU47QrltaS4Kmh3YnrDecgKOme1e04Agwg7v98KlkHfd/nmV +DIQMRteVHHSXKNb1VLxdD5/5Z2I+QU0T9JDOCFU61xLIb1uyAqT5ivfMr4exbwlUmWt Idlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GxwT/s1K"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/17] target/ppc: Create helper_scv Date: Mon, 15 Mar 2021 12:46:08 -0600 Message-Id: <20210315184615.1985590-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform the test against FSCR_SCV at runtime, in the helper. This means we can remove the incorrect set against SCV in ppc_tr_init_disas_context and do not need to add an HFLAGS bit. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 1 + target/ppc/excp_helper.c | 9 +++++++++ target/ppc/translate.c | 20 +++++++------------- 3 files changed, 17 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..513066d54d 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -13,6 +13,7 @@ DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) +DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 85de7e6c90..5c95e0c103 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1130,6 +1130,15 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) } #if defined(TARGET_PPC64) +void helper_scv(CPUPPCState *env, uint32_t lev) +{ + if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { + raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); + } else { + raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); + } +} + void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) { CPUState *cs; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7912495f28..d48c554290 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -173,7 +173,6 @@ struct DisasContext { bool vsx_enabled; bool spe_enabled; bool tm_enabled; - bool scv_enabled; bool gtse; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -4081,15 +4080,16 @@ static void gen_sc(DisasContext *ctx) #if !defined(CONFIG_USER_ONLY) static void gen_scv(DisasContext *ctx) { - uint32_t lev; + uint32_t lev = (ctx->opcode >> 5) & 0x7F; - if (unlikely(!ctx->scv_enabled)) { - gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV); - return; + /* Set the PC back to the faulting instruction. */ + if (ctx->exception == POWERPC_EXCP_NONE) { + gen_update_nip(ctx, ctx->base.pc_next - 4); } + gen_helper_scv(cpu_env, tcg_constant_i32(lev)); - lev = (ctx->opcode >> 5) & 0x7F; - gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev); + /* This need not be exact, just not POWERPC_EXCP_NONE */ + ctx->exception = POWERPC_SYSCALL_VECTORED; } #endif #endif @@ -7907,12 +7907,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; - if ((env->flags & POWERPC_FLAG_SCV) - && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { - ctx->scv_enabled = true; - } else { - ctx->scv_enabled = false; - } ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); From patchwork Mon Mar 15 18:46:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400550 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3692271jai; Mon, 15 Mar 2021 12:16:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGvmbZv2zZKeijs6OiaFer6Crd7GQTUtMaCPrasubUv2UUMWx8YVVRTCONr6ZpnQ0Xb5WG X-Received: by 2002:a92:5411:: with SMTP id i17mr882074ilb.22.1615835804176; Mon, 15 Mar 2021 12:16:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835804; cv=none; d=google.com; s=arc-20160816; b=Kfsv4VfBCpQw+e56+vlCxlylhN8cMxmeNqFoTGep5muMQlKGRVnV8tcWY8e+c0+/1a ay8P9yvq/zcKbacdjbFlGUzJhLA5uWPOarDAo//wX2TrRHDoWvHEOQbW4Lc3UN++/cjP GY967XQgarCq1QODM03ynxr8+wOmD2IsJEHdMB+tXq9k2orw8nL2sdJcqLVFo1rLARBg LpCnR7S0DBi9Eexc0gGFZ5QM0vcQQyesspcZX21Ugw7OfQ9BUS+Z0aoVcPSniP4LGID7 njI5jQose9iT3/F3ufN6t1iebbO1PAu+Ngk4hyhMoizvoEBZ5+07GOt4QIE763uLB5PQ vpFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Fm4BN1FAYzcobXIUNrNdXuRiaQp/Ku74cUVfr1tQ2mY=; b=rYgUFhR5wlblitKuSmlBnI+XpOOJ+ONtfj/e2BbOkbC+zvuLxhyS/kqI9eWsKGjX6l Fxi8SBtl9+DtY+QYJBSQ0Y61qw3RpX/BFicI7153BlDq2Yvn6NOWuREtg33PjFNq/QiO GNKyI5eZ2VjkylryVpf3TO+izcp8Txo0llLrqdIOmNeTwobGOu5WdF4CMdS8Sq7hrAMa w8UhfTMANX37ykmfPoXp0KC1aflCeOjtGadnpuIWfTRDvj0q3Kpk4c0vexfXWu3NRRbO klIXXudCJhsijhrWFNOsPUQo3p6e/4SxADcB51RxGlpJqHa5GM+rOPHmn9BZ1R/bw5xB dZ9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QIvrSSM9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/17] target/ppc: Put LPCR[GTSE] in hflags Date: Mon, 15 Mar 2021 12:46:09 -0600 Message-Id: <20210315184615.1985590-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because this bit was not in hflags, the privilege check for tlb instructions was essentially random. Recompute hflags when storing to LPCR. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 1 + target/ppc/helper_regs.c | 3 +++ target/ppc/mmu-hash64.c | 3 +++ target/ppc/translate.c | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: David Gibson diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2abaf56869..07a4331eec 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -603,6 +603,7 @@ enum { HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ + HFLAGS_GTSE = 11, /* computed from SPR_LPCR[GTSE] */ HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_SA = 22, /* MSR_SA */ HFLAGS_AP = 23, /* MSR_AP */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index c735540333..8479789e24 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -139,6 +139,9 @@ void hreg_compute_hflags(CPUPPCState *env) if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; } + if (env->spr[SPR_LPCR] & LPCR_GTSE) { + hflags |= 1 << HFLAGS_GTSE; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0fabc10302..d517a99832 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "hw/hw.h" #include "mmu-book3s-v3.h" +#include "helper_regs.h" /* #define DEBUG_SLB */ @@ -1125,6 +1126,8 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; + /* The gtse bit affects hflags */ + hreg_compute_hflags(env); } void helper_store_lpcr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d48c554290..5e629291d3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7908,7 +7908,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; - ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); + ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { From patchwork Mon Mar 15 18:46:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400534 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3679724jai; Mon, 15 Mar 2021 11:59:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzOwwaT7866IOkkCrLT5AbgCzdvmt9qmnuE4POsWTiw9YdwGE5/h/+L4eUF6GdN+g2q5qCj X-Received: by 2002:a02:3c01:: with SMTP id m1mr10534321jaa.87.1615834797901; Mon, 15 Mar 2021 11:59:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615834797; cv=none; d=google.com; s=arc-20160816; b=BKMOH30lHKyHmwxLyRUnm58Oszkp/WTWoY+VPA3DMYc7TXAQJp7yPRMJ79VDtrYK7g SLe4Ou7JwIhVNUo9nvUi/wky5oA5bRb228vCaihqdl03V2ctZTRGY2J/fUJEsIk3Znfx npmgGBpwVUZZd1qdMIq21P7xonGiRVboBWNv7PHsNkb+dhpEJ3HXVDgWpRDzX3m6XM4l H4/HT01spAGEWIH0oYy6UsWBqqSa4HtnHT350vNYrTX/wzUFqxHsv9Sn/mjrTg8qWy9T 1aNhkKFzpBfLzZ1n15Fgl9JloKNHFFfTe6926F9Z8RSzy8Zt7z6LCJJcCfi69EmPDt68 gRTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bCT8Z895v2OzlUZ7cD3kW9yujJdvuk9uwCXjA4T3jIk=; b=J5OubJPuNLo7+mRYNJA7NJ1KfDvbRec9e97CqVlz4xpCLIPqBL+EVAJu/KTJRal6/z dd+7vzi6KXK5qYMIY5ttNSJPtSmSyQ1nyhPuPa14MkWkg3KIVATpzA1NlTGCGkx/QraA Lvf7RGNePgodCfQxvwrYxm5zDznnOzwBIO74KQk7O3kLqZ9er3HQiOkJqD2fm9EF+gco K9PNFHbF9QWFx7xA7p2getdJCHiZITzb8N65ylOCEB0Hvr5l68E68NAf6Fc+dhqieXWF XT4F4G1FT02xK8BVBFTBD8DVvmjO9gaY1ZX9BTm2qqaOBw84SllzaYCsJXNIQi8Ubk7M VUMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="S/l/QMh7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/17] target/ppc: Remove MSR_SA and MSR_AP from hflags Date: Mon, 15 Mar 2021 12:46:10 -0600 Message-Id: <20210315184615.1985590-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Nothing within the translator -- or anywhere else for that matter -- checks MSR_SA or MSR_AP on the 602. This may be a mistake. However, for the moment, we need not record these bits in hflags. This allows us to simplify HFLAGS_VSX computation by moving it to overlap with MSR_VSX. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 +--- target/ppc/helper_regs.c | 7 +++---- 2 files changed, 4 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: David Gibson diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 07a4331eec..23ff16c154 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -599,14 +599,12 @@ enum { HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ - HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ HFLAGS_GTSE = 11, /* computed from SPR_LPCR[GTSE] */ HFLAGS_FP = 13, /* MSR_FP */ - HFLAGS_SA = 22, /* MSR_SA */ - HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ }; diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8479789e24..d62921c322 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -95,8 +95,7 @@ void hreg_compute_hflags(CPUPPCState *env) /* Some bits come straight across from MSR. */ msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | - (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); + (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -133,8 +132,8 @@ void hreg_compute_hflags(CPUPPCState *env) if (ppc_flags & POWERPC_FLAG_VRE) { msr_mask |= 1 << MSR_VR; } - if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { - hflags |= 1 << HFLAGS_VSX; + if (ppc_flags & POWERPC_FLAG_VSX) { + msr_mask |= 1 << MSR_VSX; } if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; From patchwork Mon Mar 15 18:46:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400547 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3688564jai; Mon, 15 Mar 2021 12:11:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUD8mnLdx89x3z4z0WDm/d8c4iXzrEh5D8YsHdPUFH8iD/qPz2LjZmmKSbmGE8THQnJZgX X-Received: by 2002:a92:cd0c:: with SMTP id z12mr868957iln.109.1615835461524; Mon, 15 Mar 2021 12:11:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835461; cv=none; d=google.com; s=arc-20160816; b=aHEDMPq6qdrag60UdJCSyEbiEtQc3oJ93s+BwjEDndSxrRekvt49H27Yj0XCRfjnXy JhblnCDyVe2bv1KsP+0ky5uI6Z7Kqpq3TlSzofX9qzf4VypDR973GX96AxXnlfQmX3uO 0EJYCT8yX+jf91rvlUvtq7kb/mcHGC8UojCJlPRJ3LioIpjUEA0AWxlvk3T+rwzwo+cP TYlYhI7zsu3eAoKHqX/MAMoZZ5IEkEtCLntgqglrEutO7E2yVc+UuTa8LQsaPxzI6F3T AjpmZTPKL9s1W+G6FGzExiWzDMrVpyHM0RiEJemVxljeRGVEJIHSfPSkCYuELzqrkcRa m8rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WgTBRUnu7J8koNQdxGgffOswXs7sxkMr5Aqor7q7qKI=; b=sRownxOQ3tO5cMNUFwmQZURDEHhZAou+/BDLHFcgmdBSmsQTplHkvT6is2HMb1kshj FbrZVN6G6+zmF3fmGKsMkzhFiwNKINnCvmf5FTMwhY1HOi7ynajSToUc8hua6RFGhcSj 7qpIHOU4PtUO00XcEG2M+9ZCEPG5RPUouHQld0rJ9+mekyPXwr1oEViJ+VuNXp7MkMuh 3mahUJLzV/SdWINUpbu950kIW/7TOI5eCrwQ38tUhQTh6HGphRP1LZoKk2qx+LqDCSzF hpi5a8z4wWe0iQW8MdLnT/VF5QCQi0dMUHM1x86zNDtyl5MzJJ772ExOatReM8h++I/S NXqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mFZYDCr6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/17] target/ppc: Remove env->immu_idx and env->dmmu_idx Date: Mon, 15 Mar 2021 12:46:11 -0600 Message-Id: <20210315184615.1985590-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We weren't recording MSR_GS in hflags, which means that BookE memory accesses were essentially random vs Guest State. Instead of adding this bit directly, record the completed mmu indexes instead. This makes it obvious that we are recording exactly the information that we need. This also means that we can stop directly recording MSR_IR. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 12 ++++-- target/ppc/helper_regs.h | 1 - target/ppc/helper_regs.c | 88 ++++++++++++++++++++-------------------- target/ppc/mem_helper.c | 2 +- target/ppc/translate.c | 6 +-- 5 files changed, 55 insertions(+), 54 deletions(-) -- 2.25.1 Reviewed-by: David Gibson diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 23ff16c154..2f8d7fa13c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -597,7 +597,6 @@ enum { HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ HFLAGS_PR = 3, /* MSR_PR */ HFLAGS_DR = 4, /* MSR_DR */ - HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ @@ -606,6 +605,9 @@ enum { HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ + + HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */ + HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */ }; /*****************************************************************************/ @@ -1130,8 +1132,6 @@ struct CPUPPCState { /* These resources are used only in TCG */ uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ - int immu_idx; /* precomputed MMU index to speed up insn accesses */ - int dmmu_idx; /* precomputed MMU index to speed up data accesses */ /* Power management */ int (*check_pow)(CPUPPCState *env); @@ -1367,7 +1367,11 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define MMU_USER_IDX 0 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) { - return ifetch ? env->immu_idx : env->dmmu_idx; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; +#endif } /* Compatibility modes */ diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 4148a442b3..42f26870b9 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -21,7 +21,6 @@ #define HELPER_REGS_H void hreg_swap_gpr_tgpr(CPUPPCState *env); -void hreg_compute_mem_idx(CPUPPCState *env); void hreg_compute_hflags(CPUPPCState *env); void cpu_interrupt_exittb(CPUState *cs); int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index d62921c322..b28037ca24 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,49 +43,6 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - void hreg_compute_hflags(CPUPPCState *env) { target_ulong msr = env->msr; @@ -95,7 +52,7 @@ void hreg_compute_hflags(CPUPPCState *env) /* Some bits come straight across from MSR. */ msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); + (1 << MSR_DR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -146,10 +103,51 @@ void hreg_compute_hflags(CPUPPCState *env) if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { hflags |= 1 << HFLAGS_HV; } + + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + unsigned immu_idx, dmmu_idx; + dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; + if (env->mmu_model & POWERPC_MMU_BOOKE) { + dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; + dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; + } else { + dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; + dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; + } + hflags |= immu_idx << HFLAGS_IMMU_IDX; + hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif env->hflags = hflags | (msr & msr_mask); - hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index f4f7e730de..444b2a30ef 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -278,7 +278,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr, target_ulong mask, dcbz_size = env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx; + int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5e629291d3..a53463b9b8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7658,8 +7658,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", - env->msr, env->spr[SPR_HID0], - env->hflags, env->immu_idx, env->dmmu_idx); + env->msr, env->spr[SPR_HID0], env->hflags, + cpu_mmu_index(env, true), cpu_mmu_index(env, false)); #if !defined(NO_TIMER_DUMP) qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 #if !defined(CONFIG_USER_ONLY) @@ -7885,7 +7885,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; ctx->pr = (hflags >> HFLAGS_PR) & 1; - ctx->mem_idx = env->dmmu_idx; + ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; ctx->dr = (hflags >> HFLAGS_DR) & 1; ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; From patchwork Mon Mar 15 18:46:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400538 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3683252jai; Mon, 15 Mar 2021 12:04:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyU7vfq2oSGvcu5MWJ9hu0nCgldppkiqmU6TQ9sCwYWAhrixJW6LOJXRoNvs02yqzBOHtmr X-Received: by 2002:adf:b1c9:: with SMTP id r9mr1101202wra.51.1615835041381; Mon, 15 Mar 2021 12:04:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835041; cv=none; d=google.com; s=arc-20160816; b=UHHJb8n8KKZTpgKgkDr1X6DKRfOWPFlM2kaEU4V9yP5QQQWOGYMKeHduh3rqc6WiLk FtgmrmKhba06au8qkaIqYEzWs9qkKNuEFH6Gsn3C9N+M3NIRAh0NQs0YSLyNOrlbzG5b 1YTSkEq9ep1b7GjYYaCek//cskq7Z2q7zpoaBz65Z2UCtuPNmhKG16u4T1IV6thd3QIB etyJn/JZAbZZN7BYo43qhEkOtpJIXvUDE/EBsAITMywG5MQXMwmDdgNv0YagfrbkAGwy tYjadrt+rtHLnbLpFalmXMYUo/ibW2wi5k9L/JLMPvsZ1Uou9YdOZ7/GOfzy9fl/szWl DpwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Yn1M+lE2v7EuyDGAcu9RIP6tnxoaTYcb2VMIE3C3SLM=; b=RXKeyFYAMXObL7azssu79wD4znR1tV9bX1nT4nNYiBL2lNrQdv9mDwjI/F1bcwT3vV UsZhtfuEr8LvJImQKK8luEG3COCmPfp+wkE6JSrwRZ87HC9l2PM30jvlFFcqf4R2KvA2 +PEjcditbN7LyzqdJ6fq9tsONiCHDLgUvdcr8hQ9/QE4Zp2ulqOtZ7DbQN2Ap+VLPrXW /1LYHj4Kgi/tuurs/PcRt8poMy1pducG2jUneYOE+nU5svIg2Tbb/vgf4PZPjJLuwWu5 vaAG6+eA+UPOGCdGhg8rmrOU8O37hzIQd6Ru+eXvRo7zEioQIGN6mTgrzEk18tLm6d1x zq5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U24q8Mgu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/17] hw/ppc/pnv_core: Update hflags after setting msr Date: Mon, 15 Mar 2021 12:46:12 -0600 Message-Id: <20210315184615.1985590-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- hw/ppc/pnv_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index bd2bf2e044..8c2a15a0fb 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -29,6 +29,7 @@ #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "helper_regs.h" static const char *pnv_core_cpu_typename(PnvCore *pc) { @@ -55,8 +56,8 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) env->gpr[3] = PNV_FDT_ADDR; env->nip = 0x10; env->msr |= MSR_HVB; /* Hypervisor mode */ - env->spr[SPR_HRMOR] = pc->hrmor; + hreg_compute_hflags(env); pcc->intc_reset(pc->chip, cpu); } From patchwork Mon Mar 15 18:46:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400549 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3690755jai; Mon, 15 Mar 2021 12:14:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtvaPdpWF2uFr8KmDahGnaE63xzmxSZpf5/K/bTRkrZCoA3u0mpCjW1xUwb43a+zpHkfPX X-Received: by 2002:a05:6e02:188a:: with SMTP id o10mr924765ilu.12.1615835662977; Mon, 15 Mar 2021 12:14:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835662; cv=none; d=google.com; s=arc-20160816; b=u6qPhitdPna3ZHrFXiN+atl9DWLk4XfJhymBXDYvbHfAaXXmWIJVN8l4nj2JiC1tHJ 7HztWlheR6ZIwsINw0P994oiW/RdX7ec/KiOkEryrzrA1/j4CQQ/SUabcCeHxCjt3K4u /30wg1N5Duz7febqq1h1/BbxgRolUN2AUSWZxKd1yIyQ9bm6A84Zndam3CHEgrs+pd24 Oz0AmBQ5yPhx012TFT7E5cD37y3aCBsZoIKmTfZif0E0NJ52KOltjXZ3ZPwM2ERp9krr 9vyOobeJ0KA+ERkYmqJGXMJNkobP4B2xhRcyhpDPE6600bYPreqMmud6noLcTXukP1PR nmRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2SLkDKUkvRbhYpK5cToVW+A+jc+3yI/l50hLyBp9kdo=; b=I+8FkG+vi7E7obzKX5uS29KfmkQZvjANX1hKb65IZs5L4OXb2m0rQvJFE6pAvMAavd 4NyYA3hFgUgk1IaJD24GCNECP4b6fiAYQjFEA4OdH+tZpuk5E3nuJXTRNPQbW+cjgpyn GAy/AS9eNn01SOrYRi/Io+QTp/cY0lA1oS+UnmugtmcmgLwY9tlwp7UYaLibpuKROGsF wJUreAg3Dbk4m/rgMPN0++fEITX6w8B4tQreX2HsioIibQB44h2ABkv/sShObujkPUgF kVHOU9syWhSgZkWSWkJy9tZdAFuKSJnM4v8lKSrpQb6TCWiQy16mZ0OJAI526+Ma62We W9CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kWSvRFVa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/17] hw/ppc/spapr_rtas: Update hflags after setting msr Date: Mon, 15 Mar 2021 12:46:13 -0600 Message-Id: <20210315184615.1985590-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- hw/ppc/spapr_rtas.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8a79f9c628..6ec3e71757 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -51,6 +51,7 @@ #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" #include "migration/blocker.h" +#include "helper_regs.h" static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, @@ -163,6 +164,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, cpu_synchronize_state(CPU(newcpu)); env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); + hreg_compute_hflags(env); /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ lpcr = env->spr[SPR_LPCR]; From patchwork Mon Mar 15 18:46:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400539 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3683385jai; Mon, 15 Mar 2021 12:04:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwG9Iq5W0u37D2gGYUMLuzpY/n+mAPiON1QWRdYijeGQmGRjYFt7Olc40e2UjxMMFsxX534 X-Received: by 2002:a1c:4143:: with SMTP id o64mr1116613wma.50.1615835051444; Mon, 15 Mar 2021 12:04:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615835051; cv=none; d=google.com; s=arc-20160816; b=JY2qRamXmIkfzd9Zh05yu4uovoiYdXX/ZxBUngURZy2nUBKZwFrAgmllKx7CdHgvjV g0y+0fJh+Z23piFKTGWSBaQAWzb28qS71UkVFCNYXne7SvP5si9c4fmV/vY9X8aPZD/4 bOYKxCrmTj74A8paAKzz301ZgC/PsbISRgj9Tn+7I4D1COxWDXXeyuXxxUWRdqkAk1SZ KEZ4cVFVCXA+pllo0DpKNF7XMpIQnEO19rJmLvq1o8Hw/WcDs3NGZiLF4XUu7Bn/dyPG q3vF3Otp83P8QvvYH7NoHCnFtsblBrkKBl6WgnBRiJ0QHXHje6SEW9oDSfGT8EnU5Pul ip8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GP7KN1O/N4US4bdn1IcXHif9taZ0y5n50rRX2Q2HUDY=; b=DL+yqBxaVbAJfPSgYcKDNRPkHvx6AKcKdpiyrVU6NU+SgtUUbd7IiIGaRMDIRuonK6 ZgZCxH/JLoSJcGtB+mdoxurttP6i6Gp2L7FZB/n7n387kEXb2Y90ma7EEDW7ooM9FnHX zbOiSlPWNVFncOpwlUnbO6e+CX8Gw6NPAgLJdJYsoWEn+gMB56k6FSABrciTCBmSRN1L TD15rWrC2rLWJI7U3pVOiF/0DKUmWsz4ey1ljjB8+R9kua+A0pfybPxVA7DgKJMbGKVc VvohG3Qt3XlOM7opKVuokghomRFTSQFSDBbQtSCjfIGfwfNwaAi0HS430wQNc7eXvE/k eIvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F620gfJe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/17] linux-user/ppc: Fix msr updates for signal handling Date: Mon, 15 Mar 2021 12:46:14 -0600 Message-Id: <20210315184615.1985590-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In save_user_regs, there are two bugs where we OR in a bit number instead of the bit, clobbering the low bits of MSR. However: The MSR_VR and MSR_SPE bits control the availability of the insns. If the bits were not already set in MSR, then any attempt to access those registers would result in SIGILL. For linux-user, we always initialize MSR to the capabilities of the cpu. We *could* add checks vs MSR where we currently check insn_flags and insn_flags2, but we know they match. Also, there's a stray cut-and-paste comment in restore. Then, do not force little-endian binaries into big-endian mode. Finally, use ppc_store_msr for the update to affect hflags. Which is the reason none of these bugs were previously noticed. Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 5 +++-- linux-user/ppc/signal.c | 23 +++++++++++------------ 2 files changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index df71e15a25..4a0f6c8dc2 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -492,11 +492,12 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) #if defined(TARGET_PPC64) int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; #if defined(TARGET_ABI32) - env->msr &= ~((target_ulong)1 << flag); + ppc_store_msr(env, env->msr & ~((target_ulong)1 << flag)); #else - env->msr |= (target_ulong)1 << flag; + ppc_store_msr(env, env->msr | (target_ulong)1 << flag); #endif #endif + env->nip = regs->nip; for(i = 0; i < 32; i++) { env->gpr[i] = regs->gpr[i]; diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index b78613f7c8..bad38f8ed9 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -261,9 +261,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VR in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_VR; #if defined(TARGET_PPC64) vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; /* 64-bit needs to put a pointer to the vectors in the frame */ @@ -300,9 +297,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); } - /* Set MSR_SPE in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_SPE; __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); } #endif @@ -354,8 +348,10 @@ static void restore_user_regs(CPUPPCState *env, __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); /* If doing signal return, restore the previous little-endian mode. */ - if (sig) - env->msr = (env->msr & ~(1ull << MSR_LE)) | (msr & (1ull << MSR_LE)); + if (sig) { + ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | + (msr & (1ull << MSR_LE)))); + } /* Restore Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { @@ -376,8 +372,6 @@ static void restore_user_regs(CPUPPCState *env, __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VEC in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ #if defined(TARGET_PPC64) vrsave = (uint32_t *)&v_regs[33]; #else @@ -468,7 +462,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); unlock_user_struct(frame, frame_addr, 1); return; @@ -563,8 +557,13 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; #endif +#ifdef TARGET_WORDS_BIGENDIAN /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); +#else + /* Signal handlers are entered in little-endian mode. */ + ppc_store_msr(env, env->msr | (1ull << MSR_LE)); +#endif unlock_user_struct(rt_sf, rt_sf_addr, 1); return; From patchwork Mon Mar 15 18:46:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400535 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3680762jai; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id o25sm7519851otk.11.2021.03.15.11.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Mar 2021 11:46:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/17] target/ppc: Validate hflags with CONFIG_DEBUG_TCG Date: Mon, 15 Mar 2021 12:46:15 -0600 Message-Id: <20210315184615.1985590-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210315184615.1985590-1-richard.henderson@linaro.org> References: <20210315184615.1985590-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Verify that hflags was updated correctly whenever we change cpu state that is used by hflags. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 5 +++++ target/ppc/helper_regs.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2f8d7fa13c..7ee5c9a66e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2424,6 +2424,10 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags); +#else static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { @@ -2431,6 +2435,7 @@ static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, *cs_base = 0; *flags = env->hflags; } +#endif void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index b28037ca24..9df1098fec 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,7 +43,7 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_hflags(CPUPPCState *env) +static uint32_t hreg_compute_hflags_value(CPUPPCState *env) { target_ulong msr = env->msr; uint32_t ppc_flags = env->flags; @@ -147,9 +147,34 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif - env->hflags = hflags | (msr & msr_mask); + return hflags | (msr & msr_mask); } +void hreg_compute_hflags(CPUPPCState *env) +{ + env->hflags = hreg_compute_hflags_value(env); +} + +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + uint32_t hflags_current = env->hflags; + uint32_t hflags_rebuilt; + + *pc = env->nip; + *cs_base = 0; + *flags = hflags_current; + + hflags_rebuilt = hreg_compute_hflags_value(env); + if (unlikely(hflags_current != hflags_rebuilt)) { + cpu_abort(env_cpu(env), + "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", + hflags_current, hflags_rebuilt); + } +} +#endif + void cpu_interrupt_exittb(CPUState *cs) { if (!kvm_enabled()) {