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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/16] target/ppc: Move helper_regs.h functions out-of-line Date: Sun, 14 Mar 2021 11:58:51 -0600 Message-Id: <20210314175906.1733746-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the functions to a new file, helper_regs.c. Note int_helper.c was relying on helper_regs.h to indirectly include qemu/log.h. Signed-off-by: Richard Henderson --- target/ppc/helper_regs.h | 184 ++---------------------------------- target/ppc/helper_regs.c | 197 +++++++++++++++++++++++++++++++++++++++ target/ppc/int_helper.c | 1 + target/ppc/meson.build | 1 + 4 files changed, 207 insertions(+), 176 deletions(-) create mode 100644 target/ppc/helper_regs.c -- 2.25.1 diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index efcc903427..4148a442b3 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -20,184 +20,16 @@ #ifndef HELPER_REGS_H #define HELPER_REGS_H -#include "qemu/main-loop.h" -#include "exec/exec-all.h" -#include "sysemu/kvm.h" +void hreg_swap_gpr_tgpr(CPUPPCState *env); +void hreg_compute_mem_idx(CPUPPCState *env); +void hreg_compute_hflags(CPUPPCState *env); +void cpu_interrupt_exittb(CPUState *cs); +int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); -/* Swap temporary saved registers with GPRs */ -static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) -{ - target_ulong tmp; - - tmp = env->gpr[0]; - env->gpr[0] = env->tgpr[0]; - env->tgpr[0] = tmp; - tmp = env->gpr[1]; - env->gpr[1] = env->tgpr[1]; - env->tgpr[1] = tmp; - tmp = env->gpr[2]; - env->gpr[2] = env->tgpr[2]; - env->tgpr[2] = tmp; - tmp = env->gpr[3]; - env->gpr[3] = env->tgpr[3]; - env->tgpr[3] = tmp; -} - -static inline void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - -static inline void hreg_compute_hflags(CPUPPCState *env) -{ - target_ulong hflags_mask; - - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; - /* Merge with hflags coming from other registers */ - env->hflags |= env->hflags_nmsr; -} - -static inline void cpu_interrupt_exittb(CPUState *cs) -{ - if (!kvm_enabled()) { - return; - } - - if (!qemu_mutex_iothread_locked()) { - qemu_mutex_lock_iothread(); - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); - qemu_mutex_unlock_iothread(); - } else { - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); - } -} - -static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, - int alter_hv) -{ - int excp; -#if !defined(CONFIG_USER_ONLY) - CPUState *cs = env_cpu(env); -#endif - - excp = 0; - value &= env->msr_mask; -#if !defined(CONFIG_USER_ONLY) - /* Neither mtmsr nor guest state can alter HV */ - if (!alter_hv || !(env->msr & MSR_HVB)) { - value &= ~MSR_HVB; - value |= env->msr & MSR_HVB; - } - if (((value >> MSR_IR) & 1) != msr_ir || - ((value >> MSR_DR) & 1) != msr_dr) { - cpu_interrupt_exittb(cs); - } - if ((env->mmu_model & POWERPC_MMU_BOOKE) && - ((value >> MSR_GS) & 1) != msr_gs) { - cpu_interrupt_exittb(cs); - } - if (unlikely((env->flags & POWERPC_FLAG_TGPR) && - ((value ^ env->msr) & (1 << MSR_TGPR)))) { - /* Swap temporary saved registers with GPRs */ - hreg_swap_gpr_tgpr(env); - } - if (unlikely((value >> MSR_EP) & 1) != msr_ep) { - /* Change the exception prefix on PowerPC 601 */ - env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; - } - /* - * If PR=1 then EE, IR and DR must be 1 - * - * Note: We only enforce this on 64-bit server processors. - * It appears that: - * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS - * exploits it. - * - 64-bit embedded implementations do not need any operation to be - * performed when PR is set. - */ - if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { - value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); - } -#endif - env->msr = value; - hreg_compute_hflags(env); -#if !defined(CONFIG_USER_ONLY) - if (unlikely(msr_pow == 1)) { - if (!env->pending_interrupts && (*env->check_pow)(env)) { - cs->halted = 1; - excp = EXCP_HALTED; - } - } -#endif - - return excp; -} - -#if !defined(CONFIG_USER_ONLY) -static inline void check_tlb_flush(CPUPPCState *env, bool global) -{ - CPUState *cs = env_cpu(env); - - /* Handle global flushes first */ - if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { - env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; - env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; - tlb_flush_all_cpus_synced(cs); - return; - } - - /* Then handle local ones */ - if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { - env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; - tlb_flush(cs); - } -} -#else +#ifdef CONFIG_USER_ONLY static inline void check_tlb_flush(CPUPPCState *env, bool global) { } +#else +void check_tlb_flush(CPUPPCState *env, bool global); #endif #endif /* HELPER_REGS_H */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c new file mode 100644 index 0000000000..5e18232b84 --- /dev/null +++ b/target/ppc/helper_regs.c @@ -0,0 +1,197 @@ +/* + * PowerPC emulation special registers manipulation helpers for qemu. + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "sysemu/kvm.h" +#include "helper_regs.h" + +/* Swap temporary saved registers with GPRs */ +void hreg_swap_gpr_tgpr(CPUPPCState *env) +{ + target_ulong tmp; + + tmp = env->gpr[0]; + env->gpr[0] = env->tgpr[0]; + env->tgpr[0] = tmp; + tmp = env->gpr[1]; + env->gpr[1] = env->tgpr[1]; + env->tgpr[1] = tmp; + tmp = env->gpr[2]; + env->gpr[2] = env->tgpr[2]; + env->tgpr[2] = tmp; + tmp = env->gpr[3]; + env->gpr[3] = env->tgpr[3]; + env->tgpr[3] = tmp; +} + +void hreg_compute_mem_idx(CPUPPCState *env) +{ + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + if (env->mmu_model & POWERPC_MMU_BOOKE) { + env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; + env->immu_idx += msr_is ? 2 : 0; + env->dmmu_idx += msr_ds ? 2 : 0; + env->immu_idx += msr_gs ? 4 : 0; + env->dmmu_idx += msr_gs ? 4 : 0; + } else { + env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; + env->immu_idx += msr_ir ? 0 : 2; + env->dmmu_idx += msr_dr ? 0 : 2; + env->immu_idx += msr_hv ? 4 : 0; + env->dmmu_idx += msr_hv ? 4 : 0; + } +} + +void hreg_compute_hflags(CPUPPCState *env) +{ + target_ulong hflags_mask; + + /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ + hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | + (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); + hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; + hreg_compute_mem_idx(env); + env->hflags = env->msr & hflags_mask; + /* Merge with hflags coming from other registers */ + env->hflags |= env->hflags_nmsr; +} + +void cpu_interrupt_exittb(CPUState *cs) +{ + if (!kvm_enabled()) { + return; + } + + if (!qemu_mutex_iothread_locked()) { + qemu_mutex_lock_iothread(); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + qemu_mutex_unlock_iothread(); + } else { + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + } +} + +int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) +{ + int excp; +#if !defined(CONFIG_USER_ONLY) + CPUState *cs = env_cpu(env); +#endif + + excp = 0; + value &= env->msr_mask; +#if !defined(CONFIG_USER_ONLY) + /* Neither mtmsr nor guest state can alter HV */ + if (!alter_hv || !(env->msr & MSR_HVB)) { + value &= ~MSR_HVB; + value |= env->msr & MSR_HVB; + } + if (((value >> MSR_IR) & 1) != msr_ir || + ((value >> MSR_DR) & 1) != msr_dr) { + cpu_interrupt_exittb(cs); + } + if ((env->mmu_model & POWERPC_MMU_BOOKE) && + ((value >> MSR_GS) & 1) != msr_gs) { + cpu_interrupt_exittb(cs); + } + if (unlikely((env->flags & POWERPC_FLAG_TGPR) && + ((value ^ env->msr) & (1 << MSR_TGPR)))) { + /* Swap temporary saved registers with GPRs */ + hreg_swap_gpr_tgpr(env); + } + if (unlikely((value >> MSR_EP) & 1) != msr_ep) { + /* Change the exception prefix on PowerPC 601 */ + env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; + } + /* + * If PR=1 then EE, IR and DR must be 1 + * + * Note: We only enforce this on 64-bit server processors. + * It appears that: + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS + * exploits it. + * - 64-bit embedded implementations do not need any operation to be + * performed when PR is set. + */ + if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { + value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); + } +#endif + env->msr = value; + hreg_compute_hflags(env); +#if !defined(CONFIG_USER_ONLY) + if (unlikely(msr_pow == 1)) { + if (!env->pending_interrupts && (*env->check_pow)(env)) { + cs->halted = 1; + excp = EXCP_HALTED; + } + } +#endif + + return excp; +} + +#ifndef CONFIG_USER_ONLY +void check_tlb_flush(CPUPPCState *env, bool global) +{ + CPUState *cs = env_cpu(env); + + /* Handle global flushes first */ + if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { + env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; + env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; + tlb_flush_all_cpus_synced(cs); + return; + } + + /* Then handle local ones */ + if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { + env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; + tlb_flush(cs); + } +} +#endif diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 429de28494..a44c2d90ea 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" +#include "qemu/log.h" #include "exec/helper-proto.h" #include "crypto/aes.h" #include "fpu/softfloat.h" diff --git a/target/ppc/meson.build b/target/ppc/meson.build index bbfef90e08..4079d01ee3 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -6,6 +6,7 @@ ppc_ss.add(files( 'excp_helper.c', 'fpu_helper.c', 'gdbstub.c', + 'helper_regs.c', 'int_helper.c', 'mem_helper.c', 'misc_helper.c', From patchwork Sun Mar 14 17:58:52 2021 Content-Type: text/plain; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/16] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags Date: Sun, 14 Mar 2021 11:58:52 -0600 Message-Id: <20210314175906.1733746-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Keep all hflags computation in one place, as this will be especially important later. Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when LE should be taken from HID0. This appears to be set if and only if POWERPC_FLAG_RTC_CLK is set, but we're not short of bits and having both names will avoid confusion. Note that this was the only user of hflags_nmsr, so we can perform a straight assignment rather than mask and set. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 2 ++ target/ppc/helper_regs.c | 13 +++++++++++-- target/ppc/misc_helper.c | 8 +++----- target/ppc/translate_init.c.inc | 4 ++-- 4 files changed, 18 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..061d2eed1b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -581,6 +581,8 @@ enum { POWERPC_FLAG_TM = 0x00100000, /* Has SCV (ISA 3.00) */ POWERPC_FLAG_SCV = 0x00200000, + /* Has HID0 for LE bit (601) */ + POWERPC_FLAG_HID0_LE = 0x00400000, }; /*****************************************************************************/ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5e18232b84..95b9aca61f 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -96,8 +96,17 @@ void hreg_compute_hflags(CPUPPCState *env) hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env); env->hflags = env->msr & hflags_mask; - /* Merge with hflags coming from other registers */ - env->hflags |= env->hflags_nmsr; + + if (env->flags & POWERPC_FLAG_HID0_LE) { + /* + * Note that MSR_LE is not set in env->msr_mask for this cpu, + * and so will never be set in msr or hflags at this point. + */ + uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); + env->hflags |= le << MSR_LE; + /* Retain for backward compatibility with migration. */ + env->hflags_nmsr = le << MSR_LE; + } } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 5d6e0de396..63e3147eb4 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -194,16 +194,14 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) target_ulong hid0; hid0 = env->spr[SPR_HID0]; + env->spr[SPR_HID0] = (uint32_t)val; + if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ - env->hflags &= ~(1 << MSR_LE); - env->hflags_nmsr &= ~(1 << MSR_LE); - env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); - env->hflags |= env->hflags_nmsr; + hreg_compute_hflags(env); qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } - env->spr[SPR_HID0] = (uint32_t)val; } void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index c03a7c4f52..049d76cfd1 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -5441,7 +5441,7 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data) pcc->excp_model = POWERPC_EXCP_601; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; } #define POWERPC_MSRR_601v (0x0000000000001040ULL) @@ -5485,7 +5485,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) #endif pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; } static void init_proc_602(CPUPPCState *env) From patchwork Sun Mar 14 17:58:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400102 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2837271jai; Sun, 14 Mar 2021 11:10:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwv3G3+msbfaqiGS+Bm7S0TZiAAl2crzQvcarFFPmO2thzbXzv+1FTLwtPKiyMBQb0en8aL X-Received: by 2002:a02:c894:: with SMTP id m20mr6963856jao.80.1615745438292; Sun, 14 Mar 2021 11:10:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745438; cv=none; d=google.com; s=arc-20160816; b=WJAOcDzPlz+mq1AcKkUkUrXi962X3NaimjU7Y1W8IykwSFB99P8AZ5snR5KKSyyPFg THicy3esRKRDzE1B13u7382RuwlADZeO2Jo8XixYWOTrR8CKhtXofeAgLOR+YGForl0D EUk2A6nJx+Zeht7+us7RKnAWH4Ia2RVgSuaITDafqHkhEYZp+2yz2+/ZDkyUoVd3mqX+ AbWVm+6cFt/26uDMEPPJEtTkDubNN9iN4s4SHiCWkq7mWReKFYfHAq5U/6DRBDuJGPT6 wCxb9YfYh6+DLIxiCl/sZSH3/kQjJtk24ltTh1pPkJ98DqvrmqPoCt1o58h2nDQ/4YRR fVpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rBNBEOcSDYR+VlJXpnn63cl+iKupYCFGcFqK74D/RBs=; b=LX3CXnp2dnSLdY+TK8mjF4YNLB4jAYOcmPuDxUj1rdAshpwu3/onOstmYmO7G+Ufjq iKLe3/YHacjvOYFs1oZPVSUnAxjOC/93x4kRFesQNsyXpSBX7DrYliUjdGRzf6WdiKW0 I9+/akw/v1nqUYgBzuWRxjtU+CZI5W8jHR9yWZSNXioSZdy5iqESiuzbxy05uDqyolV8 6fRLBKyOPD6quKyd8lvq8vUG1IH2rgUNMR9T48oBJroYUpbjnez5JK6N/vTh1wv+wFYe EKv+EF0pPZQZaNr2IpRx0N1iNlcQqWlgEm/L3McPlbYYotU9yt3rToXdDaSavwIqdun+ TEAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hogfgALt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/16] target/ppc: Properly sync cpu state with new msr in cpu_load_old Date: Sun, 14 Mar 2021 11:58:53 -0600 Message-Id: <20210314175906.1733746-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Match cpu_post_load in using ppc_store_msr to set all of the cpu state implied by the value of msr. Do not restore hflags or hflags_nmsr, as we recompute them in ppc_store_msr. Signed-off-by: Richard Henderson --- target/ppc/machine.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 283db1d28a..87d7bffb86 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -21,6 +21,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) int32_t slb_nr; #endif target_ulong xer; + target_ulong msr; for (i = 0; i < 32; i++) { qemu_get_betls(f, &env->gpr[i]); @@ -111,11 +112,19 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_betls(f, &env->ivpr_mask); qemu_get_betls(f, &env->hreset_vector); qemu_get_betls(f, &env->nip); - qemu_get_betls(f, &env->hflags); - qemu_get_betls(f, &env->hflags_nmsr); + qemu_get_sbetl(f); /* Discard unused hflags */ + qemu_get_sbetl(f); /* Discard unused hflags_nmsr */ qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused power_mode */ + /* + * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB + * before restoring. Note that this recomputes hflags and mem_idx. + */ + msr = env->msr; + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); + ppc_store_msr(env, msr); + /* Recompute mmu indices */ hreg_compute_mem_idx(env); From patchwork Sun Mar 14 17:58:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400098 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2835406jai; Sun, 14 Mar 2021 11:07:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCzha5EjjB2qlL2GRwguVm8+xXG+khPNyd5T38ayLJPb2rMCW01HScT/wcVf4Fsuj2fitX X-Received: by 2002:a92:c7c2:: with SMTP id g2mr9369024ilk.209.1615745241188; Sun, 14 Mar 2021 11:07:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745241; cv=none; d=google.com; s=arc-20160816; b=SLIJZ4yA/f9o57O0QkEiYb3avm+NmlIKMqyqahtcyXbd+DticN6xSlOvZpoVLJtIs5 4y+uBD1+VFh+XmAPRuGeoKNNOBrPTXxWjZvt1eZ9EkOMxpdNY4+82KYK7UDi9ZkLWXtY tA5vyiTttzPPLnfdlr6ThUa1rBaoQjl4PX4vkbnMnHWM0RHCEc15ckSSoE3ujTf+WyT7 QQuqmWW191/1nUt/dLZX+9rIDqcgej/qbBR3fsNmD9c8sfc6PqXpPE3E0wNvgoii5isp jzti/5sr6GUERmNnEMSVbh1+MiyLpQ43UzmiqUI/dQH/V2SFDXmFXEcszB7V8Hxtb7jB eu/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+NXtQw9hpPp+VCgrduDja0oQSnznjQ9crwR/vZ//mYY=; b=U1GXOoldqFLTFQOrlFwkPyHFwmcm0YoGnFAJtCqwgD1qR2oJnc2UKfPPO2kmOmZyhQ tIPI51vJUPQ9T3Cb7ZZDkUtM8tnCY3W908bll+7PApFGPKdMKIr5KI1ovslp0gDsiCgV Ixo/WFTfo9hMk910ydg8lslcQEQ/KXeKGPkaEG+3yhkrrrPwHLK0kpAXqS06RVQZNspi lDAM7sZgZ6IbSnRmq1xSMFi6wDadD96Ik+VjU71nwFYExj2t69sPi3LV+yCx7ng0smaW bVsY3ToiI36Z5eNk0kOKgikpLWTFA+T4aASp84qWH1rFj8kSD4OyADx+5Kzxol5BPYiX FnEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iCM8bSzT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/16] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr Date: Sun, 14 Mar 2021 11:58:54 -0600 Message-Id: <20210314175906.1733746-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In ppc_store_msr we call hreg_compute_hflags, which itself calls hreg_compute_mem_idx. Rely on ppc_store_msr to update everything required by the msr update. Signed-off-by: Richard Henderson --- target/ppc/machine.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.25.1 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 87d7bffb86..f6eeda9642 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -125,9 +125,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - /* Recompute mmu indices */ - hreg_compute_mem_idx(env); - return 0; } @@ -418,14 +415,12 @@ static int cpu_post_load(void *opaque, int version_id) /* * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring + * before restoring. Note that this recomputes hflags and mem_idx. */ msr = env->msr; env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - hreg_compute_mem_idx(env); - return 0; } From patchwork Sun Mar 14 17:58:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400106 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2838891jai; Sun, 14 Mar 2021 11:13:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdZvb5GgRIR8iMUBgtf7OLjsJ4AWghlgiuyDLI/SCzb8SzfsHzhwC1zkwjEWzlsZ2QgkXy X-Received: by 2002:a25:790d:: with SMTP id u13mr8547922ybc.427.1615745636461; Sun, 14 Mar 2021 11:13:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745636; cv=none; d=google.com; s=arc-20160816; b=EcZ6iTLbD6X3QwmL+HIZOv3FchQC4cGefYiw5mi/vG3vJyWP08lnh/mMh6UKJ8VPJI +nJ5oDCp5sc+A0Vin7532OaikdbrN8cmLyh1pvKMHWpa5eigQAyF1XZr2++u+m+8GW5N bVA9DeinwBfeOJ2ye8lEiG7bQbBEoOysw4lzwzXB7H39Ct9Pl5HVGiBSPg/6XufdJIZr legJrko71A/IPccZbIgg/prxJ8Z4PNLTl+e5r5s8EXFOM1PvbFMiNxrLlXIGdG3l7wJe AZYVstlg5JI83xws0p7jaENdMOWBn0D/xNOtxFJV2g64lkkGsjOxn1mbK5dolBknu7Bj uB4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rHSsmMGgFTbVP+9XKxjAVaBht/aShtydPxFkUYIpqOM=; b=JpHpnBWOcq6SeJx+Bobcj4DGCkRRNpSt51b0SuWtk83b5Uiy7T1RPKww3sqNHyDe3r FkOqPehV+jrA0cRUI/2oh87B/hWDMhYm72vhM3HVsUbLjj7aTDJEb5Uq7BIySnt6SsU2 vhIdAeTZvkaipC7a0GnNDOAdgq+3p20Qq+4Rz+mrI9sKizyMjS/giSqWGzeZXNg5QRn9 LiPcW/47Yd92BApFme4hkNnOCcxoDibyVBcIK3Y7qJkZxlFxIpSdfLarBUXWEw8W+qcV GCI18h8JoQdPOmQP7VwtpIxAPrReuml5Nr8dnt/Lc1cXNvGvkHOKxOvwrYDxhZMHJii3 GISQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bta5pLlX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/16] target/ppc: Retain hflags_nmsr only for migration Date: Sun, 14 Mar 2021 11:58:55 -0600 Message-Id: <20210314175906.1733746-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::829; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x829.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have eliminated all normal uses of hflags_nmsr. We need not even compute it except when we want to migrate. Rename the field to emphasize this. Remove the fixme comment for migrating access_type. This value is only ever used with the current executing instruction, and is never live when the cpu is halted for migration. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/helper_regs.c | 2 -- target/ppc/machine.c | 9 ++++++--- 3 files changed, 8 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 061d2eed1b..79c4033a42 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1105,8 +1105,8 @@ struct CPUPPCState { #endif /* These resources are used only in QEMU core */ - target_ulong hflags; /* hflags is MSR & HFLAGS_MASK */ - target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ + target_ulong hflags; + target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 95b9aca61f..a87e354ca2 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -104,8 +104,6 @@ void hreg_compute_hflags(CPUPPCState *env) */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); env->hflags |= le << MSR_LE; - /* Retain for backward compatibility with migration. */ - env->hflags_nmsr = le << MSR_LE; } } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index f6eeda9642..1f7a353c78 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -310,6 +310,10 @@ static int cpu_pre_save(void *opaque) } } + /* Retain migration compatibility for pre 6.0 for 601 machines. */ + env->hflags_compat_nmsr = (env->flags & POWERPC_FLAG_HID0_LE + ? env->hflags & MSR_LE : 0); + return 0; } @@ -829,9 +833,8 @@ const VMStateDescription vmstate_ppc_cpu = { /* Supervisor mode architected state */ VMSTATE_UINTTL(env.msr, PowerPCCPU), - /* Internal state */ - VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), - /* FIXME: access_type? */ + /* Backward compatible internal state */ + VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU), /* Sanity checking */ VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), From patchwork Sun Mar 14 17:58:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400097 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2835358jai; Sun, 14 Mar 2021 11:07:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHbJdBNJ9q8i+sw2AgcaXbmQjQSjRMLVRoaAQhYPs94XQdbA5zOActUvQDCWeVNzxVQH/7 X-Received: by 2002:a05:6638:3049:: with SMTP id u9mr6627934jak.57.1615745234700; Sun, 14 Mar 2021 11:07:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745234; cv=none; d=google.com; s=arc-20160816; b=Mzc3BXLT3EfxAH9xh6EUhcD0c/4dXhM4i1WzpihvYAcIhmwFDp8Hl7hDBYEObrJ8Rj NH7Lrh1bHLKUMgSKJkJ4NO6BqkA7twawpTjvbNSOqpjP2bNxgRxgZRHzZcfrD54/s1up FOxASk96JIyNMLLmpEJujA4XQO+w4+GAZqLvULYXrbi7LyE3/m+ftgjIjyltcj3m8dlH liXk9ySIRMWCBG1Co/as6f8ZF0Bwt/1AFQ1b3U+63JbwZtw3RT/RXHwXsAClJIx2+a33 yyfcobZKwJHxfwHLes2zz7kUxhXc1NPmGIVyLfqIWYqYjwjfNxhVcfBYBnFGW+Uanvzc Pz+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pYpOKcKLH+90rQBuRerzfXX/ETf/I2egL2u0VDsDgAk=; b=dtO+b4bdfLyfboFFm3j5ciZXNYkTJD3xpl6PD3P30PXGOfPzWoON5Bp3fZU6FtRDhm BuALIbQHnqTWQtX+DuFEPpPfl5l0ttphRUZDpCREY4eA2BGYVYcxMVqMbdSQ8kT63OKm UCLtocxLtjMqKHuXZjnxteVWFgl5qKiiynH1dzWLbJZ/36lOZVIBo9b58lZuPUC4e5ti ifMcgifTj65U/sPcV80BvjHHw3sOUSF294JChT/qtJG/5kwVlyp/Kyoxb94uqGo2tBWa /gCMOIwEP7r/aY2UduqWr3COncCj7sNZdvE4K3FXk2TGRCFqLUoWXydZuVeWGmxAdGLJ CvmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=H7HUNQ9x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/16] target/ppc: Fix comment for MSR_FE{0,1} Date: Sun, 14 Mar 2021 11:58:56 -0600 Message-Id: <20210314175906.1733746-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As per hreg_compute_hflags: We 'forget' FE0 & FE1: we'll never generate imprecise exceptions remove the hflags marker from the respective comments. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 79c4033a42..fd13489dce 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -322,13 +322,13 @@ typedef struct ppc_v3_pate_t { #define MSR_PR 14 /* Problem state hflags */ #define MSR_FP 13 /* Floating point available hflags */ #define MSR_ME 12 /* Machine check interrupt enable */ -#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ +#define MSR_FE0 11 /* Floating point exception mode 0 */ #define MSR_SE 10 /* Single-step trace enable x hflags */ #define MSR_DWE 10 /* Debug wait enable on 405 x */ #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ #define MSR_BE 9 /* Branch trace enable x hflags */ #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ -#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ +#define MSR_FE1 8 /* Floating point exception mode 1 */ #define MSR_AL 7 /* AL bit on POWER */ #define MSR_EP 6 /* Exception prefix on 601 */ #define MSR_IR 5 /* Instruction relocate */ From patchwork Sun Mar 14 17:58:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400101 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2837221jai; Sun, 14 Mar 2021 11:10:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTs49uj+DEXwb3/gEw17MUSSMtXfihY/JUXMn2G7gGW1WAoartVVRRLXrw3dQmPE6zR+KS X-Received: by 2002:a6b:103:: with SMTP id 3mr5341036iob.98.1615745433108; Sun, 14 Mar 2021 11:10:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745433; cv=none; d=google.com; s=arc-20160816; b=BjWwt8pcgnhMTrgjaUG2hKup24XGiALB4D7fvbSIlhpn2gWUcLngpPEe7aAbCm5i68 tz+RyRha128iGfe6rMN6t4bHwxkJ7GraohQ+RhdzC7NrmiQf20JvKXU0/WU6Hm4ZKZFx kWmMg3eNwegEVyGZOasPqWvyhlKSjC7JrYuJMysVQ1X/u2USPZwKpBYbWjEArhh3NW8h bpRTxc1UyiFVac93tNwVIA0ZIPm5RDTpdoIEQK5xeV+EhTHkEhdq/wlo27G3+HP5hnRE x7+8wcuItsbKwjtPpRuk5Fo8Q0BHkEZKnfF48iky7qZQ+LjGr709CcFN3b66pASPOjdr +cUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hY92A/8JkW6zB37HSUC6YiwaXy9HOEDWasRA8S9xbcA=; b=dKF7F8QCKWuQIK/isvxyRNzaztt5VtJiUhtav029Y7ToeHcszwKa5dTTMJB9k3BCbz h2oEbMyffolImjBti/Z6vfddkcQBfHOeBmkNkH/z15xROg8rTVzpEMF5bfIyQ7Ut8vaG XLbC2Tn9aeL8hsmhYpL7ec8qOzUPUE5IvWGlWN5K8HadP9JDhPsHPTg46O97/J8uQbca jSSE7Umfw/oJTzg7JzBjFqjqdQSWXcrjuaaAvmHpWQXFXtimWbWsOlI5F9+ZDDNPqWnm Dhy8jjFm4S+gz41t+M4dPEjojmKSX/s63kmHNTILiaC7kD6I3GVyqHG7GL+bpvL07OLy sJDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C+Bi21Gj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/16] target/ppc: Disconnect hflags from MSR Date: Sun, 14 Mar 2021 11:58:57 -0600 Message-Id: <20210314175906.1733746-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2d; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copying flags directly from msr has drawbacks: (1) msr bits mean different things per cpu, (2) msr has 64 bits on 64 cpus while tb->flags has only 32 bits. Create a enum to define these bits. Document the origin of each bit. This fixes the truncation of env->hflags to tb->flags, because we no longer have hflags bits set above bit 31. Most of the code in ppc_tr_init_disas_context is moved over to hreg_compute_hflags. Some of it is simple extractions from msr, some requires examining other cpu flags. Anything that is moved becomes a simple extract from hflags in ppc_tr_init_disas_context. Several existing bugs are left in ppc_tr_init_disas_context, where additional changes are required -- to be addressed in future patches. Remove a broken #if 0 block. Reported-by: Ivan Warren Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 24 ++++++++++++++++++ target/ppc/helper_regs.c | 55 ++++++++++++++++++++++++++++++++-------- target/ppc/translate.c | 55 ++++++++++++---------------------------- 3 files changed, 84 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fd13489dce..39f35b570c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -585,6 +585,30 @@ enum { POWERPC_FLAG_HID0_LE = 0x00400000, }; +/* + * Bits for env->hflags. + * + * Most of these bits overlap with corresponding bits in MSR, + * but some come from other sources. Be cautious when modifying. + */ +enum { + HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */ + HFLAGS_HV = 1, /* computed from MSR_HV and other state */ + HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ + HFLAGS_PR = 3, /* MSR_PR */ + HFLAGS_DR = 4, /* MSR_DR */ + HFLAGS_IR = 5, /* MSR_IR */ + HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ + HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ + HFLAGS_TM = 8, /* computed from MSR_TM */ + HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ + HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ + HFLAGS_FP = 13, /* MSR_FP */ + HFLAGS_SA = 22, /* MSR_SA */ + HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ +}; + /*****************************************************************************/ /* Floating point status and control register */ #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index a87e354ca2..0a746bffd7 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" @@ -87,24 +88,56 @@ void hreg_compute_mem_idx(CPUPPCState *env) void hreg_compute_hflags(CPUPPCState *env) { - target_ulong hflags_mask; + target_ulong msr = env->msr; + uint32_t ppc_flags = env->flags; + uint32_t hflags = 0; + uint32_t msr_mask; - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; + /* Some bits come straight across from MSR. */ + msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | + (1 << MSR_DR) | (1 << MSR_IR) | + (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); - if (env->flags & POWERPC_FLAG_HID0_LE) { + if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* * Note that MSR_LE is not set in env->msr_mask for this cpu, - * and so will never be set in msr or hflags at this point. + * and so will never be set in msr. */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); - env->hflags |= le << MSR_LE; + hflags |= le << MSR_LE; } + + if (ppc_flags & POWERPC_FLAG_BE) { + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + msr_mask |= 1 << MSR_SE; + } + + if (msr_is_64bit(env, msr)) { + hflags |= 1 << HFLAGS_64; + } + if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { + hflags |= 1 << HFLAGS_SPE; + } + if (ppc_flags & POWERPC_FLAG_VRE) { + msr_mask |= 1 << MSR_VR; + } + if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { + hflags |= 1 << HFLAGS_VSX; + } + if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { + hflags |= 1 << HFLAGS_TM; + } + +#ifndef CONFIG_USER_ONLY + if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { + hflags |= 1 << HFLAGS_HV; + } +#endif + + env->hflags = hflags | (msr & msr_mask); + hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..a9325a12e5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7879,67 +7879,48 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUPPCState *env = cs->env_ptr; + uint32_t hflags = ctx->base.tb->flags; int bound; ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; - ctx->pr = msr_pr; + ctx->pr = (hflags >> HFLAGS_PR) & 1; ctx->mem_idx = env->dmmu_idx; - ctx->dr = msr_dr; -#if !defined(CONFIG_USER_ONLY) - ctx->hv = msr_hv || !env->has_hv_mode; -#endif + ctx->dr = (hflags >> HFLAGS_DR) & 1; + ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; ctx->insns_flags2 = env->insns_flags2; ctx->access_type = -1; ctx->need_access_type = !mmu_is_64bit(env->mmu_model); - ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); + ctx->le_mode = (hflags >> HFLAGS_LE) & 1; ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; ctx->flags = env->flags; #if defined(TARGET_PPC64) - ctx->sf_mode = msr_is_64bit(env, env->msr); + ctx->sf_mode = (hflags >> HFLAGS_64) & 1; ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B || env->mmu_model == POWERPC_MMU_601 || env->mmu_model & POWERPC_MMU_64; - ctx->fpu_enabled = !!msr_fp; - if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { - ctx->spe_enabled = !!msr_spe; - } else { - ctx->spe_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { - ctx->altivec_enabled = !!msr_vr; - } else { - ctx->altivec_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx->vsx_enabled = !!msr_vsx; - } else { - ctx->vsx_enabled = false; - } + ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; + ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; + ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; + ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; if ((env->flags & POWERPC_FLAG_SCV) && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { ctx->scv_enabled = true; } else { ctx->scv_enabled = false; } -#if defined(TARGET_PPC64) - if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx->tm_enabled = !!msr_tm; - } else { - ctx->tm_enabled = false; - } -#endif + ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); - if ((env->flags & POWERPC_FLAG_SE) && msr_se) { - ctx->singlestep_enabled = CPU_SINGLE_STEP; - } else { - ctx->singlestep_enabled = 0; + + ctx->singlestep_enabled = 0; + if ((hflags >> HFLAGS_SE) & 1) { + ctx->singlestep_enabled |= CPU_SINGLE_STEP; } - if ((env->flags & POWERPC_FLAG_BE) && msr_be) { + if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } if ((env->flags & POWERPC_FLAG_DE) && msr_de) { @@ -7956,10 +7937,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } -#if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr_se = 1; -#endif bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns = MIN(ctx->base.max_insns, bound); From patchwork Sun Mar 14 17:58:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400100 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2836431jai; Sun, 14 Mar 2021 11:09:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtOhAiL870E46qjXCOSTPHGUhHbcmpw1ngG3qG30DHZgCOC9YKGKlklUB0FLyV6L2Gi+xS X-Received: by 2002:a6b:6e06:: with SMTP id d6mr5095311ioh.116.1615745347704; Sun, 14 Mar 2021 11:09:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745347; cv=none; d=google.com; s=arc-20160816; b=zB5MuQ/OdMs5Q9Wq18HrybzDVe6oNoD5It77ohDK1rGq0UkteAn6IIgojvA94eFcTI CrWyqRiN22kUplA33nIKI1buW3l0OwEb4lnUtnQORZbX74pE5tM334+REiGKqr3xAq0i LaGL4k61QMtElWiQMTjynz/gG/FK9BiipREJBtg2TznMu7EydVdgB0lltkVE11761pjq s55HUbMbFKdGGsOxlDWZY4dj7WhSjhpBkEvhHbplaIXcMPl0UZZ4hNutRh6t591jVa7f WJsSXIyyhDmCb2907BCn+pW/5P42nOF9iB9j3JibZzOTXDSln3Px8cxg/YjmT5XaJfDg nUxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/W2WFobHDD4oLw5DS+3Y+2H+mE4fKJy/+HfV/Ly0jXA=; b=gjjzHWjUsqvaMmRq1hL1BJflBup9b/GQu5f5eYQX+j+Xr8Bca5/tcvCs/MsV2RtS0b a2inJRI7QeVGemgbxqZOJeuejn+rrqAS5tTm6armFpYwkabmF5Jy5TFCe33ZHkI+FgQ5 Y8SLuJIiEDjeYCnzcU//FqZltg8UsZHow2kA6wYKlCpMrYzo/69iML6LA4rmayKGjeKc QA+Glb70EO92ZAr5LG9m7hKwBCreg737sOtbU1FXMB7QHr4BOUJzNuu5kgpXjCu+hrnA bkbgsRiG163EuzH9WSQX+zd1amFy+wmwelawB9Nmw1ZotX6PvdPvG0xozbtvgZJXWxBL L/TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=alFHopLV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/16] target/ppc: Reduce env->hflags to uint32_t Date: Sun, 14 Mar 2021 11:58:58 -0600 Message-Id: <20210314175906.1733746-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It will be stored in tb->flags, which is also uint32_t, so let's use the correct size. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/misc_helper.c | 2 +- target/ppc/translate.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 39f35b570c..2abaf56869 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1128,8 +1128,8 @@ struct CPUPPCState { bool resume_as_sreset; #endif - /* These resources are used only in QEMU core */ - target_ulong hflags; + /* These resources are used only in TCG */ + uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 63e3147eb4..b04b4d7c6e 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -199,7 +199,7 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ hreg_compute_hflags(env); - qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, + qemu_log("%s: set endianness to %c => %08x\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a9325a12e5..a85b890bb0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7657,7 +7657,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->nip, env->lr, env->ctr, cpu_read_xer(env), cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " - TARGET_FMT_lx " iidx %d didx %d\n", + "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, env->immu_idx, env->dmmu_idx); #if !defined(NO_TIMER_DUMP) From patchwork Sun Mar 14 17:58:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400093 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2831709jai; Sun, 14 Mar 2021 11:00:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBGfHs+QT8ABvFxU+37hsP8txDAtRM+r/wFmIEZC0y2BcvB97NYl+41phevtbG2rabW17v X-Received: by 2002:a92:540d:: with SMTP id i13mr9272495ilb.8.1615744843455; Sun, 14 Mar 2021 11:00:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615744843; cv=none; d=google.com; s=arc-20160816; b=q+vPe02v2lWCobpYVNhPT+YSI5/MzohGXhI+qPs9wU3CwYjQWYYsYhg/37zuZvYgzY 7+tSPRQLfMB3nClVvDSvOj+469BoqBjWQyNFuzv1XQAGS7cnhLsj56cqN9PQ+w4xcHiW ynkvrU7fqcRe0UFHStjycLjV6KnsgPadCFFVhadm0bjg7HzaJ8UrQTAEzJhuvYf/P+Lp jGE10kdkiKLMyzOQgB/99yzMAfcdYYDTqZBqyiqC4pJtugq+F6buoG3YUyQ0HmQuWN4m /Heg2duq2WQt2HhTZXxo3SaTDQNTBCwyy/iVE5F2xn07JJEDmVR+TCY2WP6vaV3YsIbI AV6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LL8bkt3cpcyBMDK/LZ6QT2j+SFhG/YMWEf75uL1t8Es=; b=iwYOTpHSmtBXjZqg3bZ3RQ1rOXvmduxqqZrOnW4E2M7+qflD7e8x2ECYmQdpO4u71M cSqxuP3yHQsIl23L6hswpLk3mS/I7HuQDBmzFymsH44GAD3gNIDAvZkSSw+MQoK7DC/x wimUfhkOLUpLggq7S/4uuJH/UNzgGlrDP4DWlurKkAcuDUl2rWEMWuGpgAqC5JwUmQm/ jAYr9Ws90jnjiqDRY01JNS/NyQg5qw5LVn3zC0pCEAL3u1+QSXCoSbFUl9ed02JUyuqm mOfTnMy3k2JEFXTbPeDm5SZTdHgXjguiYTR//gb59keHxXSCs+SFfwoMbYrEmZKWY3SY ysOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h8HtEOy1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/16] target/ppc: Put dbcr0 single-step bits into hflags Date: Sun, 14 Mar 2021 11:58:59 -0600 Message-Id: <20210314175906.1733746-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because these bits were not in hflags, the code generated for single-stepping on BookE was essentially random. Recompute hflags when storing to dbcr0. Signed-off-by: Richard Henderson --- target/ppc/helper_regs.c | 20 +++++++++++++++----- target/ppc/misc_helper.c | 3 +++ target/ppc/translate.c | 11 ----------- 3 files changed, 18 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 0a746bffd7..c735540333 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -107,11 +107,21 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= le << MSR_LE; } - if (ppc_flags & POWERPC_FLAG_BE) { - msr_mask |= 1 << MSR_BE; - } - if (ppc_flags & POWERPC_FLAG_SE) { - msr_mask |= 1 << MSR_SE; + if (ppc_flags & POWERPC_FLAG_DE) { + target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; + if (dbcr0 & DBCR0_ICMP) { + hflags |= 1 << HFLAGS_SE; + } + if (dbcr0 & DBCR0_BRT) { + hflags |= 1 << HFLAGS_BE; + } + } else { + if (ppc_flags & POWERPC_FLAG_BE) { + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + msr_mask |= 1 << MSR_SE; + } } if (msr_is_64bit(env, msr)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index b04b4d7c6e..a5ee1fd63c 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { + /* Bits 26 & 27 affect single-stepping */ + hreg_compute_hflags(env); + /* Bits 28 & 29 affect reset or shutdown. */ store_40x_dbcr0(env, val); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a85b890bb0..7912495f28 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } - if ((env->flags & POWERPC_FLAG_DE) && msr_de) { - ctx->singlestep_enabled = 0; - target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if (dbcr0 & DBCR0_ICMP) { - ctx->singlestep_enabled |= CPU_SINGLE_STEP; - } - if (dbcr0 & DBCR0_BRT) { - ctx->singlestep_enabled |= CPU_BRANCH_STEP; - } - - } if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } From patchwork Sun Mar 14 17:59:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400099 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2835446jai; Sun, 14 Mar 2021 11:07:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx+7KfENi08hAtj37i0AUyg7YHQO4XtLtF6ymVM3pb96bdGH2yRP+uUyXeePCLJTwSOE36f X-Received: by 2002:a05:6e02:178e:: with SMTP id y14mr4322589ilu.175.1615745244985; Sun, 14 Mar 2021 11:07:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745244; cv=none; d=google.com; s=arc-20160816; b=TvVaaLhQb/rHWrzCyQLEMjcSYwUaDRnecDl3xm5SQBeQxLjqeEYZnOPtPrLDqRjT0d YbcFMURyDLCh0tMkLOQK1qf8G3q3+OLIqkc4+sgaWeggQ3WdXD/+pSS16DRT1W0QfhUr Ia5yU0TfY6JFqyzM/rbRHqWBjIUJWlZfunz5UJ1agZ5eM8oigsfYK/RMpLDmtaOB1u9Q ZgBTaSLtr43xPlFeclt/FRBPyhAzjL1WRbefz5AX7wUO4NN6mpKrpTzDo3kgViFpYDSN b0W9by/yKsflCLe33CJQAtMK7M+X1FOyXcmKQMIcAzlYaJluR+zTGg7JEFnj9Y5kN5je oPJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nDEzeJHZqdUXe/dXYq7qR5PEy35VBqTIPDXHrdEdgcc=; b=dM+Sja0ZEQuImY0hD/qD9JZYmWumxrbWKE7JTWZ7JXT3BumXrjbKhN9iKALtnI6Yz4 x6KHQlKYz4xve/Nv3uYyH27Ik2lAtnOnPlfp55Q0VaEMJDKsiOJlYmYFwr5vmo7JxDPw D2K5Ubpub16leF0k1PTDJEXHrPUNuR0iP350A3P328rkzWZBkREMTZXE4yY55SbXaTwJ AvC0Gvb/kWqjhoUFDxtsbRuEviRxOkfvWwBeSI5LOHbT0/Qoha99v5FWxk/1EvqRfrjo Ukzw9GzrqP8vrMoeRWLhsaeTFpK+rwYoignBCtVw8HdJ8SHo/t49VJyuGA9q/XqjV30U WF9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g7cYJVkb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/16] target/ppc: Create helper_scv Date: Sun, 14 Mar 2021 11:59:00 -0600 Message-Id: <20210314175906.1733746-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform the test against FSCR_SCV at runtime, in the helper. This means we can remove the incorrect set against SCV in ppc_tr_init_disas_context and do not need to add an HFLAGS bit. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 1 + target/ppc/excp_helper.c | 9 +++++++++ target/ppc/translate.c | 20 +++++++------------- 3 files changed, 17 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..513066d54d 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -13,6 +13,7 @@ DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) +DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 85de7e6c90..5c95e0c103 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1130,6 +1130,15 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) } #if defined(TARGET_PPC64) +void helper_scv(CPUPPCState *env, uint32_t lev) +{ + if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { + raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); + } else { + raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); + } +} + void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) { CPUState *cs; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7912495f28..d48c554290 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -173,7 +173,6 @@ struct DisasContext { bool vsx_enabled; bool spe_enabled; bool tm_enabled; - bool scv_enabled; bool gtse; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -4081,15 +4080,16 @@ static void gen_sc(DisasContext *ctx) #if !defined(CONFIG_USER_ONLY) static void gen_scv(DisasContext *ctx) { - uint32_t lev; + uint32_t lev = (ctx->opcode >> 5) & 0x7F; - if (unlikely(!ctx->scv_enabled)) { - gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV); - return; + /* Set the PC back to the faulting instruction. */ + if (ctx->exception == POWERPC_EXCP_NONE) { + gen_update_nip(ctx, ctx->base.pc_next - 4); } + gen_helper_scv(cpu_env, tcg_constant_i32(lev)); - lev = (ctx->opcode >> 5) & 0x7F; - gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev); + /* This need not be exact, just not POWERPC_EXCP_NONE */ + ctx->exception = POWERPC_SYSCALL_VECTORED; } #endif #endif @@ -7907,12 +7907,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; - if ((env->flags & POWERPC_FLAG_SCV) - && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { - ctx->scv_enabled = true; - } else { - ctx->scv_enabled = false; - } ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); From patchwork Sun Mar 14 17:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400104 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2838692jai; Sun, 14 Mar 2021 11:13:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsQq8nQbHzXwaecaDQCXMw2M1vF2ckXlLOS9oVZW5+CwWFzaiHTSXcBQtYmLGLWO6rgdAV X-Received: by 2002:a05:6e02:d4e:: with SMTP id h14mr9061083ilj.80.1615745610052; Sun, 14 Mar 2021 11:13:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745610; cv=none; d=google.com; s=arc-20160816; b=h52ZZrXccgalAoUtSE3L1t4B2+DuQEVy4XKjXYp9C8xIRiyHM1fPzYfUnIHZNbygyx lDVkw58o4HMxuxd6ISzoJFFAbPkJ9Al89QkcgBdOQkKYozT0GkBTmj7iUTbTfAfTvJ/m VKyhXFn4DIcVRVMzxyJ+/qXq2bql4xBfJ+MyPhJOtL91J+sirch9Lkrx2xX+YTKsVM94 j6jSHXQGyTJtgKMBCIbAj4y5bXlF973IPDzccdJORXKdleKz0pWS0FEShYk55WjVBlv4 M/Y3BtPxQ3LiM0XjvVzPQPc1C8E8GMZyl2YsNUiljNYQp5b1DnZz8uSDNlENCdzRSktk 2xGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Fm4BN1FAYzcobXIUNrNdXuRiaQp/Ku74cUVfr1tQ2mY=; b=n2Ab3MP7Nk5RpKWgO2FTUZTjziYj8knmQQskYMhHhoB4NUFBv8viieOQXDF+hbnntd YaXJEuJxpkep84c29r5y6DC9DHFiWG+ykucfGIuMq+4pcHao2JW91Im1jYq9brg1QEns W6gu9P9YqIgrfal8VdiqhcdWllqkmkybq1izXA/Gh9LXKLlcknC4+H/iYeyCa/UAmjge KGp11c9FXXpTRFXpfHJHpPIVdOaoYeegpsrHe8/jIIi2b0I0J/+Jg/m24awCEHoVC6kD ba4lGpPWFhuCIqJPxNgw9jAnOABPncQJqiWEKcmaJqD6GZDXI7uuSiJhzXnjsIGU4u6R apWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rMuju3Ya; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/16] target/ppc: Put LPCR[GTSE] in hflags Date: Sun, 14 Mar 2021 11:59:01 -0600 Message-Id: <20210314175906.1733746-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because this bit was not in hflags, the privilege check for tlb instructions was essentially random. Recompute hflags when storing to LPCR. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 1 + target/ppc/helper_regs.c | 3 +++ target/ppc/mmu-hash64.c | 3 +++ target/ppc/translate.c | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2abaf56869..07a4331eec 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -603,6 +603,7 @@ enum { HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ + HFLAGS_GTSE = 11, /* computed from SPR_LPCR[GTSE] */ HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_SA = 22, /* MSR_SA */ HFLAGS_AP = 23, /* MSR_AP */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index c735540333..8479789e24 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -139,6 +139,9 @@ void hreg_compute_hflags(CPUPPCState *env) if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; } + if (env->spr[SPR_LPCR] & LPCR_GTSE) { + hflags |= 1 << HFLAGS_GTSE; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0fabc10302..d517a99832 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "hw/hw.h" #include "mmu-book3s-v3.h" +#include "helper_regs.h" /* #define DEBUG_SLB */ @@ -1125,6 +1126,8 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; + /* The gtse bit affects hflags */ + hreg_compute_hflags(env); } void helper_store_lpcr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d48c554290..5e629291d3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7908,7 +7908,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; - ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); + ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { From patchwork Sun Mar 14 17:59:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400096 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2834708jai; Sun, 14 Mar 2021 11:05:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUxv2w2A1fKZPq2PxldEgrctUij9GhN3qt63vqyEUN9c/ZWiNiFXniCNZtzK0HLfyz7Rgb X-Received: by 2002:a02:6014:: with SMTP id i20mr6610777jac.101.1615745156661; Sun, 14 Mar 2021 11:05:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745156; cv=none; d=google.com; s=arc-20160816; b=YPJG7woNzzHksV7dE6C9jzirwx5BJUXEjFs/GIGgAS3sRMD0caCEbtt0+ozzM57k6T fnxssjjdMzR2ZJ9KVUij1mqGV74TlpgnoDSXu2c0a8P1tXIVV7cwmC/5/Tx74CdG7BzT XOwEpuOrBS6x1T0uqQRRyMOJnDUAyPiPo2xbUAU4CyV1rEInejSO3zhoApz0X88N39JO LlVbul3XF8yvZPEajhyLSttvPyCNlm6OULriG4a6KKBSn90/oisgwmPr321Iv3bicgUK E6lPNWRVBZCqm5tqdDDq8jJl0sgcki213/kuW+h07m/pVS3KzW6jcQFpTRXmCARBN5gW bwuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bCT8Z895v2OzlUZ7cD3kW9yujJdvuk9uwCXjA4T3jIk=; b=GbnqrTDdl0vugLCZnkR353u7RDHu49e5aRNY6/HXN81WGu2Y1MeAVC/lRgIc0k5q1u C+Y2Vso58Ty9LpjZw4TIEA93xVBTPLtZqBG0elTmGjMPy2qG0mW4dOLg6Fn92nTkb8mU mL4hOIzfMK9ViyvbBdVbFu7eI1DFkfVHU/etEYpKMn+7oW2oCzNdnBieoFOHl9ZKrUTm BiHfSMgZw41eVGC044TkyKVoUpy3kCH6jRQ29u9UocSR3zSWQvcYcbyWEtmOQkELVPQg Ywb73mW8AsVSjDa4kPx/56feDso9bx/jJcxukP6lB5nr5iyndVlre9mcLDqJPrcR6Y93 UE6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YhTW0sAs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/16] target/ppc: Remove MSR_SA and MSR_AP from hflags Date: Sun, 14 Mar 2021 11:59:02 -0600 Message-Id: <20210314175906.1733746-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Nothing within the translator -- or anywhere else for that matter -- checks MSR_SA or MSR_AP on the 602. This may be a mistake. However, for the moment, we need not record these bits in hflags. This allows us to simplify HFLAGS_VSX computation by moving it to overlap with MSR_VSX. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 4 +--- target/ppc/helper_regs.c | 7 +++---- 2 files changed, 4 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 07a4331eec..23ff16c154 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -599,14 +599,12 @@ enum { HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ - HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ HFLAGS_GTSE = 11, /* computed from SPR_LPCR[GTSE] */ HFLAGS_FP = 13, /* MSR_FP */ - HFLAGS_SA = 22, /* MSR_SA */ - HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ }; diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8479789e24..d62921c322 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -95,8 +95,7 @@ void hreg_compute_hflags(CPUPPCState *env) /* Some bits come straight across from MSR. */ msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | - (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); + (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -133,8 +132,8 @@ void hreg_compute_hflags(CPUPPCState *env) if (ppc_flags & POWERPC_FLAG_VRE) { msr_mask |= 1 << MSR_VR; } - if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { - hflags |= 1 << HFLAGS_VSX; + if (ppc_flags & POWERPC_FLAG_VSX) { + msr_mask |= 1 << MSR_VSX; } if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; From patchwork Sun Mar 14 17:59:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400107 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2839324jai; Sun, 14 Mar 2021 11:14:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxxf6sha644q/Ksf46deTq1EWSe92OWW5zNow34Gy7qLPOtTyxFEoL46QarQF/EYTtOK1N6 X-Received: by 2002:a25:2cce:: with SMTP id s197mr33846288ybs.88.1615745698099; Sun, 14 Mar 2021 11:14:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745698; cv=none; d=google.com; s=arc-20160816; b=JiAmtqQ/yUf0OkYhAu5syFmTJN4eYO2MbwdIAlX+HWOr2hfd+zzbWc1/+SeltNAoMv dljuNSJt/smwGGoRknapFQakIvJO2b49KT8+N7TtrsBMiKuYFkfbuI8PZOVIaZygEDnZ 1M05X+GJewwdKg4cC1I9i2N65Lr3ew7SKphfPvhfYIgoj/UixmwBA60m0QXf340jtMsf cWWUSRg63tY5Y+/OFGX5hIQMq37F/tttnaZ58oVzUEcLBuEtUcJMktv11aAvTIOJpCWw AroXA77F6d72UCvpyKB3k7S8TNhKo0ToQ/irmbWDOXaIHBHWznw+Kk0ZVS1C9LWRB+9w tL2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WgTBRUnu7J8koNQdxGgffOswXs7sxkMr5Aqor7q7qKI=; b=OSTBGRyCWmn5oBI8NZahb+ZZHgTlApVhutEBdBuETr2e+exidvYXzD8s1phhqAKoK4 e2WjyPQvahZHU+sm/tbGo9yD/HiLzyt7geZ/BMau6+h/b6h2Wa+9tjI8EkbtBJpFMK43 /IrC635z9QF86FaRsNfjF3JoC/AETrgy2qdZ/E2w1FE0y5NnoW9MTPv4HQFZm34RY++S A5dCmtyCZVNYvvwlJq6RHcwh5iHB7pA0YafZdOtapPSOxPqRcNfZldaj5OjStviyDy6d 8gYL3d6VdZWxe7Mkj7Da2yFBIzsU1mpW0Pzknm48mkpYIdDxqIGyYID1z6aysiBZln7C EamA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="D+l3/n+z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/16] target/ppc: Remove env->immu_idx and env->dmmu_idx Date: Sun, 14 Mar 2021 11:59:03 -0600 Message-Id: <20210314175906.1733746-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We weren't recording MSR_GS in hflags, which means that BookE memory accesses were essentially random vs Guest State. Instead of adding this bit directly, record the completed mmu indexes instead. This makes it obvious that we are recording exactly the information that we need. This also means that we can stop directly recording MSR_IR. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 12 ++++-- target/ppc/helper_regs.h | 1 - target/ppc/helper_regs.c | 88 ++++++++++++++++++++-------------------- target/ppc/mem_helper.c | 2 +- target/ppc/translate.c | 6 +-- 5 files changed, 55 insertions(+), 54 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 23ff16c154..2f8d7fa13c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -597,7 +597,6 @@ enum { HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ HFLAGS_PR = 3, /* MSR_PR */ HFLAGS_DR = 4, /* MSR_DR */ - HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ @@ -606,6 +605,9 @@ enum { HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ + + HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */ + HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */ }; /*****************************************************************************/ @@ -1130,8 +1132,6 @@ struct CPUPPCState { /* These resources are used only in TCG */ uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ - int immu_idx; /* precomputed MMU index to speed up insn accesses */ - int dmmu_idx; /* precomputed MMU index to speed up data accesses */ /* Power management */ int (*check_pow)(CPUPPCState *env); @@ -1367,7 +1367,11 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define MMU_USER_IDX 0 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) { - return ifetch ? env->immu_idx : env->dmmu_idx; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; +#endif } /* Compatibility modes */ diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 4148a442b3..42f26870b9 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -21,7 +21,6 @@ #define HELPER_REGS_H void hreg_swap_gpr_tgpr(CPUPPCState *env); -void hreg_compute_mem_idx(CPUPPCState *env); void hreg_compute_hflags(CPUPPCState *env); void cpu_interrupt_exittb(CPUState *cs); int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index d62921c322..b28037ca24 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,49 +43,6 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - void hreg_compute_hflags(CPUPPCState *env) { target_ulong msr = env->msr; @@ -95,7 +52,7 @@ void hreg_compute_hflags(CPUPPCState *env) /* Some bits come straight across from MSR. */ msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); + (1 << MSR_DR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -146,10 +103,51 @@ void hreg_compute_hflags(CPUPPCState *env) if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { hflags |= 1 << HFLAGS_HV; } + + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + unsigned immu_idx, dmmu_idx; + dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; + if (env->mmu_model & POWERPC_MMU_BOOKE) { + dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; + dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; + } else { + dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; + dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; + } + hflags |= immu_idx << HFLAGS_IMMU_IDX; + hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif env->hflags = hflags | (msr & msr_mask); - hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index f4f7e730de..444b2a30ef 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -278,7 +278,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr, target_ulong mask, dcbz_size = env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx; + int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5e629291d3..a53463b9b8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7658,8 +7658,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", - env->msr, env->spr[SPR_HID0], - env->hflags, env->immu_idx, env->dmmu_idx); + env->msr, env->spr[SPR_HID0], env->hflags, + cpu_mmu_index(env, true), cpu_mmu_index(env, false)); #if !defined(NO_TIMER_DUMP) qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 #if !defined(CONFIG_USER_ONLY) @@ -7885,7 +7885,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; ctx->pr = (hflags >> HFLAGS_PR) & 1; - ctx->mem_idx = env->dmmu_idx; + ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; ctx->dr = (hflags >> HFLAGS_DR) & 1; ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; From patchwork Sun Mar 14 17:59:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400103 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2837326jai; Sun, 14 Mar 2021 11:10:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+Yd4YZaUo7lECv9y57HK0SR8CNVcSfkT7cSjDZzDlKM98Wr5iPiwj3hwbdtSTsEFt3DZo X-Received: by 2002:a6b:b2cd:: with SMTP id b196mr5385700iof.67.1615745443369; Sun, 14 Mar 2021 11:10:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745443; cv=none; d=google.com; s=arc-20160816; b=nxyoy+ve8UJLn9haZG8V4IFGuoGURcRbzUF8ygo3wXbMBNDnHknSW7dOyZ7pqdOBKL j7GM3Cpp1D2oR35MEJCp6MntpzK/4THIIOz4seg11FRPjSby9xbKVa2X2ZHFkTyAiKpP VSAd7jQtkfSxihrzmAHs/RH9YgCK4fYcf2MP4kmW0J+fLej+6vlYVKY3AuoGfqITiqbG m9d2Veaekj1sLGE5mYbFa+ODSNhEV3kTW4+qR7IdJDQVSIvH6U2Y1JHd2LpxRCLydve+ 0HzsevFF2vpZTxZ8KYm1cDriuUQ8IcBnB1+0ZvBGpMdDPOxQIVwZ0L9VM74nfrGOEtQk WlEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vELE3YSpOk5r/uHFU87DvdYSf1TzMJkyUqmnTwvrjhM=; b=KsWrqXnC0lQ4VGRIiLwBpMwR5q2k/3aHaeMRWYPZ+VVd8ZcuB3NRVsfsUNLzJb85vX FKaCge5DTrB4MEyxtDqG9UHzViZ68yAUmHizC1H1TY0z/1Ea7WVpNCtyTbV13Q4unDld 6owJHhAKVZ8Yd1mHVMgUAPsWyyfpzgdSPdLS2l6v8jcwl1vAyaDsyy2B6uTq9PrF8RzF 9Cd7ZD+ltgXljy81GI3uHCFaUDKFUBdO/VO5iDIWqQytoERPNdk7EVjXb+r5oXif0etu ygePGbHixI6OVmtVfKfLbtsvDBvbPxLyOgt+WAphOvh/eqlDiZZ7kTCyMEhzyaQhcbFH 3Q3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="V/ewIlIi"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/16] hw/ppc: Use hreg_store_msr for msr updates Date: Sun, 14 Mar 2021 11:59:04 -0600 Message-Id: <20210314175906.1733746-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, Greg Kurz , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only one of the three places in hw/ppc that modify msr updated hflags. Even in that case, use the official interface instead of a direct call to hreg_compute_hflags. Signed-off-by: Richard Henderson --- Cc: Cédric Le Goater Cc: Greg Kurz --- hw/ppc/pnv_core.c | 3 ++- hw/ppc/spapr_hcall.c | 3 +-- hw/ppc/spapr_rtas.c | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index bd2bf2e044..31f041b9c7 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -29,6 +29,7 @@ #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "helper_regs.h" static const char *pnv_core_cpu_typename(PnvCore *pc) { @@ -54,7 +55,7 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) */ env->gpr[3] = PNV_FDT_ADDR; env->nip = 0x10; - env->msr |= MSR_HVB; /* Hypervisor mode */ + hreg_store_msr(env, env->msr | MSR_HVB, true); /* Hypervisor mode */ env->spr[SPR_HRMOR] = pc->hrmor; diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..a4f7a09ba8 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1055,8 +1055,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, CPUState *cs = CPU(cpu); SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); - env->msr |= (1ULL << MSR_EE); - hreg_compute_hflags(env); + hreg_store_msr(env, env->msr | (1ULL << MSR_EE), false); if (spapr_cpu->prod) { spapr_cpu->prod = false; diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8a79f9c628..b9a6b7ef30 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -51,6 +51,7 @@ #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" #include "migration/blocker.h" +#include "helper_regs.h" static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, @@ -162,7 +163,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, cpu_synchronize_state(CPU(newcpu)); - env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); + hreg_store_msr(env, (1ULL << MSR_SF) | (1ULL << MSR_ME), true); /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ lpcr = env->spr[SPR_LPCR]; From patchwork Sun Mar 14 17:59:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400105 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2838868jai; Sun, 14 Mar 2021 11:13:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwhyuLn2Vc5zSTPzd85tujSbp/VX+l8oPCo9vhcI54sV0uYOELg2vUB/8LLOV2ICi9nmIkY X-Received: by 2002:a25:23c6:: with SMTP id j189mr31900701ybj.211.1615745633659; Sun, 14 Mar 2021 11:13:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1615745633; cv=none; d=google.com; s=arc-20160816; b=czoibowouCRvJBby8BtJ9clXZSsiHGR4Iaq7ORiQREJomUE0I4BjjPfq4zGewMZqD/ gqGy6pzrj/6fNU3XTdEoje5VK3jAw2PmvYso7kwwXYRd7+Vy3uDYMtl5+AByfCzJLjew YsG7Hia9MNwwTMO0bTswEH3yte2EOI6BDUYGAveYCVLHDJ8vmnNNyCrhV97FUS5hHY4K oDNDiQiIO+Fc+YHGrM6Gx1fuTkTEA1VGuLl56bha86GzffDQ+hu5y0Wa3To+OnvNKKfq UYM26j9INGrDat+E6vLFXb3VObTUG2YI3eP7Hcszy0jXEnY8tQ+E1rvNRiReCEy+hCgv jSwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GP7KN1O/N4US4bdn1IcXHif9taZ0y5n50rRX2Q2HUDY=; b=BZG+zXzOUPJxtrgZ7NRfJN7nVmTw5snBkuwhaXs1A8NLHCQJoJ9LkwcDQT42kBSKF1 xr7fHioUIwhYf878hLbu5l+Gwt8FveTvnO1rRnaKEZ10ZRTpYO31d9kp9alFOx/QExfw TmosgnZxHLUQpYnFWX+0QPgY2rNPYvGaeoom2BPrC3X6VFHSV8tqI9lnPnXTZHV5207x tWwyU3/MjiBLjLmrVcUTKcM8TVtkoEDd6GQ/wApGg2yBKJg/PlXjxwFznAoS9tRr9JBK iV8Em66x83UWFZqbvnGmrcb3td/dXjDP4rGsuyFJpbASxVBIQ+BN60bDzf1lfwrnqXlM wAZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ERH8veWo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/16] linux-user/ppc: Fix msr updates Date: Sun, 14 Mar 2021 11:59:05 -0600 Message-Id: <20210314175906.1733746-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In save_user_regs, there are two bugs where we OR in a bit number instead of the bit, clobbering the low bits of MSR. However: The MSR_VR and MSR_SPE bits control the availability of the insns. If the bits were not already set in MSR, then any attempt to access those registers would result in SIGILL. For linux-user, we always initialize MSR to the capabilities of the cpu. We *could* add checks vs MSR where we currently check insn_flags and insn_flags2, but we know they match. Also, there's a stray cut-and-paste comment in restore. Then, do not force little-endian binaries into big-endian mode. Finally, use ppc_store_msr for the update to affect hflags. Which is the reason none of these bugs were previously noticed. Signed-off-by: Richard Henderson --- linux-user/ppc/cpu_loop.c | 5 +++-- linux-user/ppc/signal.c | 23 +++++++++++------------ 2 files changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index df71e15a25..4a0f6c8dc2 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -492,11 +492,12 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) #if defined(TARGET_PPC64) int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; #if defined(TARGET_ABI32) - env->msr &= ~((target_ulong)1 << flag); + ppc_store_msr(env, env->msr & ~((target_ulong)1 << flag)); #else - env->msr |= (target_ulong)1 << flag; + ppc_store_msr(env, env->msr | (target_ulong)1 << flag); #endif #endif + env->nip = regs->nip; for(i = 0; i < 32; i++) { env->gpr[i] = regs->gpr[i]; diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index b78613f7c8..bad38f8ed9 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -261,9 +261,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VR in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_VR; #if defined(TARGET_PPC64) vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; /* 64-bit needs to put a pointer to the vectors in the frame */ @@ -300,9 +297,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); } - /* Set MSR_SPE in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_SPE; __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); } #endif @@ -354,8 +348,10 @@ static void restore_user_regs(CPUPPCState *env, __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); /* If doing signal return, restore the previous little-endian mode. */ - if (sig) - env->msr = (env->msr & ~(1ull << MSR_LE)) | (msr & (1ull << MSR_LE)); + if (sig) { + ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | + (msr & (1ull << MSR_LE)))); + } /* Restore Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { @@ -376,8 +372,6 @@ static void restore_user_regs(CPUPPCState *env, __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VEC in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ #if defined(TARGET_PPC64) vrsave = (uint32_t *)&v_regs[33]; #else @@ -468,7 +462,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); unlock_user_struct(frame, frame_addr, 1); return; @@ -563,8 +557,13 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; #endif +#ifdef TARGET_WORDS_BIGENDIAN /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); +#else + /* Signal handlers are entered in little-endian mode. */ + ppc_store_msr(env, env->msr | (1ull << MSR_LE)); +#endif unlock_user_struct(rt_sf, rt_sf_addr, 1); return; From patchwork Sun Mar 14 17:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 400109 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2841481jai; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/16] target/ppc: Validate hflags with CONFIG_DEBUG_TCG Date: Sun, 14 Mar 2021 11:59:06 -0600 Message-Id: <20210314175906.1733746-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82f; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Verify that hflags was updated correctly whenever we change cpu state that is used by hflags. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 5 +++++ target/ppc/helper_regs.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2f8d7fa13c..7ee5c9a66e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2424,6 +2424,10 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags); +#else static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { @@ -2431,6 +2435,7 @@ static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, *cs_base = 0; *flags = env->hflags; } +#endif void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index b28037ca24..9df1098fec 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,7 +43,7 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_hflags(CPUPPCState *env) +static uint32_t hreg_compute_hflags_value(CPUPPCState *env) { target_ulong msr = env->msr; uint32_t ppc_flags = env->flags; @@ -147,9 +147,34 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif - env->hflags = hflags | (msr & msr_mask); + return hflags | (msr & msr_mask); } +void hreg_compute_hflags(CPUPPCState *env) +{ + env->hflags = hreg_compute_hflags_value(env); +} + +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + uint32_t hflags_current = env->hflags; + uint32_t hflags_rebuilt; + + *pc = env->nip; + *cs_base = 0; + *flags = hflags_current; + + hflags_rebuilt = hreg_compute_hflags_value(env); + if (unlikely(hflags_current != hflags_rebuilt)) { + cpu_abort(env_cpu(env), + "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", + hflags_current, hflags_rebuilt); + } +} +#endif + void cpu_interrupt_exittb(CPUState *cs) { if (!kvm_enabled()) {