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[209.132.180.67]) by mx.google.com with ESMTP id p84si331208pfa.180.2018.04.26.19.56.04; Thu, 26 Apr 2018 19:56:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=k3KhfW2h; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757352AbeD0C4D (ORCPT + 29 others); Thu, 26 Apr 2018 22:56:03 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:43907 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757291AbeD0C4A (ORCPT ); Thu, 26 Apr 2018 22:56:00 -0400 Received: by mail-pf0-f196.google.com with SMTP id j11so363120pff.10; Thu, 26 Apr 2018 19:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=lLaYir9fo/gzqpZV3NgYIW7bx4xHltOLwyg7NLUydss=; b=k3KhfW2hUnmc04T61zEynKks6C7vidLncbRiBt+vtYK8veWaXn5VLFBseh7iB1vF8p vb2jK4Vi9xz0XMUa6LtUFlLkw+c+0jnOlEYxQy89O7GzS75rh6Ues8JImXt5cxw4AGAM ammw1X3sfhRHIOPe9vAK93ZAuHI9o4jWvABp773HQ/9ZVBzVQbbe4SYfIwxBod1mPSa1 WSaMh8qrot44X9YHu/GEgy2kfvEL6YaxQ9Or4nSqnu4RGDfJf9FyQp7ineB3MKrOzBWR UxH5saIrKoBdXT9Hc2bmu7KOkMaJjGnSFFqkrMyUH2f0wtxYeCLzZTNczvfeSOH2LOXz eqhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=lLaYir9fo/gzqpZV3NgYIW7bx4xHltOLwyg7NLUydss=; b=j8yIdnz42QuQNgzklrVQgn+H1VuhiDz7Jx8GyJruCHh8e4QLsqgxKw4rwse37G7xtp vjbRCHQf9LeB6/zyUrECpFKOwXeURBf3rykA9fD9S/wtzJV9x1/Qp/syf53VgN1afZpf vzF17L0iR+rjHPvYdtIliRQSuPTwquVKd9OowMidiBdxQvaP8qBN6iPqrJPUq7ySjKWl 7bAG0PENgJ6coPeS8CnbNn6fj6oq1PEC4yuKAUEhAmK8BsNJjL40aCc9Zuft42QXqmQn FZtx2Q8fu7pjgLOSo4irbRyWQMOHfM8A+eS7zLtljI8h3GfJrmizdmoT4HaBATbHk7VF lycQ== X-Gm-Message-State: ALQs6tDJ31WijMxMnAa/tRob1qo2gWj/fMbAS0gx3Phzi7WC0rKT5oh/ qJIira4d1k4V2Kwh4RJXI/g= X-Received: by 2002:a65:600a:: with SMTP id m10-v6mr522072pgu.281.1524797759495; Thu, 26 Apr 2018 19:55:59 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id h1-v6sm299609pgf.93.2018.04.26.19.55.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Apr 2018 19:55:58 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 27 Apr 2018 12:25:50 +0930 From: Joel Stanley To: Michael Turquette , Stephen Boyd Cc: Andrew Jeffery , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ryan Chen , Jae Hyun Yoo Subject: [PATCH v2] clk: aspeed: Support second reset register Date: Fri, 27 Apr 2018 12:25:47 +0930 Message-Id: <20180427025547.14115-1-joel@jms.id.au> X-Mailer: git-send-email 2.17.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- v2: This commit fixes a bug in aspeed_reset_assert() which determines the second reset register using condition. drivers/clk/clk-aspeed.c | 44 +++++++++++++++++++----- include/dt-bindings/clock/aspeed-clock.h | 1 + 2 files changed, 37 insertions(+), 8 deletions(-) -- 2.17.0 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index c7cb1f2b6f8a..1fbf45738535 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -16,6 +16,8 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET2_OFFSET 32 + #define ASPEED_RESET_CTRL 0x04 #define ASPEED_CLK_SELECTION 0x08 #define ASPEED_CLK_STOP_CTRL 0x0c @@ -30,6 +32,7 @@ #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) #define ASPEED_CLK_SELECTION_2 0xd8 +#define ASPEED_RESET_CTRL2 0xd4 /* Globally visible clocks */ static DEFINE_SPINLOCK(aspeed_clk_lock); @@ -291,6 +294,7 @@ struct aspeed_reset { #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) static const u8 aspeed_resets[] = { + /* SCU04 resets */ [ASPEED_RESET_XDMA] = 25, [ASPEED_RESET_MCTP] = 24, [ASPEED_RESET_ADC] = 23, @@ -300,38 +304,62 @@ static const u8 aspeed_resets[] = { [ASPEED_RESET_PCIVGA] = 8, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + + /* + * SCUD4 resets start at an offset to separate them from + * the SCU04 resets. + */ + [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, }; static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 rst = BIT(aspeed_resets[id]); + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; + + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } - return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); + return regmap_update_bits(ar->map, reg, BIT(bit), 0); } static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 rst = BIT(aspeed_resets[id]); + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; - return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } + + return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); } static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct aspeed_reset *ar = to_aspeed_reset(rcdev); - u32 val, rst = BIT(aspeed_resets[id]); - int ret; + u32 reg = ASPEED_RESET_CTRL; + u32 bit = aspeed_resets[id]; + int ret, val; + + if (bit >= ASPEED_RESET2_OFFSET) { + bit -= ASPEED_RESET2_OFFSET; + reg = ASPEED_RESET_CTRL2; + } - ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + ret = regmap_read(ar->map, reg, &val); if (ret) return ret; - return !!(val & rst); + return !!(val & BIT(bit)); } static const struct reset_control_ops aspeed_reset_ops = { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index d3558d897a4d..513c1b4af7a8 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -48,5 +48,6 @@ #define ASPEED_RESET_PCIVGA 6 #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 +#define ASPEED_RESET_CRT1 9 #endif