From patchwork Thu Mar 11 23:12:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 397732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA8F0C43331 for ; Thu, 11 Mar 2021 23:16:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB7D064FB3 for ; Thu, 11 Mar 2021 23:16:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231241AbhCKXPe (ORCPT ); Thu, 11 Mar 2021 18:15:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229688AbhCKXP0 (ORCPT ); Thu, 11 Mar 2021 18:15:26 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD8ECC061574; Thu, 11 Mar 2021 15:15:25 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id k8so730714wrc.3; Thu, 11 Mar 2021 15:15:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JQcxIpkyylyA7UoRXMcT1ZE3NtoucJDiZ4XXJPRfnPM=; b=BO8LN4VY0lLh3JtU77B/dACoYsgEsFQ2L9cKTY4K/Pdr4kHAa/4qUsT8G3RSt+/Ldr RKufCQumwdk/cb8/PH9F+MSRPw61iUlim4EqjMm8/q7WOGquN9ORtk7nTsCXwivtthV0 6EBk1lG5NNHMTLm9gS5Dzd72VFVnABvq57gbCXm488fbuL18GH5+/T/qkd7+5YBSSFNT l1/oJv4620S3E3j+C3ijcZRhIEYS4cQiZIbaFbFqqi3bJTce6xXfEWersY78RobhOvOO Nt6KQxxVsik9apZiLyQro/C7Rb/V4OxOgTeR0P/qjr79GqjKkFCjfp0Z+6ad1MBb2YGP QVwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JQcxIpkyylyA7UoRXMcT1ZE3NtoucJDiZ4XXJPRfnPM=; b=kPfg7bAbDHMfKNI6yChO+jcx1o+SMITnACQtwlWgRBvFwTWduQMnJY0n+a4xi6cR4D 8nlwWlaLlPmS4ZL3mXKpNvWNFiONl35no1ccyhwyjgDM5z0pwz1g+9pJWZVCGkeQ7p00 H9/4i5KVhS940kT8Z6UVh38ZdC/fqNaAl6YGIkf/+Tb3L3BIR7ehjetXaYObEsoSsnqn UslW77dFeFk0DzJTBBeDWQZSPIjgdB8YYKfJirG72HW8MscORJi6UzQnJDOoAQi0W2PL qKkvPVCJ8JbGU4kz9no2Du1JLnnRJQd6Crod7pMcUKyf1ssCbbsgVZzCfNQ0L1j1mpp0 prJg== X-Gm-Message-State: AOAM532gaTx7WejALvhh7W4gv56MVw9EUYClAHOoeQqSG+cX2pVj3oTY Flrua3Afi9t2Wcnz+TBU9lI= X-Google-Smtp-Source: ABdhPJzQiycmefLxJilSrx+Vhvn+SRoBN2MSt9sNOPgYJk+6YeN4hT6i3/0/oUbfbSnCEhVmCqyvHA== X-Received: by 2002:adf:f144:: with SMTP id y4mr11128417wro.408.1615504524463; Thu, 11 Mar 2021 15:15:24 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id j203sm263918wmj.40.2021.03.11.15.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 15:15:24 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Date: Fri, 12 Mar 2021 02:12:03 +0300 Message-Id: <20210311231208.18180-2-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311231208.18180-1-digetx@gmail.com> References: <20210311231208.18180-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add common helper which initializes OPP table for Tegra SoC core devices. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/common.c | 138 +++++++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 30 ++++++++ 2 files changed, 168 insertions(+) diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 3dc54f59cafe..6d9110fd3645 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -3,9 +3,16 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ +#define dev_fmt(fmt) "tegra-soc: " fmt + +#include +#include +#include #include +#include #include +#include static const struct of_device_id tegra_machine_match[] = { { .compatible = "nvidia,tegra20", }, @@ -31,3 +38,134 @@ bool soc_is_tegra(void) return match != NULL; } + +static int tegra_core_dev_init_opp_state(struct device *dev) +{ + struct dev_pm_opp *opp; + unsigned long rate; + struct clk *clk; + int err; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clk: %pe\n", clk); + return PTR_ERR(clk); + } + + /* + * If voltage regulator presents, then we could select the fastest + * clock rate, but driver doesn't support power management and + * frequency scaling yet, hence the top freq OPP will vote for a + * very high voltage that will produce lot's of heat. Let's select + * OPP for the current/default rate for now. + * + * Clock rate should be pre-initialized (i.e. it's non-zero) either + * by clock driver or by assigned clocks in a device-tree. + */ + rate = clk_get_rate(clk); + if (!rate) { + dev_err(dev, "failed to get clk rate\n"); + return -EINVAL; + } + + /* find suitable OPP for the clock rate and supportable by hardware */ + opp = dev_pm_opp_find_freq_ceil(dev, &rate); + + /* + * dev_pm_opp_set_rate() doesn't search for a floor clock rate and it + * will error out if default clock rate is too high, i.e. unsupported + * by a SoC hardware version. Hence will find floor rate by ourselves. + */ + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dev, &rate); + + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP for %ld Hz: %d\n", + rate, err); + return err; + } + + dev_pm_opp_put(opp); + + /* + * First dummy rate-set initializes voltage vote by setting voltage + * in accordance to the clock rate. We need to do this because some + * drivers currently don't support power management and clock is + * permanently enabled. + */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + return err; + } + + return 0; +} + +/** + * devm_tegra_core_dev_init_opp_table() - initialize OPP table + * @dev: device for which OPP table is initialized + * @params: pointer to the OPP table configuration + * + * This function will initialize OPP table and sync OPP state of a Tegra SoC + * core device. + * + * Return: 0 on success or errorno. + */ +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + struct opp_table *opp_table; + u32 hw_version; + int err; + + opp_table = devm_pm_opp_set_clkname(dev, NULL); + if (IS_ERR(opp_table)) { + dev_err(dev, "failed to set OPP clk %pe\n", opp_table); + return PTR_ERR(opp_table); + } + + /* Tegra114+ doesn't support OPP yet */ + if (!of_machine_is_compatible("nvidia,tegra20") && + !of_machine_is_compatible("nvidia,tegra30")) + return -ENODEV; + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + opp_table = devm_pm_opp_set_supported_hw(dev, &hw_version, 1); + if (IS_ERR(opp_table)) { + dev_err(dev, "failed to set OPP supported HW: %pe\n", opp_table); + return PTR_ERR(opp_table); + } + + /* + * Older device-trees have an empty OPP table, hence we will get + * -ENODEV from devm_pm_opp_of_add_table() for the older DTBs. + * + * The OPP table presence also varies per-device and depending + * on a SoC generation, hence -ENODEV is expected to happen for + * the newer DTs as well. + */ + err = devm_pm_opp_of_add_table(dev); + if (err) { + if (err == -ENODEV) + dev_err_once(dev, "OPP table not found, please update device-tree\n"); + else + dev_err(dev, "failed to add OPP table: %d\n", err); + + return err; + } + + if (params->init_state) { + err = tegra_core_dev_init_opp_state(dev); + if (err) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 98027a76ce3d..e8eab13aa199 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,6 +6,36 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__ +#include +#include + +struct device; + +/** + * Tegra SoC core device OPP table configuration + * + * @init_state: pre-initialize OPP state of a device + */ +struct tegra_core_opp_params { + bool init_state; +}; + +#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params); +#else +static inline bool soc_is_tegra(void) +{ + return false; +} + +static inline int +devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + return -ENODEV; +} +#endif #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Thu Mar 11 23:12:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 398988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B76B4C4332B for ; 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[109.252.193.52]) by smtp.gmail.com with ESMTPSA id j203sm263918wmj.40.2021.03.11.15.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 15:15:25 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default Date: Fri, 12 Mar 2021 02:12:04 +0300 Message-Id: <20210311231208.18180-3-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311231208.18180-1-digetx@gmail.com> References: <20210311231208.18180-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new Kconfig SOC_TEGRA_COMMON option which selects configuration options that are common for all Tegra SoCs. Select PM_OPP by default since from now on OPPs will be used by Tegra drivers which present on all SoC generations, like display controller driver for example. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 976dee036470..bcd61ae59ba3 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA20_VOLTAGE_COUPLER @@ -27,6 +28,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA30_VOLTAGE_COUPLER @@ -40,6 +42,7 @@ config ARCH_TEGRA_114_SOC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -51,6 +54,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -66,6 +70,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help @@ -77,6 +82,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -99,6 +105,7 @@ config ARCH_TEGRA_186_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a @@ -115,6 +122,7 @@ config ARCH_TEGRA_194_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra194 SoC. @@ -125,6 +133,7 @@ config ARCH_TEGRA_234_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra234 SoC. @@ -132,6 +141,10 @@ config ARCH_TEGRA_234_SOC endif endif +config SOC_TEGRA_COMMON + bool + select PM_OPP + config SOC_TEGRA_FUSE def_bool y depends on ARCH_TEGRA From patchwork Thu Mar 11 23:12:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 397731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 073CBC4360C for ; Thu, 11 Mar 2021 23:16:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E6E8F64F9A for ; Thu, 11 Mar 2021 23:16:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231294AbhCKXPf (ORCPT ); Thu, 11 Mar 2021 18:15:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231197AbhCKXP2 (ORCPT ); Thu, 11 Mar 2021 18:15:28 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 411A6C061574; Thu, 11 Mar 2021 15:15:28 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id x13so732997wrs.9; Thu, 11 Mar 2021 15:15:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nZPDfAK/GaZZk1byDwisDbQmbG69Ki4SSVrhCiS1D80=; b=N12BWlr0M5KU//v0sBEXxL7IXPJdEcy4qW1vxeL6ptHTdH37YkEs/0ke8kfjZdv+ye FYklpPTxlvjTVSai4knlL2sMq0250IMnU+9kKNc+067zV6gLrpc8JNwtAy3aWKzG0kpl Da5mJUipQcw2/yHdRB463OldHLFDk3m2ex55WISlzexH6P3DdRuj2Ch2+kNkVEMlNXQd br3Lc+1ueoYua/w4/rpiZZGYohTkhVezl1ZGT7derL2iZT6Z8YPP/BfWujNI+uXNd/UM MeV33Xa8PLLB1vKmp354SGTwaNjq7xFJVnaiA136c8rsiMWWbV5DlrpjPwf7uA2AOLUL 4MJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nZPDfAK/GaZZk1byDwisDbQmbG69Ki4SSVrhCiS1D80=; b=MKcIRObEY1BDCAmVh4JnCBbH4N9wUsEw0kwb6eOuipkYxajyDrEgBVJrtp/dY6pg/B xiu8tGA72UU4W4Y4JbewypYzzZbj7T7+NVVpgKH+YPKzHD+9L1v6QFWGUvzm0DXWj4GF kHbqo8oTyD368eFplVS1h1L7GMrufpUeOYnNyHBtOCAK8SByIQs6x+C/z1WhiiHsmtYg 9q4+QtbOYU5vE/dGq/IyQ62LtjLW8LF/g6+UHTyRKEmeWYU+3dvNuU5fRju79Wjxmy7v 15TKi6/LkPkjn0uIlJJj7ZcViVsJc917s7GGT4kkMppD+/gHS5E82krBpfC65Ck6Jxqc 9/FA== X-Gm-Message-State: AOAM531MNB1OwbjssjvCwGimsDCI4kbS4e165bjHLoj4B4SMzib2b/KO 2rd7y2z+hl+pAaM0zg9WCto= X-Google-Smtp-Source: ABdhPJzbQvhEVffnsKZg3UZPO25ccig+sda6lz+ibiCyMdjzTDC2P4mR/kl00LYpDj2rNc9qziT1lg== X-Received: by 2002:adf:f0c1:: with SMTP id x1mr10826975wro.7.1615504527037; Thu, 11 Mar 2021 15:15:27 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id j203sm263918wmj.40.2021.03.11.15.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 15:15:26 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] dt-bindings: power: tegra: Add binding for core power domain Date: Fri, 12 Mar 2021 02:12:05 +0300 Message-Id: <20210311231208.18180-4-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311231208.18180-1-digetx@gmail.com> References: <20210311231208.18180-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Add binding for the core power domain. Signed-off-by: Dmitry Osipenko --- .../power/nvidia,tegra20-core-domain.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml new file mode 100644 index 000000000000..bc68c5757d45 --- /dev/null +++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Core Power Domain + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +allOf: + - $ref: power-domain.yaml# + +properties: + compatible: + enum: + - nvidia,tegra20-core-domain + - nvidia,tegra30-core-domain + + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + power-supply: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to voltage regulator connected to the SoC Core power rail. + +required: + - compatible + - operating-points-v2 + - "#power-domain-cells" + - power-supply + +additionalProperties: false + +examples: + - | + power-domain { + compatible = "nvidia,tegra20-core-domain"; + operating-points-v2 = <&opp_table>; + power-supply = <®ulator>; + #power-domain-cells = <0>; + }; From patchwork Thu Mar 11 23:12:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 397730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F910C41620 for ; Thu, 11 Mar 2021 23:16:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 232D164FC0 for ; Thu, 11 Mar 2021 23:16:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbhCKXPf (ORCPT ); Thu, 11 Mar 2021 18:15:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231219AbhCKXPa (ORCPT ); Thu, 11 Mar 2021 18:15:30 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C7FDC061574; Thu, 11 Mar 2021 15:15:29 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id d15so3772491wrv.5; Thu, 11 Mar 2021 15:15:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b2w9mpc636QgZcQ3KhN9N6W9L5fmy+Ks+Eg/JPfevSU=; b=iG9PrCdKaD6u9Ne5dcQTX4Wg12IUSOOxp+Lwx7CuQZrxIuoeF6ZXjmanoN9etX4nLV oxi0bQLOzmIUNTiV9jXEtxzL5irm7hzZRt3pLVA8quZM+eDkVhq4dXuS8F5R7/wnEWNt OS89w2xzNWhjgku+GUjLyJdFKK7sffInvAEt25X8Jf+sstU6DYjkQpUaig+sB4ZZGP8J 9cisO47PuHYDKTbNdNWgBKcuNTxYrAcHOwXiMEmjDHg3qbDWAgURARSkG+kwZ7ysbvCW eqp2ArEjEiqzdTsEghvOl6fGNw3wWVE+3pQ6ZanRD1w2bPwDnq8QUW2nwSAkgyrOaCNO Tvsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b2w9mpc636QgZcQ3KhN9N6W9L5fmy+Ks+Eg/JPfevSU=; b=fYrpXmDAebdWq5elnc4bHcWHbypuMsXoZiahxFzeODW/XOJViMIX3SNlEri2wMzsuV I81/NYr/UKT856sWWZ7EC7THOYzfEMr+voS752qgULDp7Np1CXj/6ps0RFdDPr49M5Jq B9FOeZlEUJ09mPHnpiUfK3th2MQGbPiVxFU3Yig1WjoQIoctFwNHPy8cHai5UgAu5pKL vRP4lJivjXUISH73ZUEnae0Y2BirC4UnfU5TzQBpJW+tqkOP5jaMDJt1SFkUUnh2N37Z NwTVIhgEp6hNeGoZReMkbjyuqgb6sb9WChMG3vAub4u3mr8rAxmrWbMkBpWcBH1m7tvq HRuw== X-Gm-Message-State: AOAM530gS1MEc2IE0Lqj7mTZU5+pR23BXJmOeWrmAobmWLQFpi6PxIGR cevU7CLElYLKrg6eb/JAeM8= X-Google-Smtp-Source: ABdhPJwmd3xwn+J7g8zPor95wn0hzMJ6537P2c5KCUVb2hPPpDrluJOEiBOy3BnNWiKrw3CcDwoQHQ== X-Received: by 2002:a5d:63d2:: with SMTP id c18mr10928605wrw.277.1615504528353; Thu, 11 Mar 2021 15:15:28 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id j203sm263918wmj.40.2021.03.11.15.15.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 15:15:28 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] soc/tegra: Introduce core power domain driver Date: Fri, 12 Mar 2021 02:12:06 +0300 Message-Id: <20210311231208.18180-5-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311231208.18180-1-digetx@gmail.com> References: <20210311231208.18180-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org NVIDIA Tegra SoCs have multiple power domains, each domain corresponds to an external SoC power rail. Core power domain covers vast majority of hardware blocks within a Tegra SoC. The voltage of a power domain should be set to a value which satisfies all devices within a power domain. Add driver for the core power domain which manages the voltage state of the domain. This allows us to support a system-wide DVFS on Tegra. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/Kconfig | 6 + drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/core-power-domain.c | 154 ++++++++++++++++++++++++++ include/soc/tegra/common.h | 6 + 4 files changed, 167 insertions(+) create mode 100644 drivers/soc/tegra/core-power-domain.c diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index bcd61ae59ba3..fccbc168dd87 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -16,6 +16,7 @@ config ARCH_TEGRA_2x_SOC select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select SOC_TEGRA_CORE_POWER_DOMAIN select SOC_TEGRA20_VOLTAGE_COUPLER select TEGRA_TIMER help @@ -31,6 +32,7 @@ config ARCH_TEGRA_3x_SOC select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select SOC_TEGRA_CORE_POWER_DOMAIN select SOC_TEGRA30_VOLTAGE_COUPLER select TEGRA_TIMER help @@ -170,3 +172,7 @@ config SOC_TEGRA20_VOLTAGE_COUPLER config SOC_TEGRA30_VOLTAGE_COUPLER bool "Voltage scaling support for Tegra30 SoCs" depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST + +config SOC_TEGRA_CORE_POWER_DOMAIN + bool + select PM_GENERIC_DOMAINS diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index 9c809c1814bd..8f1294f954b4 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o obj-$(CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER) += regulators-tegra30.o +obj-$(CONFIG_SOC_TEGRA_CORE_POWER_DOMAIN) += core-power-domain.o diff --git a/drivers/soc/tegra/core-power-domain.c b/drivers/soc/tegra/core-power-domain.c new file mode 100644 index 000000000000..9099290c1b02 --- /dev/null +++ b/drivers/soc/tegra/core-power-domain.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NVIDIA Tegra SoC Core Power Domain Driver + */ + +#include +#include +#include +#include +#include +#include + +#include + +static struct lock_class_key tegra_core_domain_lock_class; +static bool tegra_core_domain_state_synced; +static DEFINE_MUTEX(tegra_core_lock); + +bool tegra_soc_core_domain_state_synced(void) +{ + return tegra_core_domain_state_synced; +} + +static int tegra_genpd_set_performance_state(struct generic_pm_domain *genpd, + unsigned int level) +{ + struct dev_pm_opp *opp; + int err; + + opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); + if (IS_ERR(opp)) { + dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", + level, opp); + return PTR_ERR(opp); + } + + mutex_lock(&tegra_core_lock); + err = dev_pm_opp_set_opp(&genpd->dev, opp); + mutex_unlock(&tegra_core_lock); + + dev_pm_opp_put(opp); + + if (err) { + dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", + level, err); + return err; + } + + return 0; +} + +static unsigned int +tegra_genpd_opp_to_performance_state(struct generic_pm_domain *genpd, + struct dev_pm_opp *opp) +{ + return dev_pm_opp_get_level(opp); +} + +static int tegra_core_domain_probe(struct platform_device *pdev) +{ + struct generic_pm_domain *genpd; + struct opp_table *opp_table; + const char *rname = "power"; + int err; + + genpd = devm_kzalloc(&pdev->dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = pdev->dev.of_node->name; + genpd->set_performance_state = tegra_genpd_set_performance_state; + genpd->opp_to_performance_state = tegra_genpd_opp_to_performance_state; + + opp_table = devm_pm_opp_set_regulators(&pdev->dev, &rname, 1); + if (IS_ERR(opp_table)) + return dev_err_probe(&pdev->dev, PTR_ERR(opp_table), + "failed to set OPP regulator\n"); + + err = pm_genpd_init(genpd, NULL, false); + if (err) { + dev_err(&pdev->dev, "failed to init genpd: %d\n", err); + return err; + } + + /* + * We have a "PMC -> Core" hierarchy of the power domains where + * PMC needs to resume and change performance (voltage) of the + * Core domain from the PMC GENPD on/off callbacks, hence we need + * to annotate the lock in order to remove confusion from the + * lockdep checker when a nested access happens. + */ + lockdep_set_class(&genpd->mlock, &tegra_core_domain_lock_class); + + err = of_genpd_add_provider_simple(pdev->dev.of_node, genpd); + if (err) { + dev_err(&pdev->dev, "failed to add genpd: %d\n", err); + goto remove_genpd; + } + + return 0; + +remove_genpd: + pm_genpd_remove(genpd); + + return err; +} + +static void tegra_core_domain_set_synced(struct device *dev, bool synced) +{ + int err; + + tegra_core_domain_state_synced = synced; + + mutex_lock(&tegra_core_lock); + err = dev_pm_opp_sync_regulators(dev); + mutex_unlock(&tegra_core_lock); + + if (err) + dev_err(dev, "failed to sync regulators: %d\n", err); +} + +static void tegra_core_domain_sync_state(struct device *dev) +{ + tegra_core_domain_set_synced(dev, true); +} + +static void tegra_core_domain_shutdown(struct platform_device *pdev) +{ + /* + * Ensure that core voltage is at a level suitable for boot-up + * before system is rebooted, which may be important for some + * devices if regulators aren't reset on reboot. This is usually + * the case if PMC soft-reboot is used. + */ + tegra_core_domain_set_synced(&pdev->dev, false); +} + +static const struct of_device_id tegra_core_domain_match[] = { + { .compatible = "nvidia,tegra20-core-domain", }, + { .compatible = "nvidia,tegra30-core-domain", }, + { } +}; + +static struct platform_driver tegra_core_domain_driver = { + .driver = { + .name = "tegra-core-power", + .of_match_table = tegra_core_domain_match, + .suppress_bind_attrs = true, + .sync_state = tegra_core_domain_sync_state, + }, + .probe = tegra_core_domain_probe, + .shutdown = tegra_core_domain_shutdown, +}; +builtin_platform_driver(tegra_core_domain_driver); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index e8eab13aa199..9a4ac3af2401 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -22,6 +22,7 @@ struct tegra_core_opp_params { #ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +bool tegra_soc_core_domain_state_synced(void); int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *params); #else @@ -30,6 +31,11 @@ static inline bool soc_is_tegra(void) return false; } +static inline bool tegra_soc_core_domain_state_synced(void) +{ + return false; +} + static inline int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *params) From patchwork Thu Mar 11 23:12:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 398987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0368CC43603 for ; Thu, 11 Mar 2021 23:16:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D949964FD7 for ; Thu, 11 Mar 2021 23:16:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbhCKXPg (ORCPT ); Thu, 11 Mar 2021 18:15:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbhCKXPb (ORCPT ); Thu, 11 Mar 2021 18:15:31 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBDA9C061574; Thu, 11 Mar 2021 15:15:30 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id j2so3761130wrx.9; Thu, 11 Mar 2021 15:15:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/cs0cNSjfmc/2lc6bUnEBoVh2012qFAEKZG9xKVF14o=; b=M/Z84Nww0TQawWyCb54acxMQofcEEkcoP+oYWhytiFpTcUW3S/bmVrAE7TlIS6ds+m 2ZmhZAwO5hey9UMtKgjPFlD6tl/nhmx3goDjgPuiw7bgAAC/OPUmIj0x70CeHmTSi84V Ee8gFZuP7jBW8B/dbczyNUU2yL2i6ieEVFreGlIPuDVXhFt5UrFdodvgI066tTsmImhF 00wq1D54ZOyPlQpymnOUbmGiO4DpAuRSyNaAtLq1oG+x8E/hXCHNWJBN6saTk259l1yZ i8F+YoHJqYfUHdO8LxIKCbNtbwKExanLUYuwlLLvH/ojPsqfszSukQBUw7EBqPZ+BGSW gzHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/cs0cNSjfmc/2lc6bUnEBoVh2012qFAEKZG9xKVF14o=; b=POlkj0M0IqjIlnDwHA4rXbMyUpi58sgLa3zroV7LqwMs8pAmmf900LhnRbwaxAg3kp MgaGfD3OunSKRFQxL6NQq44NpDnjFPyfRSK+37XiWdKtE2N33P1FrClGhewrmrGstlTG 6jDRxbgHTHAjbvZml6HZlDlqEn3NskPpW2+fZDFo1dfSkhpaw/L2GI4llCzDfhsZ5Nwg z0hXVQjmsva4Wqyv4VDOUUvtg5TETrQoQGOh5WvfWK5u+QXIip2oAX8tItKqXe1Jyojl IPARGu6pjx+nVBI8jsCNY3+R4HBukn1vzC8rM+065q+duAROZ3/QCMYzTmqnbdtfTa4D sBWQ== X-Gm-Message-State: AOAM5338Bpdwg3x3r71NbnMlEvDFeYCefXX0bgCVa9bREDRYfyXQ/rHN 4rOafWQ7id2CBhvFsVmI/Ecmjfh3p24= X-Google-Smtp-Source: ABdhPJwqhHjaNF60uJGOenxW5a5MwPDquiEd1b/c1WdZ6vqabTRkjAF+OkpaLTun8PG9HkYmIBiaHA== X-Received: by 2002:a5d:4341:: with SMTP id u1mr11187812wrr.88.1615504529619; Thu, 11 Mar 2021 15:15:29 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id j203sm263918wmj.40.2021.03.11.15.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 15:15:29 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] soc/tegra: regulators: Support Core domain state syncing Date: Fri, 12 Mar 2021 02:12:07 +0300 Message-Id: <20210311231208.18180-6-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311231208.18180-1-digetx@gmail.com> References: <20210311231208.18180-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The core voltage shall not drop until state of Core domain is synced, i.e. all device drivers that use Core domain are loaded and ready. Support Core domain state syncing. The Core domain driver invokes the core-regulator voltage syncing once the state of domain is synced, at this point the Core voltage is allowed to go lower than the level left after bootloader. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 367a71a3cd10..e2c11d442591 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -16,6 +16,8 @@ #include #include +#include + struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; @@ -38,6 +40,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra20 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -58,7 +75,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; } diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 0e776b20f625..42d675b79fa3 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -16,6 +16,7 @@ #include #include +#include #include struct tegra_regulator_coupler { @@ -39,6 +40,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra30 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -59,7 +75,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; } From patchwork Thu Mar 11 23:12:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 398986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AB85C4160E for ; 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[109.252.193.52]) by smtp.gmail.com with ESMTPSA id j203sm263918wmj.40.2021.03.11.15.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 15:15:30 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] soc/tegra: pmc: Link children power domains to the parent domain Date: Fri, 12 Mar 2021 02:12:08 +0300 Message-Id: <20210311231208.18180-7-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210311231208.18180-1-digetx@gmail.com> References: <20210311231208.18180-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Core domain is a parent of PMC power domains, hence PMC domains should be set up as a sub-domains of the parent (Core) domain if "power-domains" phandle presents in a device-tree node of PMC domain. This allows to propagate GENPD performance changes to the parent Core domain if performance change is applied to a PMC domain. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 84ab27d85d92..ba8407819397 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1283,6 +1283,7 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) static int tegra_powergate_init(struct tegra_pmc *pmc, struct device_node *parent) { + struct of_phandle_args child_args, parent_args; struct device_node *np, *child; int err = 0; @@ -1296,6 +1297,21 @@ static int tegra_powergate_init(struct tegra_pmc *pmc, of_node_put(child); break; } + + if (of_parse_phandle_with_args(child, "power-domains", + "#power-domain-cells", + 0, &parent_args)) + continue; + + child_args.np = child; + child_args.args_count = 0; + + err = of_genpd_add_subdomain(&parent_args, &child_args); + of_node_put(parent_args.np); + if (err) { + of_node_put(child); + break; + } } of_node_put(np);