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[82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:21 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_PORTAY?= , Rob Herring , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , linux-pm@vger.kernel.org (open list:DEVICE FREQUENCY (DEVFREQ)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 1/4] dt-bindings: devfreq: rk3399_dmc: Add rockchip, pmu phandle. Date: Tue, 9 Mar 2021 00:38:55 +0100 Message-Id: <20210308233858.24741-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Enric Balletbo i Serra The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU general register files to know the DRAM type, so add a phandle to the syscon that manages these registers. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Gaël PORTAY Acked-by: MyungJoo Ham Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index a10d1f6d85c6..a41bcfef95c8 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -12,6 +12,8 @@ Required properties: for details. - center-supply: DMC supply node. - status: Marks the node enabled/disabled. +- rockchip,pmu: Phandle to the syscon managing the "PMU general register + files". Optional properties: - interrupts: The CPU interrupt number. The interrupt specifier From patchwork Mon Mar 8 23:38:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 395515 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2130644jai; Mon, 8 Mar 2021 15:40:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJzNW2pTj9Lp2zrrKJSH4jI4iTXm9T2kUZnYSABcu+CgLwleZPbyFXKf4w8ksqwL8Nr04H7w X-Received: by 2002:a17:907:10ce:: with SMTP id rv14mr17646656ejb.56.1615246854586; Mon, 08 Mar 2021 15:40:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615246854; cv=none; d=google.com; s=arc-20160816; b=m6crxqei2b8cE7zO2+UNTRvpgeLShRLTbxMY+0tcbG7s2aLXkRccMKiLb/FJjpFq3r +X63wAs5Xa2jqgG8d0kBPM+DD1Npq3NzGD99Dw8+b1VgGYMJYQpb/fs9G+jf9de4+D2A eBXoKoUhIZCiu0K9mi9/MGH0JMZFaBO7mGJpjIfTj4t2dxVWXJq/eGJAm//Dvgdb7p1C PnGWqqR/wG7+DuvEsrfxahOW8y5YvzPxAolU3A87cHXKFtfFea2KOC4EYJf1RYmt2q5Y fHfksXbA7DRF7lvrn9z6GXI4jhszsGeFaFaYdBmHbuYH5iacFh/7AwQG3mrOBUsV1IMP PsSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cNI4lb320b0g3N9E/pXmEbLu1U21wMPwIZ392wgv3s0=; b=j3qrbUvKYm4qhsVfGA7+r2eHiCBZd8GJrnxQ7vx4ifK9oPj6tmy77aN+5OzdxdXcnA YT6axzdqkvIlpZXQauHuOyACuQ6HvHwCRRA3MEq3b/ks2bKiHu1j+tR6L7QVFAEzYinc W07G+Ei8XtHDBFc0VPV9KvGAqyzWoQb6Izk6pgr0KDNpxJzc4mGDGKQnoZl7P/fRKPPF 4wUSFQbTOCvn1UQiALAUBuquXFURwhgp7BRgLcTfhPHYJkaFvkiQnIcQfGcjStf38EI/ /qxAXgL0Gqgpswu86RAZPwFbvHmF18OAEImgdigFMyAGifhT6PT7lCPnkF5ed0HajzNi /Lgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YcPsI338; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:24 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Lin Huang , Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_PORTAY?= , Rob Herring , Johan Jonker , Helen Koike , Chen-Yu Tsai , Jacob Chen , Shunqian Zheng , Robin Murphy , Boris Brezillon , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 2/4] arm64: dts: rk3399: Add dfi and dmc nodes. Date: Tue, 9 Mar 2021 00:38:56 +0100 Message-Id: <20210308233858.24741-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308233858.24741-1-daniel.lezcano@linaro.org> References: <20210308233858.24741-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lin Huang These are required to support DDR DVFS on rk3399 platform. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index edbbf35fe19e..6f23d99236fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1937,6 +1937,25 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = ; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; From patchwork Mon Mar 8 23:38:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 395517 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2131083jai; Mon, 8 Mar 2021 15:41:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJz2gUsmlwbCjqCZb5tzEBIgmnfHIC8YYtQd4UtUnFWfZcbkkNzeVY7oBay2nzxdSQ3GT7mJ X-Received: by 2002:a50:9d0b:: with SMTP id v11mr1022687ede.308.1615246904088; Mon, 08 Mar 2021 15:41:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615246904; cv=none; d=google.com; s=arc-20160816; b=YJdZyoY7HiQ6Zmh5GO2pGLRrMNZb8d8lxxnGK/dgU4pi3NJC65k/MvnLUSB65PgwUG J0EX9FOJv0Q6ahRb0iJXMFp0y1AzQB/unRL8PUa+SyWKGhSwhaZC1bdYrj5K0LaAS8Qc EupD+xDjaXVj8wmks4Pwea+P2a9ctJ37FMQTVwylj9hhTeDIVlZ7q0bnHR40CkF6QUOB n1ux/8QFCE8whW2r/yv9o7b5NbHwAAStMhlGnhZoMuncaDVQiFnwsB/wuN4J0p4ROxsr HfvF5JL0Biy5USBNUdg7qoh4gsf6bnhDrSWV0hAFYFhyGEVlNJ2WUe9L18m9kfKSZsyz ut5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uZSiFVg2/jE/hYgherndxXMvyjYS/mnvO0aiBAtVcTY=; b=pHgACNS2IeFBm1EjTt8KtQKI9tpabB78gwjSgYVyFq4kJWh+jvkgAPedDTlBQZsYS1 THdVLm5r+3o5vFnRkBh802PY3NIr0QOeVsH4pIxpOTpDFxHnLjwsUxJCmImzKx//xihf cmTc8betrRjzMFcYn8+CTqVeOxro76fddYUeSxSh+91krOmagE52ICDbwmRcE3QBEXPh u2nbiMaGdCjDtXV1PMJeyysxzSCoHtMMIUJJu8GdT3KlJYejn0gnmgAxa9180Gn++n8Z +yf+05h3vyhBS9fZmi5V8qtfSXEi+MKHYIdlNTTg4eXiBsTGuJyFUsKHbWwI8cuHlzlh I25Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8IUb56a; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:32 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Lin Huang , Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_PORTAY?= , Rob Herring , Johan Jonker , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 3/4] arm64: dts: rockchip: Enable dmc and dfi nodes on gru. Date: Tue, 9 Mar 2021 00:38:57 +0100 Message-Id: <20210308233858.24741-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308233858.24741-1-daniel.lezcano@linaro.org> References: <20210308233858.24741-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lin Huang Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano --- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 4 ++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 45 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 29 ++++++++++++ 3 files changed, 78 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 1384dabbdf40..d32b015ad2cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -398,3 +398,7 @@ ap_i2c_tp: &i2c5 { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + +&dmc { + center-supply = <&ppvar_centerlogic>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 32dcaf210085..fc3dc9a4b43c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -289,6 +289,12 @@ status = "okay"; }; +&dmc_opp_table { + opp04 { + opp-suspend; + }; +}; + /* * Set some suspend operating points to avoid OVP in suspend * @@ -489,6 +495,45 @@ ap_i2c_audio: &i2c8 { status = "okay"; }; +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + upthreshold = <25>; + downdifferential = <15>; + rockchip,ddr3_speed_bin = <21>; + rockchip,pd_idle = <0x40>; + rockchip,sr_idle = <0x2>; + rockchip,sr_mc_gate_idle = <0x3>; + rockchip,srpd_lite_idle = <0x4>; + rockchip,standby_idle = <0x2000>; + rockchip,dram_dll_dis_freq = <300000000>; + rockchip,phy_dll_dis_freq = <125000000>; + rockchip,auto_pd_dis_freq = <666000000>; + rockchip,ddr3_odt_dis_freq = <333000000>; + rockchip,ddr3_drv = <40>; + rockchip,ddr3_odt = <120>; + rockchip,phy_ddr3_ca_drv = <40>; + rockchip,phy_ddr3_dq_drv = <40>; + rockchip,phy_ddr3_odt = <240>; + rockchip,lpddr3_odt_dis_freq = <333000000>; + rockchip,lpddr3_drv = <34>; + rockchip,lpddr3_odt = <240>; + rockchip,phy_lpddr3_ca_drv = <40>; + rockchip,phy_lpddr3_dq_drv = <40>; + rockchip,phy_lpddr3_odt = <240>; + rockchip,lpddr4_odt_dis_freq = <333000000>; + rockchip,lpddr4_drv = <60>; + rockchip,lpddr4_dq_odt = <40>; + rockchip,lpddr4_ca_odt = <40>; + rockchip,phy_lpddr4_ca_drv = <40>; + rockchip,phy_lpddr4_ck_cs_drv = <80>; + rockchip,phy_lpddr4_dq_drv = <80>; + rockchip,phy_lpddr4_odt = <60>; +}; + &sdhci { /* * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index 69cc9b05baa5..c9e7032b01a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,31 @@ opp-microvolt = <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + }; + }; }; &cpu_l0 { @@ -139,3 +164,7 @@ &gpu { operating-points-v2 = <&gpu_opp_table>; }; + +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; From patchwork Mon Mar 8 23:38:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 395516 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2130697jai; Mon, 8 Mar 2021 15:40:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJyL68bRUlm8sYCPaqplZJJjsFvg6lVuFSM9vOg9oGPRagGwixpcb6xaheUTfrFB6FziAcJ4 X-Received: by 2002:a17:906:358c:: with SMTP id o12mr17917578ejb.156.1615246858914; Mon, 08 Mar 2021 15:40:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615246858; cv=none; d=google.com; s=arc-20160816; b=q3Z2StnIWzJO3CqyUTzi0wb0q/6pVb+1Fbl0YJFVDygwfcmMOQs6TbusDCYGdW+2Cr FySykjA7MiL6KP/c1GFwq5KVB6QO81DxSCKFDJHj2GdkDWOtCjzmYACC2R3wrEKJZOIC i59PLNgH6TGOE67DIdI1zlsdrdOzMWTQd0ct7tvaUF2PNjf9BYmKN16Q/3svgmybSmx6 mIqx+BICCdGhpC16c+Lw7hgNW20alRkDmuLyp8DXuBh7ZDw9/qMdMj2TqO9qCVcbnvpu ibo7b9XGnTNan0yeiOVwWt+/Tgcz56CxVsD/whYwaZLlZiBwaeqBD/+yVu0ctWunW+Ry VczA== ARC-Message-Signature: i=1; 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[82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:33 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, =?utf-8?q?Ga=C3=ABl_PORTAY?= , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , linux-pm@vger.kernel.org (open list:DEVICE FREQUENCY (DEVFREQ)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 4/4] dt-bindings: devfreq: rk3399_dmc: Remove references of unexistant defines Date: Tue, 9 Mar 2021 00:38:58 +0100 Message-Id: <20210308233858.24741-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308233858.24741-1-daniel.lezcano@linaro.org> References: <20210308233858.24741-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Gaël PORTAY Those DDR related defines do not exist. Replace their references with their numerical constant. Signed-off-by: Gaël PORTAY Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../bindings/devfreq/rk3399_dmc.txt | 73 +++++++++---------- 1 file changed, 34 insertions(+), 39 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index a41bcfef95c8..ddde2c4f97df 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -79,24 +79,23 @@ Following properties relate to DDR timing: - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines the DRAM side driver strength in ohms. Default - value is DDR3_DS_40ohm. + value is 40. - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value - is DDR3_ODT_120ohm. + is 120. - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines the phy side CA line (incluing command line, address line and clock line) driver strength. - Default value is PHY_DRV_ODT_40. + Default value is 40. - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is PHY_DRV_ODT_40. + driver strength. Default value is 40. - rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines - the PHY side ODT strength. Default value is - PHY_DRV_ODT_240. + the PHY side ODT strength. Default value is 240. - rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines then ODT disable frequency in MHz (Mega Hz). @@ -106,25 +105,23 @@ Following properties relate to DDR timing: - rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines the DRAM side driver strength in ohms. Default - value is LP3_DS_34ohm. + value is 34. - rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT strength in ohms. Default value - is LP3_ODT_240ohm. + is 240. - rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines the PHY side CA line (including command line, address line and clock line) driver strength. - Default value is PHY_DRV_ODT_40. + Default value is 40. - rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is - PHY_DRV_ODT_40. + driver strength. Default value is 40. - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define - the phy side odt strength, default value is - PHY_DRV_ODT_240. + the phy side odt strength, default value is 240. - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter defines the ODT disable frequency in @@ -134,32 +131,30 @@ Following properties relate to DDR timing: - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines the DRAM side driver strength in ohms. Default - value is LP4_PDDS_60ohm. + value is 60. - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on DQS/DQ line strength in ohms. - Default value is LP4_DQ_ODT_40ohm. + Default value is 40. - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on CA line strength in ohms. - Default value is LP4_CA_ODT_40ohm. + Default value is 40. - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines the PHY side CA line (including command address - line) driver strength. Default value is - PHY_DRV_ODT_40. + line) driver strength. Default value is 40. - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines the PHY side clock line and CS line driver - strength. Default value is PHY_DRV_ODT_80. + strength. Default value is 80. - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is PHY_DRV_ODT_80. + driver strength. Default value is 80. - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines - the PHY side ODT strength. Default value is - PHY_DRV_ODT_60. + the PHY side ODT strength. Default value is 60. Example: dmc_opp_table: dmc_opp_table { @@ -195,23 +190,23 @@ Example: rockchip,phy_dll_dis_freq = <125>; rockchip,auto_pd_dis_freq = <666>; rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = ; - rockchip,ddr3_odt = ; - rockchip,phy_ddr3_ca_drv = ; - rockchip,phy_ddr3_dq_drv = ; - rockchip,phy_ddr3_odt = ; + rockchip,ddr3_drv = <40>; + rockchip,ddr3_odt = <120>; + rockchip,phy_ddr3_ca_drv = <40>; + rockchip,phy_ddr3_dq_drv = <40>; + rockchip,phy_ddr3_odt = <240>; rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = ; - rockchip,lpddr3_odt = ; - rockchip,phy_lpddr3_ca_drv = ; - rockchip,phy_lpddr3_dq_drv = ; - rockchip,phy_lpddr3_odt = ; + rockchip,lpddr3_drv = <34>; + rockchip,lpddr3_odt = <240>; + rockchip,phy_lpddr3_ca_drv = <40>; + rockchip,phy_lpddr3_dq_drv = <40>; + rockchip,phy_lpddr3_odt = <240>; rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = ; - rockchip,lpddr4_dq_odt = ; - rockchip,lpddr4_ca_odt = ; - rockchip,phy_lpddr4_ca_drv = ; - rockchip,phy_lpddr4_ck_cs_drv = ; - rockchip,phy_lpddr4_dq_drv = ; - rockchip,phy_lpddr4_odt = ; + rockchip,lpddr4_drv = <60>; + rockchip,lpddr4_dq_odt = <40>; + rockchip,lpddr4_ca_odt = <40>; + rockchip,phy_lpddr4_ca_drv = <40>; + rockchip,phy_lpddr4_ck_cs_drv = <80>; + rockchip,phy_lpddr4_dq_drv = <80>; + rockchip,phy_lpddr4_odt = <60>; };