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[23.128.96.18]) by mx.google.com with ESMTP id i11si7131983edb.325.2021.03.07.21.46.07; Sun, 07 Mar 2021 21:46:08 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lztQgfYo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234612AbhCHFp1 (ORCPT + 6 others); Mon, 8 Mar 2021 00:45:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234611AbhCHFpG (ORCPT ); Mon, 8 Mar 2021 00:45:06 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8A33C06174A for ; Sun, 7 Mar 2021 21:45:06 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id w7so839876pll.8 for ; Sun, 07 Mar 2021 21:45:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M2CEXbNlNorHIt0/KQNWcmF9T/2OkYKo0K/LHRqivCU=; b=lztQgfYorT9TT3sWSs9ILIwSY8945RaSt1tzpos1IF0092b0/OPzvAQKMnD1KhUbgL Xg31B3JFQbvZkGiHfoRWUw0rzn2Gx/m8r8PfMhLOQQ0+Uw5cw3qMzQJnmvchdmh1rBBH VopVpFLi/csbJnZ2L+Abk3YkNoQ7sUhSa8ZmPtq+iRTrHhszohdYIbAEBX7/Q3L3AtrV aM9aQj0dzg0/KK30X5Ca73gG6C1yYZjzdemgGElEgqAtGQgxEJzuTFEmu6Fkhr14RX6Q vknQjzP/kcQFBOsdZVz3Lc+qeLDBvjltcPuILo1Rwi1l0oiXKZ+6nkgQJYXujxMHAUqI Ofyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M2CEXbNlNorHIt0/KQNWcmF9T/2OkYKo0K/LHRqivCU=; b=kUnxmXFBESCiEAs3c/a7nG5dk2aOOAj/Gycu2vo0ILxCdAQ+jlCiWjzD3X4r4T8BBf PVNPAu8F8d/fkl7bViMvtUGYcabF21pQAthjl4J+q/RtUVVzkBe90yGh6Q2FQI2YKAN4 PidxtpCC2m74upUymspX4uXvA/KhUpLKGpD+mn7lHeC2iFj+L9ZpkVSG0k09DJJwaJ+p Ic3CoDA8nlK4B3p/Z4B0SVJgDwJE6xz1AhC9LYCIXjtOekTUQ7xyZGajUUaDPVAH+OxB MoVWOylpjPHZ8tqLj3gasNAbvTvJar+DzconQbjNf3pTr9TzEh1v04J5EgkK9ZV7hXye /eww== X-Gm-Message-State: AOAM53324G08E/m9imtESlje2QTfkYjmJCuRg68z+eVcW5DAUe4d5zNx 6N7lSmLarVlxSYTnbsEg7T4t X-Received: by 2002:a17:902:6845:b029:e4:4d0f:c207 with SMTP id f5-20020a1709026845b02900e44d0fc207mr19446669pln.36.1615182306319; Sun, 07 Mar 2021 21:45:06 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6e84:fef9:1070:d306:6d0e:bf6b]) by smtp.gmail.com with ESMTPSA id y29sm4331506pfp.206.2021.03.07.21.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Mar 2021 21:45:05 -0800 (PST) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v4 1/3] dt-bindings: mtd: Convert Qcom NANDc binding to YAML Date: Mon, 8 Mar 2021 11:14:45 +0530 Message-Id: <20210308054447.28418-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210308054447.28418-1-manivannan.sadhasivam@linaro.org> References: <20210308054447.28418-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Qcom NANDc devicetree binding to YAML. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++++++++++++++++++ .../devicetree/bindings/mtd/qcom_nandc.txt | 142 ------------- 2 files changed, 196 insertions(+), 142 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/qcom,nandc.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt -- 2.25.1 diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml new file mode 100644 index 000000000000..84ad7ff30121 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm NAND controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + enum: + - qcom,ipq806x-nand + - qcom,ipq4019-nand + - qcom,ipq6018-nand + - qcom,ipq8074-nand + - qcom,sdx55-nand + + reg: + maxItems: 1 + + clocks: + items: + - description: Core Clock + - description: Always ON Clock + + clock-names: + items: + - const: core + - const: aon + + "#address-cells": true + "#size-cells": true + +patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-bus-width: + const: 8 + + nand-ecc-strength: + enum: [1, 4, 8] + + nand-ecc-step-size: + enum: + - 512 + +allOf: + - $ref: "nand-controller.yaml#" + + - if: + properties: + compatible: + contains: + const: qcom,ipq806x-nand + then: + properties: + dmas: + items: + - description: rxtx DMA channel + + dma-names: + items: + - const: rxtx + + qcom,cmd-crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain the ADM command type CRCI block instance number + specified for the NAND controller on the given platform + + qcom,data-crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain the ADM data type CRCI block instance number + specified for the NAND controller on the given platform + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-nand + - qcom,ipq6018-nand + - qcom,ipq8074-nand + - qcom,sdx55-nand + + then: + properties: + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot-nand"; + reg = <0 0x58a0000>; + }; + + partition@58a0000 { + label = "fs-nand"; + reg = <0x58a0000 0x4000000>; + }; + }; + }; + }; + + #include + nand-controller@79b0000 { + compatible = "qcom,ipq4019-nand"; + reg = <0x79b0000 0x1000>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpicbam 0>, + <&qpicbam 1>, + <&qpicbam 2>; + dma-names = "tx", "rx", "cmd"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot-nand"; + reg = <0 0x58a0000>; + }; + + partition@58a0000 { + label = "fs-nand"; + reg = <0x58a0000 0x4000000>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt deleted file mode 100644 index 5647913d8837..000000000000 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ /dev/null @@ -1,142 +0,0 @@ -* Qualcomm NAND controller - -Required properties: -- compatible: must be one of the following: - * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x - SoC and it uses ADM DMA - * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in - IPQ4019 SoC and it uses BAM DMA - * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in - IPQ6018 SoC and it uses BAM DMA - * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in - IPQ8074 SoC and it uses BAM DMA - * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in - SDX55 SoC and it uses BAM DMA - -- reg: MMIO address range -- clocks: must contain core clock and always on clock -- clock-names: must contain "core" for the core clock and "aon" for the - always on clock - -EBI2 specific properties: -- dmas: DMA specifier, consisting of a phandle to the ADM DMA - controller node and the channel number to be used for - NAND. Refer to dma.txt and qcom_adm.txt for more details -- dma-names: must be "rxtx" -- qcom,cmd-crci: must contain the ADM command type CRCI block instance - number specified for the NAND controller on the given - platform -- qcom,data-crci: must contain the ADM data type CRCI block instance - number specified for the NAND controller on the given - platform - -QPIC specific properties: -- dmas: DMA specifier, consisting of a phandle to the BAM DMA - and the channel number to be used for NAND. Refer to - dma.txt, qcom_bam_dma.txt for more details -- dma-names: must contain all 3 channel names : "tx", "rx", "cmd" -- #address-cells: <1> - subnodes give the chip-select number -- #size-cells: <0> - -* NAND chip-select - -Each controller may contain one or more subnodes to represent enabled -chip-selects which (may) contain NAND flash chips. Their properties are as -follows. - -Required properties: -- reg: a single integer representing the chip-select - number (e.g., 0, 1, 2, etc.) -- #address-cells: see partition.txt -- #size-cells: see partition.txt - -Optional properties: -- nand-bus-width: see nand-controller.yaml -- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will - be used according to chip requirement and available - OOB size. - -Each nandcs device node may optionally contain a 'partitions' sub-node, which -further contains sub-nodes describing the flash partition mapping. See -partition.txt for more detail. - -Example: - -nand-controller@1ac00000 { - compatible = "qcom,ipq806x-nand"; - reg = <0x1ac00000 0x800>; - - clocks = <&gcc EBI2_CLK>, - <&gcc EBI2_AON_CLK>; - clock-names = "core", "aon"; - - dmas = <&adm_dma 3>; - dma-names = "rxtx"; - qcom,cmd-crci = <15>; - qcom,data-crci = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot-nand"; - reg = <0 0x58a0000>; - }; - - partition@58a0000 { - label = "fs-nand"; - reg = <0x58a0000 0x4000000>; - }; - }; - }; -}; - -nand-controller@79b0000 { - compatible = "qcom,ipq4019-nand"; - reg = <0x79b0000 0x1000>; - - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpicbam 0>, - <&qpicbam 1>, - <&qpicbam 2>; - dma-names = "tx", "rx", "cmd"; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot-nand"; - reg = <0 0x58a0000>; - }; - - partition@58a0000 { - label = "fs-nand"; - reg = <0x58a0000 0x4000000>; - }; - }; - }; -}; From patchwork Mon Mar 8 05:44:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 395344 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1439066jai; Sun, 7 Mar 2021 21:46:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJxOmAkpTxgAL0pfRhCm590EcRJDSBzJRzU5tnWxvitStSkz4xuJDFJPhOR67SkR28laV0HV X-Received: by 2002:aa7:d44a:: with SMTP id q10mr20145437edr.278.1615182366398; Sun, 07 Mar 2021 21:46:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615182366; cv=none; d=google.com; s=arc-20160816; b=AW5MWcOtH7x8cFCCO8pa9h4jdjz5nff6qK0CJEClnIy7LOjNDEnBAqSNcrpghUKdEM 5XFGTitFlqd9nMf8OWXUlRS6AmOP6FiBg7y+fCgPil/M4xG0GzImh+heNxXJ4VvJgbJ0 b/S53lx3u88lKLECcZMwnSSq7elclrJT49Dw4Jy3kLmvw6mm0nuW9LqS/sVX/PSY6wm1 JCbAE+BDcwqen86/YhUcE6PvQSkfXHBs7Km0AXBe5ipAs8x5z9CIY80rpWR/pu2X8vno 3aAqodVMogutVRTUKnVtibc5jgiO+Qjw5d6j0EiuRDMx7WUoGQzW47FGrh5oimoka7Ie 2hAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0vZpb9y8MutMaka6YLswZQUFtbMSrJ0Y46Hxti/8tHM=; b=PRZOK8TB2YaeSbdOzk6iizTjKdGHiXAPNFk7acQRh4pVQ8+30OpXwV2apuZ2grNKBx aAXsj5RPQ5cMqJ3l95gCBEoYiFCUNb4Ox0NmijMrE7HZzzQHHpvzrsRRoppxhFR0NAfC HihBVeMNp0Qrnzl/uyIQFZUQNmTom7WNFHI0izvotW9BUKzV8/c6Qf6/AJyq375xY1YW pVhy8Kri0trLs5wKeGPPIyAJrGSzZiOvkwNcerw5Qk0VCg5Hyt9HFFQEYYyjEOOQSdnH TsEZ+q6Yr0pOaHRwpQ83hsdIzDmTLbcOjjRcfMEeEoTZivTy3w7xer3oPYFQX4DPrADS RLkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="BJ/nj+3l"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i11si7131983edb.325.2021.03.07.21.46.06; Sun, 07 Mar 2021 21:46:06 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="BJ/nj+3l"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234626AbhCHFp1 (ORCPT + 6 others); Mon, 8 Mar 2021 00:45:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234613AbhCHFpO (ORCPT ); Mon, 8 Mar 2021 00:45:14 -0500 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AC3DC06174A for ; Sun, 7 Mar 2021 21:45:14 -0800 (PST) Received: by mail-pf1-x434.google.com with SMTP id x7so3000663pfi.7 for ; Sun, 07 Mar 2021 21:45:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0vZpb9y8MutMaka6YLswZQUFtbMSrJ0Y46Hxti/8tHM=; b=BJ/nj+3l8mDnLcnBxLlfarOq64qe5GCTAGyv452RcjzDzQpB4tYWS6+XYTFp1wDjLg iekeoQ8giTKMDsFCXfSNVD0QgoGyu/K42d7mJXVvz2aZnWHm/gNU14zW/Y3R7m5YsN3h fd7WoXMP/NspTSfDlYrON5Hdlbrys7rnjkhYIunH2u2usjqGZ3LVdW0ymxcqrvobyp93 UvbWKUzzalTAkVeIqkca95kXND+bReJeQoPRoLuOgzOD2pqaupg7xO76WXBfkXBWfOsj LEIpVyb42vMZL1lLkvnY0ikFcr64g4HTqfIZseiRA1pZfYXuyiUcX6jbIpEDNbTM5rL6 NjSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0vZpb9y8MutMaka6YLswZQUFtbMSrJ0Y46Hxti/8tHM=; b=hIhPaoNuh0r3jHgitHuH8xWeT/O5Iq38f6zxWfvnFFbBcqod2wZVW93BaGeW6iquON m6X4R+y9zaOOCzrHmHWhoXv9wwXDLm90Htwapy5+fC7uYClt0W6KptVyR+xnv8Yx3ZWu +F4d0WdWQlJo9dogbc3mBozBV3Ud0LEBwDSbQqpmJS/QPTCmaUnrjKRj7eCdHpkwFkH2 0qpXGZ5guPLPmusHmYwQJNrkrYBM1J292Cu3o3UqYUAmuwelGIoA4GxMU2Y3UN4u5rkX lKKQfewjbUMpB5dS6JmRYHbKanjD5vxm/cl5vvMDICsEs4e4Jan44GHlY/fhV5Dn1nkr 0O4g== X-Gm-Message-State: AOAM533bdEghLEWHueEsGNPZseyfkguGc2OwN/0nmtYJz1bi/LtwmMrP 1iNSkLicTA+5xfHqeNqfVE+G X-Received: by 2002:a05:6a00:1493:b029:1ef:a5e:ae7 with SMTP id v19-20020a056a001493b02901ef0a5e0ae7mr20047950pfu.61.1615182313824; Sun, 07 Mar 2021 21:45:13 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6e84:fef9:1070:d306:6d0e:bf6b]) by smtp.gmail.com with ESMTPSA id y29sm4331506pfp.206.2021.03.07.21.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Mar 2021 21:45:13 -0800 (PST) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 2/3] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Date: Mon, 8 Mar 2021 11:14:46 +0530 Message-Id: <20210308054447.28418-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210308054447.28418-1-manivannan.sadhasivam@linaro.org> References: <20210308054447.28418-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). So let's add a property for declaring such secure regions so that the drivers can skip touching them. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index d0e422f4b3e0..15a674bedca3 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -143,6 +143,13 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. + secure-regions: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Regions in the NAND chip which are protected using a secure element + like Trustzone. This property contains the start address and size of + the secure regions present. + required: - reg From patchwork Mon Mar 8 05:44:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 395343 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp1439060jai; Sun, 7 Mar 2021 21:46:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJydlCerYL86CcgY1vjyxxinVTAO8xXgWozXAgCMR30E75ILGMmh6L/zXrF+QEOsK6sDHf8n X-Received: by 2002:a17:906:33d9:: with SMTP id w25mr14011718eja.413.1615182366051; Sun, 07 Mar 2021 21:46:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615182366; cv=none; d=google.com; s=arc-20160816; b=de0NwJgXG7ys/jcpxi0ati+Fd0OeFqmfK6hkIYgnXegi9D1o6BKs+23iUoKb+yOweZ 49vuNG+PUnurhQvQu8zf9AUwfQQlIc14hF1qkkSC/S7TRGtx+KyOvDAoFX0GA81k/6Er 2vtK+UW9Or0UAWCpHtZgZipqLKVITQVEKQl1LzcGXrCcQivhFjVXWcP8Ot++s6VFcP+X sIm92CWi5/YS6pkd/PRCYgTMGymbxKHRFbc+fahRcy+UWspM6ENVBzKPWmiuq6WL9o5i GhUsub+9lbN8sN62NS39n7eV4/fR6UZg4lAhwWn1+QjPaVTZel6PICpL1hZq1m0atG+t 3QYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CKfXA4DMfTR++O8eVm8Qy2CjPVyIzCtorOINkgAd8zQ=; b=k0KdDXiUygjit30s4DodEJz1wMPME05GU04N/njjfcyfNEdLVHasq8oEFUg4LLhRq6 bRfOmirLMSg8t6iLLjJhIGtD2ZFQJnUp3e2/XZaVw70dcj0EsLubofRNWMM4QuEF9fN3 d+UUE68s75PLOJzznqbMeC0Yo5NX/WwqkxW7SI7cuu9xmd3XFW5ACiNnrZZyOl/DNT86 hAd/Z/GVwN+k5gmftHeI8MTJGqaNh/klYjrqgZJPPsMeCGnczXefake4ZI4gbvXL+R5q 0lBiVFI41UAlK/OEOgvmyCMvDcGdBAjJbCHPhAd1zF6gylYoZA9GiVNVH+G1yQJG8yQp KuhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qtNe7skT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i11si7131983edb.325.2021.03.07.21.46.05; Sun, 07 Mar 2021 21:46:06 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qtNe7skT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234627AbhCHFp2 (ORCPT + 6 others); Mon, 8 Mar 2021 00:45:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234618AbhCHFpW (ORCPT ); Mon, 8 Mar 2021 00:45:22 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 524B8C06175F for ; Sun, 7 Mar 2021 21:45:22 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id t9so2399287pjl.5 for ; Sun, 07 Mar 2021 21:45:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CKfXA4DMfTR++O8eVm8Qy2CjPVyIzCtorOINkgAd8zQ=; b=qtNe7skTOZCl/HAWrplXkqfCuqoipUM1zBUhn4J/ju39z6M6o54BBdrFrTcPoxbEvA igtfJ+H7kRENdIl2PreWOajeae1i4hM+5V6x17GxWusJiF+BeNTvAz3IfyW7ilSYh80b T5gvWfKUg7rP165PPG8pLoMQZVUvqInHM+2grfzxdLiJ8K+6Mp/hHI1WWBb3Lmr+FWPC 3t3vWcu7oJGuB/OrWi6k9NY98zKyKmocleVWFY3dlKN879/xrHgWQE0pdAftCZpmYPIn Wg8QLJLWvRmAhGKgQMDmk1dllSGBY7y84uaOux3/6jZAOknJUFGSju9L4jR0U4zBJyzF nfQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CKfXA4DMfTR++O8eVm8Qy2CjPVyIzCtorOINkgAd8zQ=; b=XYgopGJUBAkLUQ9GtyEpwa0gR7XPnSFBmqAp5V8Tt3w4ICTzbXiPYE37ewIaxn+dxU o3jfC1vIZe9kUT/vXlX0dzJmyl65Dc2K4u3B8lWan18fFBvyFc8AWWP7WRRv4JM3HSRu EOXorCJ6mMsaVw72k2LarG0A60qTydHZPwnLqhdFOngZ050f4F/uKPHTUcmIPkU618FV 2autWXwK49LABMNg4bm3hQkBngEBHzSTIV3SdWIHWBMw4PqXBsGQ01alrjOOIYYX8Z9u LyfnZghmHDJkTV0aKD2uSoAPH/tGJcojrFO8ADaMJygmGkiL9NvMvwjCRPnHG5uOWCuX DQyQ== X-Gm-Message-State: AOAM5302uQiHcPLOAnmTcWH/FcGWYkDhVfCD+Rx028QcjBkL+nFmHtzK HZl89mw49qwUAe+TZ9JRtiqj X-Received: by 2002:a17:90a:31cf:: with SMTP id j15mr22329179pjf.41.1615182321795; Sun, 07 Mar 2021 21:45:21 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6e84:fef9:1070:d306:6d0e:bf6b]) by smtp.gmail.com with ESMTPSA id y29sm4331506pfp.206.2021.03.07.21.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Mar 2021 21:45:21 -0800 (PST) From: Manivannan Sadhasivam To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, boris.brezillon@collabora.com, Daniele.Palmas@telit.com, bjorn.andersson@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 3/3] mtd: rawnand: qcom: Add support for secure regions in NAND memory Date: Mon, 8 Mar 2021 11:14:47 +0530 Message-Id: <20210308054447.28418-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210308054447.28418-1-manivannan.sadhasivam@linaro.org> References: <20210308054447.28418-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). The regions are declared using a NAND chip DT property, "secure-regions". So let's make use of this property and skip access to the secure regions present in a system. Signed-off-by: Manivannan Sadhasivam --- drivers/mtd/nand/raw/qcom_nandc.c | 72 +++++++++++++++++++++++++++---- 1 file changed, 63 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 87c23bb320bf..8027f7cb32be 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -431,6 +431,11 @@ struct qcom_nand_controller { * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for * ecc/non-ecc mode for the current nand flash * device + * + * @sec_regions: Array representing the secure regions in the + * NAND chip + * + * @nr_sec_regions: Number of secure regions in the NAND chip */ struct qcom_nand_host { struct nand_chip chip; @@ -453,6 +458,9 @@ struct qcom_nand_host { u32 ecc_bch_cfg; u32 clrflashstatus; u32 clrreadstatus; + + u32 *sec_regions; + u8 nr_sec_regions; }; /* @@ -662,16 +670,27 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, } /* helper to configure address register values */ -static void set_address(struct qcom_nand_host *host, u16 column, int page) +static int set_address(struct qcom_nand_host *host, u16 column, int page) { struct nand_chip *chip = &host->chip; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + u32 offs = page << chip->page_shift; + int i, j; + + /* Skip touching the secure regions if present */ + for (i = 0, j = 0; i < host->nr_sec_regions; i++, j += 2) { + if (offs >= host->sec_regions[j] && + (offs <= host->sec_regions[j] + host->sec_regions[j + 1])) + return -EIO; + } if (chip->options & NAND_BUSWIDTH_16) column >>= 1; nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); + + return 0; } /* @@ -1491,13 +1510,13 @@ static void qcom_nandc_command(struct nand_chip *chip, unsigned int command, WARN_ON(column != 0); host->use_ecc = true; - set_address(host, 0, page_addr); + ret = set_address(host, 0, page_addr); update_rw_regs(host, ecc->steps, true); break; case NAND_CMD_SEQIN: WARN_ON(column != 0); - set_address(host, 0, page_addr); + ret = set_address(host, 0, page_addr); break; case NAND_CMD_PAGEPROG: @@ -1615,7 +1634,10 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, host->use_ecc = false; clear_bam_transaction(nandc); - set_address(host, host->cw_size * cw, page); + ret = set_address(host, host->cw_size * cw, page); + if (ret) + return ret; + update_rw_regs(host, 1, true); config_nand_page_read(nandc); @@ -1943,7 +1965,10 @@ static int copy_last_cw(struct qcom_nand_host *host, int page) /* prepare a clean read buffer */ memset(nandc->data_buffer, 0xff, size); - set_address(host, host->cw_size * (ecc->steps - 1), page); + ret = set_address(host, host->cw_size * (ecc->steps - 1), page); + if (ret) + return ret; + update_rw_regs(host, 1, true); config_nand_single_cw_page_read(nandc, host->use_ecc); @@ -2005,12 +2030,16 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page) struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret; clear_read_regs(nandc); clear_bam_transaction(nandc); host->use_ecc = true; - set_address(host, 0, page); + ret = set_address(host, 0, page); + if (ret) + return ret; + update_rw_regs(host, ecc->steps, true); return read_page_ecc(host, NULL, chip->oob_poi, page); @@ -2188,7 +2217,10 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, 0, mtd->oobavail); - set_address(host, host->cw_size * (ecc->steps - 1), page); + ret = set_address(host, host->cw_size * (ecc->steps - 1), page); + if (ret) + return ret; + update_rw_regs(host, 1, false); config_nand_page_write(nandc); @@ -2267,7 +2299,10 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs) /* prepare write */ host->use_ecc = false; - set_address(host, host->cw_size * (ecc->steps - 1), page); + ret = set_address(host, host->cw_size * (ecc->steps - 1), page); + if (ret) + return ret; + update_rw_regs(host, 1, false); config_nand_page_write(nandc); @@ -2830,7 +2865,8 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, struct nand_chip *chip = &host->chip; struct mtd_info *mtd = nand_to_mtd(chip); struct device *dev = nandc->dev; - int ret; + struct property *prop; + int ret, length, nr_elem; ret = of_property_read_u32(dn, "reg", &host->cs); if (ret) { @@ -2872,6 +2908,24 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, /* set up initial status value */ host->status = NAND_STATUS_READY | NAND_STATUS_WP; + /* + * Look for secure regions in the NAND chip. These regions are supposed + * to be protected by a secure element like Trustzone. So the read/write + * accesses to these regions will be blocked in the runtime by this + * driver. + */ + prop = of_find_property(dn, "secure-regions", &length); + if (prop) { + nr_elem = length / sizeof(u32); + host->nr_sec_regions = nr_elem / 2; + + host->sec_regions = devm_kcalloc(dev, nr_elem, sizeof(u32), GFP_KERNEL); + if (!host->sec_regions) + return -ENOMEM; + + of_property_read_u32_array(dn, "secure-regions", host->sec_regions, nr_elem); + } + ret = nand_scan(chip, 1); if (ret) return ret;