From patchwork Sun Mar 7 07:04:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 395205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CB41C433E9 for ; Sun, 7 Mar 2021 07:05:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F3B7365129 for ; Sun, 7 Mar 2021 07:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230140AbhCGHE5 (ORCPT ); Sun, 7 Mar 2021 02:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229971AbhCGHEb (ORCPT ); Sun, 7 Mar 2021 02:04:31 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEBB7C06174A; Sat, 6 Mar 2021 23:04:30 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 124-20020a1c00820000b029010b871409cfso1849723wma.4; Sat, 06 Mar 2021 23:04:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Ub3gKGJwLJRaryXIKn0038/d6bzjLaWe3sRPb09LY0=; b=AmB7IwiFXx0W13v8S9Z2zbPBM7+n887S+jm3NBBFN2lfZiaLPdECQRuUviS2w7wFOB lfnxNHM7crl+YYuytYu9kMdbYXk+/1hAfwuN0dyE6tDZxNf9qe+LvS6m8eSKMcF4aDlr WmlDmxGP9I/W75pwwP7GrLXpQAnA9YspWj1wYS9NKw/+TX0UCG/ypkjpoqEZtwAEu1PG m0voZoS6zB0Pm/VsKV07sIur4MOdVFTL3tNxttVZed2zdPgHHI1IVSvUa7bxDOSZNdU3 GEr1sQfciYwpDA40lmawQ/Izsv57GkFB7jAQiz5bc/VVT0YB84/usK3zxDTRXtkuEccY DqPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Ub3gKGJwLJRaryXIKn0038/d6bzjLaWe3sRPb09LY0=; b=L3fIQEcbcZaCDkyOzXKp2/P0FK2H+9B2M5Byaw1N9NhOY6uZL87OOoy3bJCht/ZYGY A+gTLd5jefQqzrkSRlstbRUgRnEanGQ4UlQ6iU5vvMDMjCyuZuM7B1CfT2+lGZrANwSP YX0kZtMIyril6PiByleQFxtQuz60pC08zHpJcPYjM0Taaix7qgGoO2Q7pxXQf/6FQT4h XtrcUNIL/UF/d+3FaDgTMhQRAsfsm089eKPDLxqeESIklhmeBDdMqQ8gSvziYEUiD97M EyOnU7+OJERr+cL8SaJTJNDY5/NFaWLqkmP9aQfPz4Lik63P+jr6K8eidlbuYPckrSN0 7BAQ== X-Gm-Message-State: AOAM530odZviaD7cGqgXZfEccaerc6yZ/cFhcJI1spwfud4sC9ID9SbH G52UYhHIVSCWzQqoctnjcRA= X-Google-Smtp-Source: ABdhPJyfKAoQsPOxQOdi2EBax2XgOCjp2YAIO/dGDM9G4jHSQUDuK5/fBT+8oLKopuFZb1bbS/3wAQ== X-Received: by 2002:a7b:c0c4:: with SMTP id s4mr16866001wmh.9.1615100669632; Sat, 06 Mar 2021 23:04:29 -0800 (PST) Received: from localhost.localdomain (67.red-83-54-30.dynamicip.rima-tde.net. [83.54.30.67]) by smtp.gmail.com with ESMTPSA id j9sm12162533wmi.24.2021.03.06.23.04.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 Mar 2021 23:04:29 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v10 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Date: Sun, 7 Mar 2021 08:04:21 +0100 Message-Id: <20210307070426.15933-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210307070426.15933-1-sergio.paracuellos@gmail.com> References: <20210307070426.15933-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index 000000000000..1422badcf9de --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Sergio Paracuellos + */ + +#ifndef _DT_BINDINGS_CLK_MT7621_H +#define _DT_BINDINGS_CLK_MT7621_H + +#define MT7621_CLK_XTAL 0 +#define MT7621_CLK_CPU 1 +#define MT7621_CLK_BUS 2 +#define MT7621_CLK_50M 3 +#define MT7621_CLK_125M 4 +#define MT7621_CLK_150M 5 +#define MT7621_CLK_250M 6 +#define MT7621_CLK_270M 7 + +#define MT7621_CLK_HSDMA 8 +#define MT7621_CLK_FE 9 +#define MT7621_CLK_SP_DIVTX 10 +#define MT7621_CLK_TIMER 11 +#define MT7621_CLK_PCM 12 +#define MT7621_CLK_PIO 13 +#define MT7621_CLK_GDMA 14 +#define MT7621_CLK_NAND 15 +#define MT7621_CLK_I2C 16 +#define MT7621_CLK_I2S 17 +#define MT7621_CLK_SPI 18 +#define MT7621_CLK_UART1 19 +#define MT7621_CLK_UART2 20 +#define MT7621_CLK_UART3 21 +#define MT7621_CLK_ETH 22 +#define MT7621_CLK_PCIE0 23 +#define MT7621_CLK_PCIE1 24 +#define MT7621_CLK_PCIE2 25 +#define MT7621_CLK_CRYPTO 26 +#define MT7621_CLK_SHXC 27 + +#define MT7621_CLK_MAX 28 + +#endif /* _DT_BINDINGS_CLK_MT7621_H */ From patchwork Sun Mar 7 07:04:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 395204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FEA5C4332E for ; Sun, 7 Mar 2021 07:05:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7DD9465125 for ; Sun, 7 Mar 2021 07:05:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230184AbhCGHE5 (ORCPT ); Sun, 7 Mar 2021 02:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230023AbhCGHEc (ORCPT ); Sun, 7 Mar 2021 02:04:32 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD1D0C06174A; Sat, 6 Mar 2021 23:04:31 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id b18so7835503wrn.6; Sat, 06 Mar 2021 23:04:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+4put77zvWkbAq7p9W7RkFBT+N9LdQEWztn2bykM+dQ=; b=j0zWpsa/gayzQcRkqn1TPbYerYny+Qaq2VBhPEsUdG6qG9WgmeFw+7BOF8VysbRacY lwObp4O0qamLO6g7qQL4qV7YVm2AOjefupQo/5vNxp29lg8oT/9t5IewZcTRZgHSfWh+ GKjPPBRAeHB0iGzXlUUOE2bBbtd4+unecFBSUqJUih1Dq5ey4feOCOlwETRQ7a2RxFYC KU1uqR56BQtxLjzjf3fxh+Fq1yHjTiPY5/gNyf3feMouq42kZFxJB3638k4iq0xim6zR +oPr321O41jU8mGHFETTX543z+Fh7MAENfAbc00p4HeZriKMXAnekYSWmPIVARu/G+Pk F3SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+4put77zvWkbAq7p9W7RkFBT+N9LdQEWztn2bykM+dQ=; b=Tz1+vwJ3TPRSUb+4tVb07i41HpzjdwPdG7xbpEe4IEd8QQ223Ol9ZC/TZ1lRrgUmjl SvkYaWP35u3uMQsN+MVHM8j1WC1f3B0S011sEbDFA/jbRo5N/HNFtin1dKJ3Lz0uF28M D+Fg7w+z7eimaNOgrBpf0WTKFAeUzCEkUtE1p1H8mH4LQYayOHaevA+Dtf688GodX6l9 UKHvlc8wPhNg3ZyZPBbGbGo1bwtg0e3V+pM7Ft9sVdq2QowsKn79CuvG0BHbSKQfu4LJ BszfhNGxlmbRiAUBeDPhU88whF2axDPsi1WmyV9/hUwuIKbwu+c8+XGVFbc8bqvOhbmh hKCA== X-Gm-Message-State: AOAM531GoUAJo6Tiy4kITp4bkTTfC9kUiXImofi9eyxi7ujS27/WmEFe xmgP9IPkFm3i4z72NdA1D+8= X-Google-Smtp-Source: ABdhPJx5anhLHtuwZJ35GutGutDkvSApUcSdd+GOoolyFWaE52xNkXpmslTdGPbaj8STtRoE+IpWHg== X-Received: by 2002:adf:e603:: with SMTP id p3mr17312337wrm.360.1615100670672; Sat, 06 Mar 2021 23:04:30 -0800 (PST) Received: from localhost.localdomain (67.red-83-54-30.dynamicip.rima-tde.net. [83.54.30.67]) by smtp.gmail.com with ESMTPSA id j9sm12162533wmi.24.2021.03.06.23.04.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 Mar 2021 23:04:30 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH v10 2/6] dt: bindings: add mt7621-sysc device tree binding documentation Date: Sun, 7 Mar 2021 08:04:22 +0100 Message-Id: <20210307070426.15933-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210307070426.15933-1-sergio.paracuellos@gmail.com> References: <20210307070426.15933-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos Reviewed-by: Rob Herring --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml new file mode 100644 index 000000000000..ef2d71b23ba0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: . + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: mediatek,mt7621-sysc + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + ralink,memctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control memory registers + + clock-output-names: + maxItems: 8 + +required: + - compatible + - reg + - '#clock-cells' + - ralink,memctl + +additionalProperties: false + +examples: + - | + #include + + sysc: sysc@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; From patchwork Sun Mar 7 07:04:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 395202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ED03C15506 for ; Sun, 7 Mar 2021 07:05:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 579456513A for ; Sun, 7 Mar 2021 07:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230272AbhCGHE7 (ORCPT ); Sun, 7 Mar 2021 02:04:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbhCGHEe (ORCPT ); Sun, 7 Mar 2021 02:04:34 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA6DC06175F; Sat, 6 Mar 2021 23:04:34 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id j4-20020a05600c4104b029010c62bc1e20so1814815wmi.3; Sat, 06 Mar 2021 23:04:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Y7ZqJ7aphYkfKg9dEOtdy4V6nKSW7Mz/xYiwcmDq+A=; b=TxY5FAVv88lgQE2+LrnZ5LvGh4ZRLQCLkAgXJkl2SuuNdx/uKdRcD1NhyqZ/3a6BiP pC0D1tJQ1dKiCj2rdN09OY+d+dpt7X69l5Wzh0Pnp+6+WIwk83h8rvPgK5oz6fqJ5FgX K6FmwacK3V686yOe7CKDq6qHWU8tF2/8ruxxjXYh/i9IQCLL0OPTByGWvSMKFWcSsarx vUy6/ojES05vlnOa/wBRLUGIhzg3OuFnV76wUmEGA2iBqxA6r5SKxpglruQwcP0K34hl gEYjVJ66eUI5u8CQs2CSR8dabWMy4kDHdWFjK28+K2OY3P/CzWLq0LGxKuJZ6cgfo3EW OuAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Y7ZqJ7aphYkfKg9dEOtdy4V6nKSW7Mz/xYiwcmDq+A=; b=H2k+gLnuXbzksGBllWHjwE5FcRz9wxllakRcnRzVyIDZvvO/B20UqAgkXTKD3obIvd ye0jUvg3NJy7ZuRkS/FBa2M6Zjn6ydOl6guxZlIWY+by690TS1B6LUGFZ8eZMU5pXtEe GNqZpwO7VOMBDoYcmrpQQF9KvgokoBLW1LczYFw9qHfCrVr/P7AjVP2hWp0uXoTl+lES P8zlr43/Q8sujAGNLJeeiwKq8/3BePiXEFpCQvelDJG4+Hf8DitF/5mFlXjtG6ovhoUK n3QC9tXjPC+8u6o49Y7ylV2HBAcln1/cRx6SXhLboAy0xS3R5/CeP222k23jEuoYLNZn 0WpA== X-Gm-Message-State: AOAM531Ec7f+5XoLE44SHLiBvPllqGKqQKovY7cBdNVHgCg/t7/kxMVr n9EbQPJbsx54dTFucXKOce8= X-Google-Smtp-Source: ABdhPJz1kaIGwonywkkzFRP2nJuAjnyRm8GqZdH5T8yOm+CZpFPlNpGaZfiuI3/7n8lRPOLzDwzJXA== X-Received: by 2002:a7b:cd81:: with SMTP id y1mr16711143wmj.51.1615100672861; Sat, 06 Mar 2021 23:04:32 -0800 (PST) Received: from localhost.localdomain (67.red-83-54-30.dynamicip.rima-tde.net. [83.54.30.67]) by smtp.gmail.com with ESMTPSA id j9sm12162533wmi.24.2021.03.06.23.04.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 Mar 2021 23:04:32 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH v10 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Date: Sun, 7 Mar 2021 08:04:24 +0100 Message-Id: <20210307070426.15933-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210307070426.15933-1-sergio.paracuellos@gmail.com> References: <20210307070426.15933-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/gbpc1.dts | 11 ---- drivers/staging/mt7621-dts/mt7621.dtsi | 74 ++++++++++++-------------- 2 files changed, 33 insertions(+), 52 deletions(-) diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts index a7c0d3115d72..7716d0efe524 100644 --- a/drivers/staging/mt7621-dts/gbpc1.dts +++ b/drivers/staging/mt7621-dts/gbpc1.dts @@ -100,17 +100,6 @@ partition@50000 { }; }; -&sysclock { - compatible = "fixed-clock"; - /* This is normally 1/4 of cpuclock */ - clock-frequency = <225000000>; -}; - -&cpuclock { - compatible = "fixed-clock"; - clock-frequency = <900000000>; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 16fc94f65486..b68183e7e6ad 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,5 +1,6 @@ #include #include +#include / { #address-cells = <1>; @@ -27,27 +28,6 @@ aliases { serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* This is normally 1/4 of cpuclock */ - clock-frequency = <220000000>; - }; - - mmc_clock: mmc_clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; mmc_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; @@ -76,8 +56,13 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; + compatible = "mtk,mt7621-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; }; wdt: wdt@100 { @@ -101,8 +86,8 @@ i2c: i2c@900 { compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysclock>; - + clocks = <&sysc MT7621_CLK_I2C>; + clock-names = "i2c"; resets = <&rstctrl 16>; reset-names = "i2c"; @@ -119,8 +104,8 @@ i2s: i2s@a00 { compatible = "mediatek,mt7621-i2s"; reg = <0xa00 0x100>; - clocks = <&sysclock>; - + clocks = <&sysc MT7621_CLK_I2S>; + clock-names = "i2s"; resets = <&rstctrl 17>; reset-names = "i2s"; @@ -138,7 +123,7 @@ i2s: i2s@a00 { }; memc: memc@5000 { - compatible = "mtk,mt7621-memc"; + compatible = "mtk,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; }; @@ -156,8 +141,8 @@ uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; - clock-frequency = <50000000>; + clocks = <&sysc MT7621_CLK_UART1>; + clock-names = "uart1"; interrupt-parent = <&gic>; interrupts = ; @@ -173,7 +158,8 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&sysc MT7621_CLK_SPI>; + clock-names = "spi"; resets = <&rstctrl 18>; reset-names = "spi"; @@ -189,6 +175,8 @@ gdma: gdma@2800 { compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; + clocks = <&sysc MT7621_CLK_GDMA>; + clock-names = "gdma"; resets = <&rstctrl 14>; reset-names = "dma"; @@ -206,6 +194,8 @@ hsdma: hsdma@7000 { compatible = "mediatek,mt7621-hsdma"; reg = <0x7000 0x1000>; + clocks = <&sysc MT7621_CLK_HSDMA>; + clock-names = "hsdma"; resets = <&rstctrl 5>; reset-names = "hsdma"; @@ -311,11 +301,6 @@ rstctrl: rstctrl { #reset-cells = <1>; }; - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -334,7 +319,8 @@ sdhci: sdhci@1E130000 { pinctrl-0 = <&sdhci_pins>; pinctrl-1 = <&sdhci_pins>; - clocks = <&mmc_clock &mmc_clock>; + clocks = <&sysc MT7621_CLK_SHXC>, + <&sysc MT7621_CLK_50M>; clock-names = "source", "hclk"; interrupt-parent = <&gic>; @@ -349,7 +335,7 @@ xhci: xhci@1E1C0000 { 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; - clocks = <&sysclock>; + clocks = <&sysc MT7621_CLK_XTAL>; clock-names = "sys_ck"; interrupt-parent = <&gic>; @@ -368,7 +354,7 @@ gic: interrupt-controller@1fbc0000 { timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&sysc MT7621_CLK_CPU>; }; }; @@ -381,6 +367,9 @@ nand: nand@1e003000 { 0x1e003800 0x800>; #address-cells = <1>; #size-cells = <1>; + + clocks = <&sysc MT7621_CLK_NAND>; + clock-names = "nand"; }; ethsys: syscon@1e000000 { @@ -394,8 +383,9 @@ ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysclock>; - clock-names = "ethif"; + clocks = <&sysc MT7621_CLK_FE>, + <&sysc MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; #address-cells = <1>; #size-cells = <0>; @@ -521,7 +511,9 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clocks = <&sysc MT7621_CLK_PCIE0>, + <&sysc MT7621_CLK_PCIE1>, + <&sysc MT7621_CLK_PCIE2>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2"; From patchwork Sun Mar 7 07:04:26 2021 Content-Type: text/plain; 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[83.54.30.67]) by smtp.gmail.com with ESMTPSA id j9sm12162533wmi.24.2021.03.06.23.04.33 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 Mar 2021 23:04:34 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH v10 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Date: Sun, 7 Mar 2021 08:04:26 +0100 Message-Id: <20210307070426.15933-7-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210307070426.15933-1-sergio.paracuellos@gmail.com> References: <20210307070426.15933-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L: linux-wireless@vger.kernel.org S: Maintained F: drivers/net/wireless/mediatek/mt7601u/ +MEDIATEK MT7621 CLOCK DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml +F: drivers/clk/ralink/clk-mt7621.c + MEDIATEK MT7621/28/88 I2C DRIVER M: Stefan Roese L: linux-i2c@vger.kernel.org