From patchwork Fri Mar 5 19:16:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393584 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp690458jai; Fri, 5 Mar 2021 11:09:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJzVVPR0TLyiU3zDXJlEjYCDDLzPL+MYUgegXn1t8xi6edJnQq//OjtArkgXRs5nZfg21njH X-Received: by 2002:a05:6402:3049:: with SMTP id bu9mr10813290edb.104.1614971347860; Fri, 05 Mar 2021 11:09:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614971347; cv=none; d=google.com; s=arc-20160816; b=a/KLoBOI59ewin3Z15zeqnXjk9NGgl6zrQh+Q5/pPeKhhno31gmbk+1VTT63P2Nb54 09lfG3A35Gspg4Rx3jm3mWb4tporx4pNHOLoAfXvOuLTl/u5dle2RY2ocjRldzppjV3Q eTgL2rT6FgCEg0Vy7T6khyA+XDTUDUD9ylZs1r7+b+INq7tLNevboQcAcOp+VsGypAZB MwVpi4ujGshsH5JV75oybFV9RbaTkR+sKMphzuEH82zG8SlVrGJonuqNxOYczVDiS5Fb WWvDPKmqBkMZVdaD5S2eNF1DnNC6c7xhMXBaiMrNJ4eSxT/f1g4hK9DeQ2bRC6XFAObC Mkhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from :dkim-signature; bh=VV6l2UYIK3KjG62wbZQyRbbCwbcaL9xMG+xJectCaSQ=; b=LPxqpFt7mtmU6oDdMJkikwUPDHU3+kaAXcMU5+G6fg5BbEUZ8qEJeNDJ9Nwl8fP1Xc yOKwyKPOqapr8T5fpXQvRa/chG4tEooFk3VI963SLArqqCERXL+ehlF+BiWs8LGhLdY8 ZQaKfEOHitOTnnSyp++LpLD3t2+Zy/edLIFpwQ3A6Wu96GRckukYNHlvcZ5GUrcE2U5/ bv31oMb7XFCYJQVmKGwb8zsH7vJ+Ua23KoVgfKwhtoNInUfgui1oueZ/qaUO/o4awk7n 4HTL8uXjKUSSaB2lQJotsdQVKHl48EUfLVS8iffphXritynEIS0ll1Un/doA5M2+2teU Vr0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bzxxKMo6; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ml22si1089671ejb.629.2021.03.05.11.09.07; Fri, 05 Mar 2021 11:09:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bzxxKMo6; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229589AbhCETIf (ORCPT + 16 others); Fri, 5 Mar 2021 14:08:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230087AbhCETIX (ORCPT ); Fri, 5 Mar 2021 14:08:23 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6046FC061574 for ; Fri, 5 Mar 2021 11:08:22 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id d11so3238673wrj.7 for ; Fri, 05 Mar 2021 11:08:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=VV6l2UYIK3KjG62wbZQyRbbCwbcaL9xMG+xJectCaSQ=; b=bzxxKMo6Ogos8ed1bQ6s6udD/kJ9kQL+1u7FQeFbjidgEvu7cBJ7VGiE9Pl9+cvX6e sAxLTFoXPOWnUBZO+tojPnSHCleOjw8eb0nXTbsvx62naFi+h5VJUSF4vHvLERKNnEgS F+Y5H5XYcK759NObYrQN1pJafRKkCHwrDg3Rz2QYQQLWZ25uoKjeglKuDYYP+cQe9QDS g05OmBw0+CVQ8pPD47CPwJpMmx/Zkwgq8omYzjfg2wPGAmUUhyh3Z2y32D0d38oz3xb4 d7g0qt2PpP8wSNmdXp408Op28gMqny3F4UIx7sw+wNwW1pV/wwTqhldsgf4eBj+8lXre C6xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=VV6l2UYIK3KjG62wbZQyRbbCwbcaL9xMG+xJectCaSQ=; b=YRz4hbaM9lj+3UavwkuTdmVVSCfaB9z4d2pd3AqzRwjnoPij9cHgRjSqK14yvRLGd9 WpZvqqCiJA8OKgH4zpbsgDPmdZlwwyJNSB+GKGYGS30nvdhGKuQ8ySND/3aMcodAibKh 19Kz2leNRE8OhkpOC9jArycYpGYgQy30QNpwxEyseXZHVQvvi9oiQk7jAAxposDNWea+ hqKfLHW9bx7ne3AnM0fSjQ/0N2E3Sw29DhGRfERsyYTymZYTH8zakL/Ub5eg6NpL8Qt0 PQ1BIGb6qgHFfqWynhBEIPmCf4T2jsdhWa8rbp17P194Y6x7O2Me5JMLhSv0MGIGemzS hd4A== X-Gm-Message-State: AOAM532E7bN//o4vzEoRh/jUJVZY+GzZ2ST1ZpLCs9760BCe4zhAy9fA rROp8TR+LXxTGi53LHH6+pPyRQ== X-Received: by 2002:adf:fe09:: with SMTP id n9mr11017306wrr.104.1614971300978; Fri, 05 Mar 2021 11:08:20 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:55da:a740:2edb:1c7e]) by smtp.gmail.com with ESMTPSA id c11sm5355437wrs.28.2021.03.05.11.08.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Mar 2021 11:08:20 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v3 1/6] mhi: pci_generic: Parametrable element count for events Date: Fri, 5 Mar 2021 20:16:43 +0100 Message-Id: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all hardwares need to use the same number of event ring elements. This change makes this parametrable. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- v2: no change v3: no change drivers/bus/mhi/pci_generic.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 8187fcf..c58bf96 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -71,9 +71,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = false, \ } -#define MHI_EVENT_CONFIG_CTRL(ev_ring) \ +#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ { \ - .num_elements = 64, \ + .num_elements = el_count, \ .irq_moderation_ms = 0, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -114,9 +114,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } -#define MHI_EVENT_CONFIG_DATA(ev_ring) \ +#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ - .num_elements = 128, \ + .num_elements = el_count, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -127,9 +127,9 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } -#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ +#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ { \ - .num_elements = 2048, \ + .num_elements = el_count, \ .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -156,12 +156,12 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { static struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ - MHI_EVENT_CONFIG_CTRL(0), + MHI_EVENT_CONFIG_CTRL(0, 64), /* DIAG dedicated event ring */ - MHI_EVENT_CONFIG_DATA(1), + MHI_EVENT_CONFIG_DATA(1, 128), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(2, 100), - MHI_EVENT_CONFIG_HW_DATA(3, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) }; static struct mhi_controller_config modem_qcom_v1_mhiv_config = { From patchwork Fri Mar 5 19:16:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393589 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp690500jai; Fri, 5 Mar 2021 11:09:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJyz2MAToeeBLeeTRvLAGn8AJlHxEogeFpKP1FHBqDO7qKZwXPpsQgFfSZQh4fmMJ7jYaGYr X-Received: by 2002:a17:906:3f96:: with SMTP id b22mr3686952ejj.478.1614971350700; Fri, 05 Mar 2021 11:09:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614971350; cv=none; d=google.com; s=arc-20160816; b=YtNR76Qk0aA9GHNPTX4jaR3BrGE+UWzh1rqL4yHc/w8dipLzuEF+N3tQLqZxIUAXmO tMhFK3f1Stqe19dPwYDtLe2c3tlm1edVMB7sdm41kDkH0+Atdj4M5SUvfMF31B0TtcKX 6DTaVSK2hHfrFzjS0qr+i/P1AwQ/dHxvAUcoYr7ThOGW1HahejhXZtx6MFr3QTnA4est piosalMXTVwS+KSMwT/tZlOeU7H3sorvhhDp4VztzqN+FPwpM5iqDWzWwuoAHRinxFuw raISN/ncj93hOfSV6DBA6GBd+kuRQcs2BFfJLIpCVNlr/TTApk03Fjpg8xxJmykgqc0r DZRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=7G9A1TBrr/rvyfIfwUmC1Wqq1DUUgbMT2BKXZ0DzFl8=; b=AM/gyYII3560HsZbNfS2ZRStK9yln/wPIeLak7+jWwCnSBNvIuOluf0MPJ/HzRZxKh 8Ra4JhcDA26BYtvQr3c1KbcG1JirtO5P2XmkXOm5iZIY+TTydXcWlEW73HrjdkwaS8FH wjIOmhPLFuoyIQmmq3mNnI36VbhLa/XphdblJqcIN2NhycGTQQ1cR1K+/2ljXXoT6I2i ZGbWUvhMkBZyd0qeZLVv1tQ6Bu6eEKk1HePwxMijkD8ZTzF5XB0vftMQUDX1OcRaz6yz gyMTG+ePXPt6QtABFaGLt6tNgc0PdZUOtPt2hmBGQFQPkfrZ7Xjmhq69lCvOj3mMdVw9 BqKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QoU3xVHl; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ml22si1089671ejb.629.2021.03.05.11.09.10; Fri, 05 Mar 2021 11:09:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QoU3xVHl; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229591AbhCETIf (ORCPT + 16 others); Fri, 5 Mar 2021 14:08:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230089AbhCETIY (ORCPT ); Fri, 5 Mar 2021 14:08:24 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE695C061574 for ; Fri, 5 Mar 2021 11:08:23 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id v15so3245690wrx.4 for ; Fri, 05 Mar 2021 11:08:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7G9A1TBrr/rvyfIfwUmC1Wqq1DUUgbMT2BKXZ0DzFl8=; b=QoU3xVHlVE9VxGu0CpwsK2MVpmUV8lng4DnYW3gVdzARhivUP438tDt0aaXxyqkwCW KF7dhaKlFGBbNA1AKQRMUAlv6MAnwnn34yrisdaIg3qG00I8n+DkYvHoPS5DALAIYQwb qL/QYS4AiFCfhpdlcZWDVL8I4rZQdMRWUaf2rQCdFHsqbEWi6/f1xGwWWzR4/MlfSy2M 3Yn0wZPiVp6uxy2yp01WyHu2fFS0ORAS9sqlJSX6fgU8qank0J5iUKYH1eAmPol3zzHm JfvsPrYFIr4X4tDf3N6ynRGzw2kcD0X2FtH+Us1k0McnpdwPvvnrhA6vL6E+Frkt7yho sltw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7G9A1TBrr/rvyfIfwUmC1Wqq1DUUgbMT2BKXZ0DzFl8=; b=IoCY4w4BuzNDKX9xXBlZs8nF7zXSkosPxyU1b9oHoB8OIrTUSYM90KdfwIAbzovMEo 6GpOEG/VfA7bKpX7SdJKFU/F4LNdU7RpebNjydxhMb9ZhOtrQE6E5sBzOTZKsEK3CKhY ARxaQf5RjC09MTFapGs+j7Jp9poyOhRHodqZrPir11tWL9m7P9K/MCbGcirF+wkSyLDW BcUJtyggpIeYuJBXFTFRkQDIP5lasgWWXopyt4FnRlhxuS0RsNugx5hFcxTwRSgqd6wA 4cfXFsL9W4JFoipJv7cwBl2ldNRnWef/8WQJiLEopK0mjmHhV9eOT3148OkORtx91mz6 /qBQ== X-Gm-Message-State: AOAM531rfI1iCwIvccbYw2VtzgqADLrdXbhw/C8renT6pFqEU2dh41Rr YDRDAybISF+VaEn44gT48vAYEA== X-Received: by 2002:adf:fecc:: with SMTP id q12mr10632342wrs.317.1614971302423; Fri, 05 Mar 2021 11:08:22 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:55da:a740:2edb:1c7e]) by smtp.gmail.com with ESMTPSA id c11sm5355437wrs.28.2021.03.05.11.08.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Mar 2021 11:08:22 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v3 2/6] mhi: pci_generic: Introduce quectel EM1XXGR-L support Date: Fri, 5 Mar 2021 20:16:44 +0100 Message-Id: <1614971808-22156-2-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> References: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for EM1XXGR-L modems, this modem series is based on SDX24 qcom chip. The modem is mainly based on MBIM protocol for both the data and control path. The drivers for these channels (mhi-net-mbim and mhi_uci) are not yet part of the kernel but will be integrated by different series. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- v2: update timeout_ms according real modem boot time v3: no change drivers/bus/mhi/pci_generic.c | 73 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c58bf96..45d0cf2 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -114,6 +114,36 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } +#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } \ + +#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ .num_elements = el_count, \ @@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), +}; + +static struct mhi_event_config mhi_quectel_em1xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 128), + MHI_EVENT_CONFIG_DATA(1, 128), + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) +}; + +static struct mhi_controller_config modem_quectel_em1xx_config = { + .max_channels = 128, + .timeout_ms = 20000, + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), + .ch_cfg = mhi_quectel_em1xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), + .event_cfg = mhi_quectel_em1xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { + .name = "quectel-em1xx", + .edl = "qcom/prog_firehose_sdx24.mbn", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); From patchwork Fri Mar 5 19:16:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393588 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp690493jai; Fri, 5 Mar 2021 11:09:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJz7ncRGR2mSwMZ6SHWqdIHwkeqF3tzLpBD3nppCJBw9iChoPddCxQQIbXkZYsydKTOzhhnd X-Received: by 2002:a05:6402:1d1a:: with SMTP id dg26mr10398277edb.266.1614971350202; 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Also add the FIREHOSE channels used by the flash-programmer firmware loaded in EDL mode. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- v2: no change v3: no change drivers/bus/mhi/pci_generic.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 45d0cf2..c274e65 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -212,6 +212,14 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { + .name = "qcom-sdx24", + .edl = "qcom/prog_firehose_sdx24.mbn", + .config = &modem_qcom_v1_mhiv_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), @@ -254,6 +262,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), + .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ From patchwork Fri Mar 5 19:16:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393587 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp690484jai; Fri, 5 Mar 2021 11:09:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJzASiLzxJR0Ar1mX+kbm9TXZkoWx2/QpzWr+ofzmDk6oXO5yjQowdjnDx8PQT0BoWrfTcg/ X-Received: by 2002:a05:6402:3049:: with SMTP id bu9mr10813459edb.104.1614971349604; Fri, 05 Mar 2021 11:09:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614971349; cv=none; d=google.com; s=arc-20160816; b=ojqtIHZAvoP7Fpm7db/2AuXZkTzOg1Jsx2qC7UDLHaKTo8pOVw7i9mKU54C5X7AS/q bF1woVOIFdrNGuMkaeAOJd4hlBizCyM7CgdQ56uDX1dAgeo6o9Bk+c66e5dJSC3bwQsK 5RH/wql4yomubRAkdnPz1vV1+HtBN1HelTIzpOiCIyOT8W82vHYghVrlqpHCpTqvftB9 5Zp/rTPMHZ9yqQVcodf1uXwHa4cXZWiZtnU6kME66m5gzESzb0S1AMcpPW4S37X55I5n O1h/aFGcH2C003LhcFSl8FEPlQRBfKNar9YFxxBkJ11xHDu64iZwfgh6PgKrD49YtM1Y yoqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=634De0VmcZftqA0EsYtSRssGeJ1lMakbJs+e7qthPxU=; b=wmFmdnAdvWPhXtwsJe8UqMOAPzT02CrXeQbHG42EKlkKcC8saod00x6Yxfha7gtFST XT9mcHzh/lvfb/MEUnng+sYToC4BGz/8CZAPDzOdv5oOL9tpcCy/nEPXHQrR5W3ud3Jo JZZr1zqEAaimNotKiUwaxLQMVJm6mnuBn+esCN7wlRZRxUqqPc+Ou67zM/y7eRD4HmKt f7yBbojCplUC1fYU1CZAx4tYTQpKB4OgbHHpbuIEsZFo8kX99RDPwNgzB+65hFEdLQlW naT8i/jLKQT7AgsCrXG6k/bzxGdSZzUKIwdsy8aoOSphEru53kgernQILudPpvZsUdsJ mQgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMMbvn7I; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ml22si1089671ejb.629.2021.03.05.11.09.09; Fri, 05 Mar 2021 11:09:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMMbvn7I; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229955AbhCETIf (ORCPT + 16 others); Fri, 5 Mar 2021 14:08:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbhCETI0 (ORCPT ); Fri, 5 Mar 2021 14:08:26 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB420C061574 for ; Fri, 5 Mar 2021 11:08:25 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id n22so2376596wmc.2 for ; Fri, 05 Mar 2021 11:08:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=634De0VmcZftqA0EsYtSRssGeJ1lMakbJs+e7qthPxU=; b=TMMbvn7IqgceEw2QLrz/yNpja+KaG2awcVxCZmB+rZzYcqBx48C0uwMXq3khyYXqRt xKAAz9ZLpTwSxDnmTkNFTe1i/o0SYVRf2gvEFrdg3IPR4+RyCYS+We09VE/IDeBwM6hd 3+skIwth+kCHTWRXZzuXHmPPmzhaeNA71mBHKZKuCW6FH19zRRTEYfbmuUB10plgf03V CZQ+40cPmAvVaEIiLcfuSFapUIMJTIFj8/TkcqNM7DWxXyMx4nOaIRlNXeiho5WnAczk IaagPjARzZPyvoQv1i6oBUwtMOiUaek8JBbGUwB62vjJDzuB6HoXvz9OE89X/Qau9neT 6mnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=634De0VmcZftqA0EsYtSRssGeJ1lMakbJs+e7qthPxU=; b=PGO80/fpyutuR5uvIwInMteUth1Hcgv7t8Z03dGuqxJUYQPOMStXBvjIN9dbx7FSG9 xrgeHx8ZVyLDE+PeydVhfDGrRzV1n5BEIxu2EpgqXJhFTMkpdmW8WWQ8SP8I/fYwT1Eb 2Y/LO57wJivpEQdNsrAwUbptnwZkZeingLeet8usd3sk88qcobJ7yrhZL9f49POxHCVE BOBRwNhImSalwcddpAuhKhY7Mm7bpeS2CYGHc+aCcXr18o4s646X+TUyJCjU0E0l95mZ VpCy7zv8ICl9WKQrmmEDH+DFhtdlh5mbUvuuMptF21ojz5Qx8HerY0LmqgbAcAKjjOZf fr1Q== X-Gm-Message-State: AOAM530scuJl/qqwBbgYioqBKJJiZGJXCgygQKdXTPw7rqf94ikByD5D j5LMuvEucpyxcl6QV0JzD2pLow== X-Received: by 2002:a7b:c1c9:: with SMTP id a9mr9945055wmj.145.1614971304570; Fri, 05 Mar 2021 11:08:24 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:55da:a740:2edb:1c7e]) by smtp.gmail.com with ESMTPSA id c11sm5355437wrs.28.2021.03.05.11.08.23 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Mar 2021 11:08:24 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v3 4/6] mhi: pci_generic: No-Op for device_wake operations Date: Fri, 5 Mar 2021 20:16:46 +0100 Message-Id: <1614971808-22156-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> References: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The wake_db register presence is highly speculative and can fuze MHI devices. Indeed, currently the wake_db register address is defined at entry 127 of the 'Channel doorbell array', thus writing to this address is equivalent to ringing the doorbell for channel 127, causing trouble with some devics (e.g. SDX24 based modems) that get an unexpected channel 127 doorbell interrupt. This change fixes that issue by setting wake get/put as no-op for pci_generic devices. The wake device sideband mechanism seems really specific to each device, and is AFAIK not defined by the MHI spec. It also removes zeroing initialization of wake_db register during MMIO initialization, the register being set via wake_get/put accessors few cycles later during M0 transition. Signed-off-by: Loic Poulain --- v2: reword commit message v3: no change drivers/bus/mhi/core/init.c | 2 -- drivers/bus/mhi/pci_generic.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 2159dbc..32eb90f 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -510,8 +510,6 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) /* Setup wake db */ mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); - mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); - mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); mhi_cntrl->wake_set = false; /* Setup channel db address for each channel in tre_ring */ diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c274e65..4685a83 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -312,6 +312,21 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, } } +static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) +{ + /* no-op */ +} + +static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) +{ + /* no-op */ +} + +static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) +{ + /* no-op */ +} + static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) { struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); @@ -515,6 +530,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mhi_cntrl->status_cb = mhi_pci_status_cb; mhi_cntrl->runtime_get = mhi_pci_runtime_get; mhi_cntrl->runtime_put = mhi_pci_runtime_put; + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) From patchwork Fri Mar 5 19:16:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393586 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp690480jai; Fri, 5 Mar 2021 11:09:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJww5OCFotcNsnh9UxN1/5wIFRnfrh0zRom/55V1SltSbQ15rkN/ZPJAShyNzvOJeOSLmf8t X-Received: by 2002:a05:6402:26ce:: with SMTP id x14mr10435355edd.359.1614971349094; Fri, 05 Mar 2021 11:09:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614971349; cv=none; d=google.com; s=arc-20160816; b=nXTB4byy96iy/B73Oy1nhTeMmUrlzHT4dRdxfwpq0UYHdKAJuCqfpoA9YjkdfDSS3h jyQk8Ifr4zom87NPbiH4GlULXqR5qdsZpDTc+2RA08NSq9kMrsJy3F0iYYAAg0zufkVj zQ9cCskIyhw46aA9+BQ7Eb+LFDs2WrTvwaXt+3Y1tN8cOFGtMTLuhqAIC2gQ7vBMy6hq eKSgifZFu9MyOhx/aGxnJlb4uF93l32dY5KmS1miwHsYxZLm1oseEwTBbGNc9755Tc2y 0iI6mItI+DYSzvlWP66XDJ5nyBnAuPAvbL7l+wHngB7zKmpRxv9OEX+IzwEb/fdjXdir iUEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=faIAP9pFaeyTPsM83fpq3GbW4v6kwIcv7zej+9Y4PP0=; b=DzZBicaOW1seaD3j6vzY8d3x3vz6K9T6El50otyrPBDrkzD5UrSg8rKtjvLbZ9Xxpb LS7b6A58VZ1T9rEMTZyC+1cmHZ+vojtdoQhLvqGarHPOOiVGv0rrDpQLhW23pxv33K8B 8W3OGldaFxBisUcHUvRNc+4vgPcbolsKiFdUhASXotic75cmek62I3QNCrNG2gDb9yCN bGAJ2gGb6SK+7mC1HZXo1K7wTr7VNizkqZg0frenyweDBXVRTVhQ1kEdqaSbst52JLGu OHunTbICphb+/JDWXkd1ovymbSZJpasoxS4vfTtZdnTJWykM+R+lf1WDTlyofeJRbe+K BkBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qef7gdpT; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ml22si1089671ejb.629.2021.03.05.11.09.08; Fri, 05 Mar 2021 11:09:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qef7gdpT; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229597AbhCETIg (ORCPT + 16 others); Fri, 5 Mar 2021 14:08:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230112AbhCETI1 (ORCPT ); Fri, 5 Mar 2021 14:08:27 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E41E3C061574 for ; Fri, 5 Mar 2021 11:08:26 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id h98so3201345wrh.11 for ; Fri, 05 Mar 2021 11:08:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=faIAP9pFaeyTPsM83fpq3GbW4v6kwIcv7zej+9Y4PP0=; b=qef7gdpTjh4V3ABvN98nFLaz40lUaTKPndB603NyEChTzqYTNiVEwGWWyl8ueJ1qWO i3wCaLGHJ+PEzpJb/5sn36zAlfJZZ5XDWKDjGJFkqpcVd6ApZXxdfJh17T2mR45Cxpa8 9TPouScARKnA4CCRBuaajTcBbxsswvzv6kwjfTQAlQIseB2mY4D9J9xvvjzt9VztVOc7 1ATQLiYuE4xvzoIZpwL6RnNTVKi6/W17YdCHgoskcNB6Og5bfFCqszVzkAXNVaZ9s7YY d86vpuITNA90JpL6Yh0wpM4MuOETBI5YX+I0mi2SAwGKK+bmxRqqg2ymyOc4WGh0MJZi LdPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=faIAP9pFaeyTPsM83fpq3GbW4v6kwIcv7zej+9Y4PP0=; b=qL1W4dJBxFlEo7l9YiOJReW6lm+Qg5l5/cp/hKv5vrldr04tGYeOtkIO3vjLwhIXTY 6kT7ZAv7EInHVflXskcdVucciU3wpagn7bhw4GyJR3ej4VU0sfkO6q01An7rZaMb1lhD U7lw8OIoyKTspKOpBTSBHYzCQKmFDMMxA2xzMgfVdpxFgggVw2tpF6ABFdwn0OOQ7oaz twIFu+snzxMW8CIe2ETNFogiPTZUNM6EjHYOH2etdRx9pLWodPxkB5P0/oyjRIrEmG9D mbwIpLA4v0EGe0aofGpzVM4SKXaXYJ5V+5DMjlLrdt9+FsJjpodwNFXhVl+Wj/VnuDeb WYow== X-Gm-Message-State: AOAM532Ke9GeWf+zddk0VHbUupUl2MR7Mn5k7E6uTihbo55v/n3m4HgP j2reCq5Bt96hQWDrnMCVdYjnKg== X-Received: by 2002:a5d:6cab:: with SMTP id a11mr10858843wra.419.1614971305647; Fri, 05 Mar 2021 11:08:25 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:55da:a740:2edb:1c7e]) by smtp.gmail.com with ESMTPSA id c11sm5355437wrs.28.2021.03.05.11.08.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Mar 2021 11:08:25 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v3 5/6] mhi: pci_generic: Use generic PCI power management Date: Fri, 5 Mar 2021 20:16:47 +0100 Message-Id: <1614971808-22156-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> References: <1614971808-22156-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The PCI core can take care of proper PCI suspend/resume operations, but this is discarded when the driver saves PCI state by its own. This currently prevents the PCI core to enable PME (for modem initiated D3 exit) which is requested for proper runtime pm support. This change deletes explicit PCI state-saving and state-set from suspend callback, letting the PCI doing the appropriate work. Signed-off-by: Loic Poulain --- v2: no change v3: no change drivers/bus/mhi/pci_generic.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 4685a83..4ab0aa8 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -544,9 +544,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_set_drvdata(pdev, mhi_pdev); - /* Have stored pci confspace at hand for restore in sudden PCI error */ + /* Have stored pci confspace at hand for restore in sudden PCI error. + * cache the state locally and discard the PCI core one. + */ pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_load_saved_state(pdev, NULL); pci_enable_pcie_error_reporting(pdev); @@ -717,10 +720,8 @@ static int __maybe_unused mhi_pci_suspend(struct device *dev) /* Transition to M3 state */ mhi_pm_suspend(mhi_cntrl); - pci_save_state(pdev); pci_disable_device(pdev); pci_wake_from_d3(pdev, true); - pci_set_power_state(pdev, PCI_D3hot); return 0; } @@ -732,14 +733,13 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; int err; - pci_set_power_state(pdev, PCI_D0); - pci_restore_state(pdev); - pci_set_master(pdev); - err = pci_enable_device(pdev); if (err) goto err_recovery; + pci_set_master(pdev); + pci_wake_from_d3(pdev, false); + /* Exit M3, transition to M0 state */ err = mhi_pm_resume(mhi_cntrl); if (err) { From patchwork Fri Mar 5 19:16:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 393585 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp690469jai; Fri, 5 Mar 2021 11:09:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJxhJt4x/Hm1c3yTbuPBf/0R5IlOLdw+7O5ihlbIHiscEnEcDN0Db6TAyev0WTzK73a3A3F7 X-Received: by 2002:a05:6402:1d92:: with SMTP id dk18mr10474854edb.161.1614971348400; Fri, 05 Mar 2021 11:09:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614971348; cv=none; d=google.com; s=arc-20160816; b=bQwNA264DQ/n+uuCzOQXatM7jd3VAScQ/JuWnKea9h3WVYgfr10nH0Wf9QZAUvUZqP vD57zNuad7lS/RMr65bBFQKQSOEPuFKPmLlUuhyjSc851L8CTJmSQa5P27ROW1hzpgJ7 RapuW0fYmAxpsz4Rt68+fn78yTyxl0ewx99kifA+lkxcScGRX6Pw4xAATXb2fceF1Jmq M7S1SdgIDu0aGTT70aadF8gh4Gw/GpbcH5xA7hCM6sx6K7unDGiBhRm8qHG+kZGK3rZg 3hSv5ZxW6VQX/Y85jwhVYk+P0IvC62v67BFsZjxbaFstcZGCAplCaqIOEjrTW6mnrEDJ 0FZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Hyo/CJdck6kg1EG9ppCml8u7zKY1PWwyhVY28ETSFEA=; b=JedEAw+NjkXU02RudD3fXsEYlqlJGxlamlcy22KlxUid6zhR/pEfV7bzqemhK4Opj6 0Kn2Yv/UouqKCgF2vF+RMZaaIPF93Y7x8pvl45aDU/ssmICCG07/mmOPzf96GEl0l3If ikJdJBFNpPOi6xBfmIWhwAQHFFMa48ABmz6s7hd3zIBoslsuu9oCyElOCd+ISHa31l0a XxKhqINZxtXpC4E5TdMHVH/j2aSIjhns6mFu/3km9Pg0f2HyJydLOtv8pRn6qUKTsfUH SdocLaI12tas9YP4TY/K3N/hSoGnj7qYyKY+5NN7rJN6D5wgCCh8GWgfVYtCtlfw+Q+H J0Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z7ZV1iqa; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In that mode, all MHI operations are suspended and the PCI device can be safely put into PCI D3 state. The device is then resumed from D3/M3 either because of host initiated MHI operation (e.g. buffer TX) or because the device (modem) has triggered wake-up via PME feature (e.g. on incoming data). Same procedures can be used for system wide or runtime suspend/resume. Signed-off-by: Loic Poulain --- v2: replace force_runtime_suspend/resume via local function to ensure device is always resumed during system resume whatever its runtime pm state. v3: - remove extra mark_last_busy - move mark_last_busy after mhi_pm_suspend - remove terminal semicolon from print drivers/bus/mhi/pci_generic.c | 95 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 4ab0aa8..92ab9bb 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -274,6 +275,7 @@ MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); enum mhi_pci_device_status { MHI_PCI_DEV_STARTED, + MHI_PCI_DEV_SUSPENDED, }; struct mhi_pci_device { @@ -306,6 +308,10 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, case MHI_CB_FATAL_ERROR: case MHI_CB_SYS_ERROR: dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); + pm_runtime_forbid(&pdev->dev); + break; + case MHI_CB_EE_MISSION_MODE: + pm_runtime_allow(&pdev->dev); break; default: break; @@ -427,13 +433,19 @@ static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) { - /* no PM for now */ - return 0; + /* The runtime_get() MHI callback means: + * Do whatever is requested to leave M3. + */ + return pm_runtime_get(mhi_cntrl->cntrl_dev); } static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) { - /* no PM for now */ + /* The runtime_put() MHI callback means: + * Device can be moved in M3 state. + */ + pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); + pm_runtime_put(mhi_cntrl->cntrl_dev); } static void mhi_pci_recovery_work(struct work_struct *work) @@ -447,6 +459,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); del_timer(&mhi_pdev->health_check_timer); + pm_runtime_forbid(&pdev->dev); /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -454,7 +467,6 @@ static void mhi_pci_recovery_work(struct work_struct *work) mhi_unprepare_after_power_down(mhi_cntrl); } - /* Check if we can recover without full reset */ pci_set_power_state(pdev, PCI_D0); pci_load_saved_state(pdev, mhi_pdev->pci_state); pci_restore_state(pdev); @@ -488,6 +500,10 @@ static void health_check(struct timer_list *t) struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return; + if (!mhi_pci_is_alive(mhi_cntrl)) { dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); queue_work(system_long_wq, &mhi_pdev->recovery_work); @@ -575,6 +591,14 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) /* start health check */ mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + /* Only allow runtime-suspend if PME capable (for wakeup) */ + if (pci_pme_capable(pdev, PCI_D3hot)) { + pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); + } + return 0; err_unprepare: @@ -598,6 +622,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) mhi_unprepare_after_power_down(mhi_cntrl); } + /* balancing probe put_noidle */ + if (pci_pme_capable(pdev, PCI_D3hot)) + pm_runtime_get_noresume(&pdev->dev); + mhi_unregister_controller(mhi_cntrl); } @@ -708,31 +736,48 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; -static int __maybe_unused mhi_pci_suspend(struct device *dev) +static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return 0; del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + mhi_cntrl->ee != MHI_EE_AMSS) + goto pci_suspend; /* Nothing to do at MHI level */ + /* Transition to M3 state */ - mhi_pm_suspend(mhi_cntrl); + err = mhi_pm_suspend(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to suspend device: %d\n", err); + clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); + return -EBUSY; + } +pci_suspend: pci_disable_device(pdev); pci_wake_from_d3(pdev, true); return 0; } -static int __maybe_unused mhi_pci_resume(struct device *dev) +static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; int err; + if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) + return 0; + err = pci_enable_device(pdev); if (err) goto err_recovery; @@ -740,6 +785,10 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) pci_set_master(pdev); pci_wake_from_d3(pdev, false); + if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || + mhi_cntrl->ee != MHI_EE_AMSS) + return 0; /* Nothing to do at MHI level */ + /* Exit M3, transition to M0 state */ err = mhi_pm_resume(mhi_cntrl); if (err) { @@ -750,16 +799,44 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) /* Resume health check */ mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + /* It can be a remote wakeup (no mhi runtime_get), update access time */ + pm_runtime_mark_last_busy(dev); + return 0; err_recovery: - /* The device may have loose power or crashed, try recovering it */ + /* Do not fail to not mess up our PCI device state, the device likely + * lost power (d3cold) and we simply need to reset it from the recovery + * procedure, trigger the recovery asynchronously to prevent system + * suspend exit delaying. + */ queue_work(system_long_wq, &mhi_pdev->recovery_work); + pm_runtime_mark_last_busy(dev); - return err; + return 0; +} + +static int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + pm_runtime_disable(dev); + return mhi_pci_runtime_suspend(dev); +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + int ret; + + /* Depending the platform, device may have lost power (d3cold), we need + * to resume it now to check its state and recover when necessary. + */ + ret = mhi_pci_runtime_resume(dev); + pm_runtime_enable(dev); + + return ret; } static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) };