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[209.51.188.17]) by mx.google.com with ESMTPS id x9si2439617ion.76.2021.03.05.05.57.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Mar 2021 05:57:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jkanQvyI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIAxb-0002HD-7w for patch@linaro.org; Fri, 05 Mar 2021 08:57:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIAv1-0007gt-PU for qemu-devel@nongnu.org; Fri, 05 Mar 2021 08:55:03 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:46774) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIAuw-00079h-Ox for qemu-devel@nongnu.org; Fri, 05 Mar 2021 08:55:03 -0500 Received: by mail-wr1-x433.google.com with SMTP id a18so2146441wrc.13 for ; Fri, 05 Mar 2021 05:54:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MupsZ87lXP1Mr2svUts96dM3pR11RQaXebcgIZ/+VwI=; b=jkanQvyIQym4YGOj+5qMM3YlHiN7MrXjcgJB+knzRGOf2SYAlcg85dzRk82iS6XIay TkfjYjzz/MV+iyI8ttxMxWPGdfDdtiDshPqzWmGKTyYsHvfwmuH+9mgefX2lLho8Dtfq hnjEhVd1XeXaAQmzH+NtKChhKQKeRDa139Kw2zoiWkz6aBC1MjPtYyighgHS4YEIzHfy 7a5/5TcIXW5dJJAaNU37bQbN4PKlPA5JWBDYiCh61Er7UfaJfj3PCzBhxVHpa9wj/orV blKJY6klAXywlJHA+/aMz21dUKsCogtwMY+9Qy48yTdLNmZK/ekpdOVjbEuOzfAgvoFm /+8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MupsZ87lXP1Mr2svUts96dM3pR11RQaXebcgIZ/+VwI=; b=ln2DSnHd4awAGyv6aenBKmAUBneYofXDHYwtGmw/wwd/cPfoiwNBOw00ukkZASBiAl LzBiofCIGNwmqkusVBLha6uE4ZgcokBZ6J6sa+oBVbj+5rQ/tbq/x7avFdjo35KX7WlD 9zQBO87zBPhAN7EqYnM34nYGf+ab48FpqG9UMyXpDk5M9moy52K1O58WMoDn8csoHAoW Fe3+ujRqMVcH9dWyl5xsDJlOBPF3LAq05xey4mi9MioW2qBayyjN4dIVYq382in9dzGd DFYLpHwYLq3hvWserntOdNic0wmPeJAvItkoSLv5UL9NYOCHzXGQPD8D3idM/C+RXvWk q4xg== X-Gm-Message-State: AOAM533Ox8lGBpQHU2ZP7vzP3omfNZBcmjvnQy2AmfsTAnBEMPPSeHAc 6pxQgrVlbnrxL4+fi7oFmHUjYw== X-Received: by 2002:adf:a406:: with SMTP id d6mr9580631wra.141.1614952497417; Fri, 05 Mar 2021 05:54:57 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p6sm4516932wru.2.2021.03.05.05.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 05:54:54 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 102031FF87; Fri, 5 Mar 2021 13:54:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v1 1/3] semihosting: Move include/hw/semihosting/ -> include/semihosting/ Date: Fri, 5 Mar 2021 13:54:49 +0000 Message-Id: <20210305135451.15427-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210305135451.15427-1-alex.bennee@linaro.org> References: <20210305135451.15427-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Peter Maydell , Aleksandar Rikalo , "open list:RISC-V TCG CPUs" , Sagar Karandikar , =?utf-8?q?Alex_Benn=C3=A9e?= , Chris Wulff , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , Laurent Vivier , Max Filippov , Michael Walle , "open list:ARM TCG CPUs" , Palmer Dabbelt , Bastian Koppelmann , Paolo Bonzini , Alistair Francis , Guan Xuetao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé We want to move the semihosting code out of hw/ in the next patch. This patch contains the mechanical steps, created using: $ git mv include/hw/semihosting/ include/ $ sed -i s,hw/semihosting,semihosting, $(git grep -l hw/semihosting) Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Message-Id: <20210226131356.3964782-2-f4bug@amsat.org> --- include/{hw => }/semihosting/console.h | 0 include/{hw => }/semihosting/semihost.h | 0 gdbstub.c | 2 +- hw/mips/malta.c | 2 +- hw/semihosting/arm-compat-semi.c | 6 +++--- hw/semihosting/config.c | 2 +- hw/semihosting/console.c | 4 ++-- linux-user/aarch64/cpu_loop.c | 2 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- linux-user/semihost.c | 2 +- softmmu/vl.c | 2 +- stubs/semihost.c | 2 +- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 4 ++-- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- target/lm32/helper.c | 2 +- target/m68k/op_helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/mips-semi.c | 4 ++-- target/mips/translate.c | 2 +- target/nios2/helper.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/unicore32/helper.c | 2 +- target/xtensa/translate.c | 2 +- target/xtensa/xtensa-semi.c | 2 +- MAINTAINERS | 2 +- 28 files changed, 32 insertions(+), 32 deletions(-) rename include/{hw => }/semihosting/console.h (100%) rename include/{hw => }/semihosting/semihost.h (100%) -- 2.20.1 diff --git a/include/hw/semihosting/console.h b/include/semihosting/console.h similarity index 100% rename from include/hw/semihosting/console.h rename to include/semihosting/console.h diff --git a/include/hw/semihosting/semihost.h b/include/semihosting/semihost.h similarity index 100% rename from include/hw/semihosting/semihost.h rename to include/semihosting/semihost.h diff --git a/gdbstub.c b/gdbstub.c index 3ee40479b6..e51e33cc70 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -49,7 +49,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "exec/exec-all.h" #include "sysemu/replay.h" diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9afc0b427b..26e7b1bd9f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -58,7 +58,7 @@ #include "qemu/error-report.h" #include "hw/misc/empty_slot.h" #include "sysemu/kvm.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "hw/mips/cps.h" #include "hw/qdev-clock.h" diff --git a/hw/semihosting/arm-compat-semi.c b/hw/semihosting/arm-compat-semi.c index 23c6e3edcb..94950b6c56 100644 --- a/hw/semihosting/arm-compat-semi.c +++ b/hw/semihosting/arm-compat-semi.c @@ -34,9 +34,9 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/semihosting/semihost.h" -#include "hw/semihosting/console.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/semihost.h" +#include "semihosting/console.h" +#include "semihosting/common-semi.h" #include "qemu/log.h" #include "qemu/timer.h" #ifdef CONFIG_USER_ONLY diff --git a/hw/semihosting/config.c b/hw/semihosting/config.c index 9807f10cb0..3548e0f627 100644 --- a/hw/semihosting/config.c +++ b/hw/semihosting/config.c @@ -22,7 +22,7 @@ #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/error-report.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "chardev/char.h" #include "sysemu/sysemu.h" diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c index 9b4fee9260..c9ebd6fdd0 100644 --- a/hw/semihosting/console.c +++ b/hw/semihosting/console.c @@ -17,8 +17,8 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/semihosting/semihost.h" -#include "hw/semihosting/console.h" +#include "semihosting/semihost.h" +#include "semihosting/console.h" #include "exec/gdbstub.h" #include "exec/exec-all.h" #include "qemu/log.h" diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 7c42f65706..ee72a1c20f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,7 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/common-semi.h" #include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index cadfb7fa43..989d03cd89 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,7 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 9665dabb09..6767f941e8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,7 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { diff --git a/linux-user/semihost.c b/linux-user/semihost.c index c0015ee7f6..82013b8b48 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/semihosting/console.h" +#include "semihosting/console.h" #include "qemu.h" #include diff --git a/softmmu/vl.c b/softmmu/vl.c index 10bd8a10a3..ac06dfbae0 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -108,7 +108,7 @@ #include "qapi/opts-visitor.h" #include "qapi/clone-visitor.h" #include "qom/object_interfaces.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "crypto/init.h" #include "sysemu/replay.h" #include "qapi/qapi-events-run-state.h" diff --git a/stubs/semihost.c b/stubs/semihost.c index 1d8b37f7b2..1b30f38b03 100644 --- a/stubs/semihost.c +++ b/stubs/semihost.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include "qemu/option.h" #include "qemu/error-report.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "sysemu/sysemu.h" /* Empty config */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e1a3b9421..d763f376c6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -22,7 +22,7 @@ #include "exec/exec-all.h" #include /* For crc32 */ #include "hw/irq.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" @@ -34,7 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 731c435c00..d63ae465e1 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -21,7 +21,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include /* For crc32 */ -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "qemu/range.h" @@ -31,7 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b23a8975d5..6d002e2c63 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -28,7 +28,7 @@ #include "internals.h" #include "qemu/host-utils.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "exec/gen-icount.h" #include "exec/helper-proto.h" diff --git a/target/arm/translate.c b/target/arm/translate.c index 1653cca1aa..62b1c2081b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -29,7 +29,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "arm_ldst.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 7c52ae76d6..01cc3c53a5 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/host-utils.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "exec/log.h" bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 202498deb5..730cdf7744 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -21,7 +21,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #if defined(CONFIG_USER_ONLY) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295..bd4dca571f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -31,7 +31,7 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" diff --git a/target/mips/mips-semi.c b/target/mips/mips-semi.c index 898251aa02..6de60fa6dd 100644 --- a/target/mips/mips-semi.c +++ b/target/mips/mips-semi.c @@ -22,8 +22,8 @@ #include "qemu/log.h" #include "exec/helper-proto.h" #include "exec/softmmu-semi.h" -#include "hw/semihosting/semihost.h" -#include "hw/semihosting/console.h" +#include "semihosting/semihost.h" +#include "semihosting/console.h" typedef enum UHIOp { UHI_exit = 1, diff --git a/target/mips/translate.c b/target/mips/translate.c index 70891c37cd..0b6d82d228 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29,7 +29,7 @@ #include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "target/mips/trace.h" #include "trace-tcg.h" diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 57c97bde3c..53be8398e9 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -26,7 +26,7 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #if defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2f43939fb6..83a6bcfad0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,7 +24,7 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" -#include "hw/semihosting/common-semi.h" +#include "semihosting/common-semi.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index 54c26871fe..704393c27f 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -14,7 +14,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "hw/semihosting/console.h" +#include "semihosting/console.h" #undef DEBUG_UC32 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 944a157747..0ae4efc48a 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -37,7 +37,7 @@ #include "qemu/log.h" #include "qemu/qemu-print.h" #include "exec/cpu_ldst.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "exec/translator.h" #include "exec/helper-proto.h" diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 25f57a6500..79f2b043f2 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -29,7 +29,7 @@ #include "cpu.h" #include "chardev/char-fe.h" #include "exec/helper-proto.h" -#include "hw/semihosting/semihost.h" +#include "semihosting/semihost.h" #include "qapi/error.h" #include "qemu/log.h" diff --git a/MAINTAINERS b/MAINTAINERS index 1443278059..37ddf90669 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3227,7 +3227,7 @@ Semihosting M: Alex Bennée S: Maintained F: hw/semihosting/ -F: include/hw/semihosting/ +F: include/semihosting/ Multi-process QEMU M: Elena Ufimtseva From patchwork Fri Mar 5 13:54:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 393516 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp445822jai; Fri, 5 Mar 2021 05:55:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJyQ+fB7vHRyIsJUlVMB+gWcJJRI/OZxRyNqvVXWopIEZ8bTIOSuyxGqlqvxsTHUZqbgPMFX X-Received: by 2002:a92:cda6:: with SMTP id g6mr8878081ild.274.1614952511901; Fri, 05 Mar 2021 05:55:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614952511; cv=none; d=google.com; s=arc-20160816; b=EcSubIU0bUC0qZRJ2BrW3GlxNCWSy99Ow8ApGq3mYjBfDpA2+ah+ywDzgPGm52mh/j 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Semihosting is also used by user emulation. As a generic feature, move it out of hw/ directory. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Message-Id: <20210226131356.3964782-3-f4bug@amsat.org> --- meson.build | 1 + {hw/semihosting => semihosting}/common-semi.h | 0 {hw/semihosting => semihosting}/arm-compat-semi.c | 0 {hw/semihosting => semihosting}/config.c | 0 {hw/semihosting => semihosting}/console.c | 0 Kconfig | 1 + MAINTAINERS | 2 +- hw/Kconfig | 1 - hw/meson.build | 1 - {hw/semihosting => semihosting}/Kconfig | 0 {hw/semihosting => semihosting}/meson.build | 0 11 files changed, 3 insertions(+), 3 deletions(-) rename {hw/semihosting => semihosting}/common-semi.h (100%) rename {hw/semihosting => semihosting}/arm-compat-semi.c (100%) rename {hw/semihosting => semihosting}/config.c (100%) rename {hw/semihosting => semihosting}/console.c (100%) rename {hw/semihosting => semihosting}/Kconfig (100%) rename {hw/semihosting => semihosting}/meson.build (100%) -- 2.20.1 diff --git a/meson.build b/meson.build index 07bc23129a..3578692315 100644 --- a/meson.build +++ b/meson.build @@ -1939,6 +1939,7 @@ subdir('migration') subdir('monitor') subdir('net') subdir('replay') +subdir('semihosting') subdir('hw') subdir('accel') subdir('plugins') diff --git a/hw/semihosting/common-semi.h b/semihosting/common-semi.h similarity index 100% rename from hw/semihosting/common-semi.h rename to semihosting/common-semi.h diff --git a/hw/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c similarity index 100% rename from hw/semihosting/arm-compat-semi.c rename to semihosting/arm-compat-semi.c diff --git a/hw/semihosting/config.c b/semihosting/config.c similarity index 100% rename from hw/semihosting/config.c rename to semihosting/config.c diff --git a/hw/semihosting/console.c b/semihosting/console.c similarity index 100% rename from hw/semihosting/console.c rename to semihosting/console.c diff --git a/Kconfig b/Kconfig index bf694c42af..d52ebd839b 100644 --- a/Kconfig +++ b/Kconfig @@ -2,3 +2,4 @@ source Kconfig.host source backends/Kconfig source accel/Kconfig source hw/Kconfig +source semihosting/Kconfig diff --git a/MAINTAINERS b/MAINTAINERS index 37ddf90669..90118a537a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3226,7 +3226,7 @@ F: qapi/rdma.json Semihosting M: Alex Bennée S: Maintained -F: hw/semihosting/ +F: semihosting/ F: include/semihosting/ Multi-process QEMU diff --git a/hw/Kconfig b/hw/Kconfig index 8ea26479c4..ff40bd3f7b 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -31,7 +31,6 @@ source remote/Kconfig source rtc/Kconfig source scsi/Kconfig source sd/Kconfig -source semihosting/Kconfig source smbios/Kconfig source ssi/Kconfig source timer/Kconfig diff --git a/hw/meson.build b/hw/meson.build index e615d72d4d..8ba79b1a52 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -30,7 +30,6 @@ subdir('rdma') subdir('rtc') subdir('scsi') subdir('sd') -subdir('semihosting') subdir('smbios') subdir('ssi') subdir('timer') diff --git a/hw/semihosting/Kconfig b/semihosting/Kconfig similarity index 100% rename from hw/semihosting/Kconfig rename to semihosting/Kconfig diff --git a/hw/semihosting/meson.build b/semihosting/meson.build similarity index 100% rename from hw/semihosting/meson.build rename to semihosting/meson.build From patchwork Fri Mar 5 13:54:51 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id w12si2283194ilo.156.2021.03.05.05.55.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Mar 2021 05:55:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jWWRCWei; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIAvD-0007gK-LH for patch@linaro.org; Fri, 05 Mar 2021 08:55:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIAuz-0007bs-1i for qemu-devel@nongnu.org; Fri, 05 Mar 2021 08:55:01 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55302) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIAuw-00079I-Gh for qemu-devel@nongnu.org; Fri, 05 Mar 2021 08:55:00 -0500 Received: by mail-wm1-x32c.google.com with SMTP id w7so1515311wmb.5 for ; Fri, 05 Mar 2021 05:54:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qs3X4Vrdn0QMj8+l/h+TrHu30GN7onIaZQm+5Oo555k=; b=jWWRCWeikH/1ic62WGfEJYHM+DuvzknFxwhVseBkLuusYU+eEMHt+kbDQ+vZoXG1hG E480h4jv12fQN59oCGAF73lhDlxTMIJaXhtbXn49+cfwzPYrmraAFWHyW9L5VoJTbnxU otz7In9ozoO59KoBLWuZt0b+CdjAup7gfQWOrZRgjYrfbna66gYjTyIC5JWi/cJR95wB 622C65aTMddClNfTku9igojnCks6U54F43TxxYs5IWKTfZyZWn9lFVYlFo+ZPqaYH3GK pF7W+Inv1nJtJdjI+9ABrsTP/8GVXfPLkt+8/nVsPQyVnK3sBBA4NY30kOfkB+XZ29bx lv4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qs3X4Vrdn0QMj8+l/h+TrHu30GN7onIaZQm+5Oo555k=; b=lvgvzhG1ouEafjA8sOar9qGPzHgVT0YRtIGTcAa7nMhqJ2sQQhJKV2D4+zf8SFljL/ evJWd6+BXbBLk6QK9NvOrDBSPPD8Ffw0IN+U78xnInBfjl1B+whJZPVal/bxAmgKN0o6 dv4/ZpC/Vs2jHqwNU0Dd1pnalVpP+H2Kbh50or6imgViT6jvl+xdoNzHkhglXYIoNeBj D2VeZfxE8BVmlJcNeiNzm0FUjfr7Nc1tqq9fcgypuulRa7SF4xII2vwVdrdyYR+hshjk EUOoGXwY7dvWYZNbexVApLzMbVpAsupekqcfkPDewbHAqnpfaU48q2oyIXN+m4KSVd3H Jzow== X-Gm-Message-State: AOAM533UMpTbCRRHWj5cZTN88rlQ5MwQSUpBPFomsIrqtUWbvLcHVxBD NNOHW+U105t9uEztl3j0N3ZO4A== X-Received: by 2002:a1c:730f:: with SMTP id d15mr8912110wmb.135.1614952496967; Fri, 05 Mar 2021 05:54:56 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m2sm4446648wml.34.2021.03.05.05.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 05:54:54 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 496E51FF8F; Fri, 5 Mar 2021 13:54:52 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO Date: Fri, 5 Mar 2021 13:54:51 +0000 Message-Id: <20210305135451.15427-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210305135451.15427-1-alex.bennee@linaro.org> References: <20210305135451.15427-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bug 1915925 <1915925@bugs.launchpad.net>, Keith Packard , "open list:ARM TCG CPUs" , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I'm not sure this every worked properly and it's certainly not exercised by check-tcg or Peter's semihosting tests. Hoist it into it's own helper function and attempt to validate the results in the linux-user semihosting test at the least. Bug: https://bugs.launchpad.net/bugs/1915925 Cc: Bug 1915925 <1915925@bugs.launchpad.net> Cc: Keith Packard Signed-off-by: Alex Bennée --- tests/tcg/arm/semicall.h | 1 + semihosting/arm-compat-semi.c | 129 +++++++++++++++++++--------------- tests/tcg/arm/semihosting.c | 34 ++++++++- 3 files changed, 107 insertions(+), 57 deletions(-) -- 2.20.1 diff --git a/tests/tcg/arm/semicall.h b/tests/tcg/arm/semicall.h index d4f6818192..676a542be5 100644 --- a/tests/tcg/arm/semicall.h +++ b/tests/tcg/arm/semicall.h @@ -9,6 +9,7 @@ #define SYS_WRITE0 0x04 #define SYS_READC 0x07 +#define SYS_HEAPINFO 0x16 #define SYS_REPORTEXC 0x18 uintptr_t __semi_call(uintptr_t type, uintptr_t arg0) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 94950b6c56..a8fdbceb5f 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -822,6 +822,78 @@ static const GuestFDFunctions guestfd_fns[] = { put_user_utl(val, args + (n) * sizeof(target_ulong)) #endif +/* + * SYS_HEAPINFO is a little weird: "On entry, the PARAMETER REGISTER + * contains the address of a pointer to a four-field data block" which + * we then fill in. The PARAMETER REGISTER is unchanged. + */ + +struct HeapInfo { + target_ulong heap_base; + target_ulong heap_limit; + target_ulong stack_base; + target_ulong stack_limit; +}; + +static bool do_heapinfo(CPUState *cs, target_long arg0) +{ + target_ulong limit; + struct HeapInfo info = {}; +#ifdef CONFIG_USER_ONLY + TaskState *ts = cs->opaque; +#else + target_ulong rambase = common_semi_rambase(cs); +#endif + +#ifdef CONFIG_USER_ONLY + /* + * Some C libraries assume the heap immediately follows .bss, so + * allocate it using sbrk. + */ + if (!ts->heap_limit) { + abi_ulong ret; + + ts->heap_base = do_brk(0); + limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE; + /* Try a big heap, and reduce the size if that fails. */ + for (;;) { + ret = do_brk(limit); + if (ret >= limit) { + break; + } + limit = (ts->heap_base >> 1) + (limit >> 1); + } + ts->heap_limit = limit; + } + + info.heap_base = ts->heap_base; + info.heap_limit = ts->heap_limit; + info.stack_base = ts->stack_base; + info.stack_limit = 0; /* Stack limit. */ + + if (copy_to_user(arg0, &info, sizeof(info))) { + errno = EFAULT; + return set_swi_errno(cs, -1); + } +#else + limit = current_machine->ram_size; + /* TODO: Make this use the limit of the loaded application. */ + info.heap_base = rambase + limit / 2; + info.heap_limit = rambase + limit; + info.stack_base = rambase + limit; /* Stack base */ + info.stack_limit = rambase; /* Stack limit. */ + + if (cpu_memory_rw_debug(cs, arg0, &info, sizeof(info), true)) { + errno = EFAULT; + return set_swi_errno(cs, -1); + } + +#endif + + return 0; +} + + /* * Do a semihosting call. * @@ -1184,63 +1256,8 @@ target_ulong do_common_semihosting(CPUState *cs) } case TARGET_SYS_HEAPINFO: { - target_ulong retvals[4]; - target_ulong limit; - int i; -#ifdef CONFIG_USER_ONLY - TaskState *ts = cs->opaque; -#else - target_ulong rambase = common_semi_rambase(cs); -#endif - GET_ARG(0); - -#ifdef CONFIG_USER_ONLY - /* - * Some C libraries assume the heap immediately follows .bss, so - * allocate it using sbrk. - */ - if (!ts->heap_limit) { - abi_ulong ret; - - ts->heap_base = do_brk(0); - limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE; - /* Try a big heap, and reduce the size if that fails. */ - for (;;) { - ret = do_brk(limit); - if (ret >= limit) { - break; - } - limit = (ts->heap_base >> 1) + (limit >> 1); - } - ts->heap_limit = limit; - } - - retvals[0] = ts->heap_base; - retvals[1] = ts->heap_limit; - retvals[2] = ts->stack_base; - retvals[3] = 0; /* Stack limit. */ -#else - limit = current_machine->ram_size; - /* TODO: Make this use the limit of the loaded application. */ - retvals[0] = rambase + limit / 2; - retvals[1] = rambase + limit; - retvals[2] = rambase + limit; /* Stack base */ - retvals[3] = rambase; /* Stack limit. */ -#endif - - for (i = 0; i < ARRAY_SIZE(retvals); i++) { - bool fail; - - fail = SET_ARG(i, retvals[i]); - - if (fail) { - /* Couldn't write back to argument block */ - errno = EFAULT; - return set_swi_errno(cs, -1); - } - } - return 0; + return do_heapinfo(cs, arg0); } case TARGET_SYS_EXIT: case TARGET_SYS_EXIT_EXTENDED: diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c index 33faac9916..fd5780ec3c 100644 --- a/tests/tcg/arm/semihosting.c +++ b/tests/tcg/arm/semihosting.c @@ -7,7 +7,13 @@ * SPDX-License-Identifier: GPL-3.0-or-later */ +#define _GNU_SOURCE /* asprintf is a GNU extension */ + #include +#include +#include +#include +#include #include "semicall.h" int main(int argc, char *argv[argc]) @@ -18,8 +24,34 @@ int main(int argc, char *argv[argc]) uintptr_t exit_block[2] = {0x20026, 0}; uintptr_t exit_code = (uintptr_t) &exit_block; #endif + struct { + void *heap_base; + void *heap_limit; + void *stack_base; + void *stack_limit; + } info; + void *ptr_to_info = (void *) &info; + char *heap_info, *stack_info; + void *brk = sbrk(0); + + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World\n"); + + memset(&info, 0, sizeof(info)); + __semi_call(SYS_HEAPINFO, (uintptr_t) &ptr_to_info); + + asprintf(&heap_info, "heap: %p -> %p\n", info.heap_base, info.heap_limit); + __semi_call(SYS_WRITE0, (uintptr_t) heap_info); + if (info.heap_base != brk) { + sprintf(heap_info, "heap mismatch: %p\n", brk); + __semi_call(SYS_WRITE0, (uintptr_t) heap_info); + return -1; + } + + asprintf(&stack_info, "stack: %p -> %p\n", info.stack_base, info.stack_limit); + __semi_call(SYS_WRITE0, (uintptr_t) stack_info); + free(heap_info); + free(stack_info); - __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); __semi_call(SYS_REPORTEXC, exit_code); /* if we get here we failed */ return -1;