From patchwork Wed Apr 18 08:52:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 133603 Delivered-To: patch@linaro.org Received: by 10.46.84.18 with SMTP id i18csp5640653ljb; Wed, 18 Apr 2018 01:53:48 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/UhWfDBa70ghpWhVs1P0Ko2nF53GqNLFD8h1oMtvM8nbddetBkXHQaoIG7RGq4XpOYk4oe X-Received: by 10.101.97.130 with SMTP id c2mr1073641pgv.219.1524041628389; Wed, 18 Apr 2018 01:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524041628; cv=none; d=google.com; s=arc-20160816; b=jc7JZXwZ3DMFhxW3YHhLHLFY+wVt6un4PPoLNtVcmuwCVIXMGFFGKWUTSvBu0UbVKr qUmvmXR5FgBG1UwWoQkNnHl6DBl74IzJ5xIt+tDD+dzUwdkc69RXXzi0ZQvDGyBdacM3 aNQTn9UCIwBz96aw8E74GdG988XnRjM3CrWoITnw8CIHjltL2RbGLhNOlbOCkPkoLLGN BiNI0VjVucTcuIxC59QMuTcX8KdtKr/I78eiWkf3ydkcSbT7M+WyGHhRvSogzjLQW/CA 8bEO3+UB0YiSWNHwmJkkFgqyZB0+3UTQwYe3k/YmDu8RCMZE1fCQuam9IUkON9gdmKjA iIhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:message-id:date:subject:to:from:dkim-signature :delivered-to:arc-authentication-results; bh=bQeLAXU9MdLU9MUSIr3kZ2Ll/Oeakv7SUfO3t3FaXwc=; b=sLQVjVf2G1rhX24EVjIf7fe7fbmHJ3GwLXo0mPRi4owHfhleRZvJLsj4cmnSLDJKgF ejLcKCjI0RNV/q5C9cw12Z4PlDhAnlyBoBYwr8tfNFNCTu4koI8sLWHqXuiEtNqIz327 beiYQpvBSNhfpX6IpoCHBMySScMC+hTlzumRrUC8dm45oApGb4UbfUU1gQb3omc/oqGJ 6gBS581jquoKGjnLqdhF/IR/F6WUKoQU+Nl1poMGyaI8lI5hlUH2eNgXGAW2o69/TFSF i99pg2qIXLvZ0mZhdmOJaisuMV6xsbHkC2PCAUxtQeyp0HzKnmvvkJ6tmCPRVDpa/b1V dypA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=P2YLUrWV; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id x9-v6si806358pln.508.2018.04.18.01.53.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Apr 2018 01:53:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=P2YLUrWV; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A692D6E547; Wed, 18 Apr 2018 08:53:16 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x234.google.com (mail-lf0-x234.google.com [IPv6:2a00:1450:4010:c07::234]) by gabe.freedesktop.org (Postfix) with ESMTPS id 155B76E546 for ; Wed, 18 Apr 2018 08:53:10 +0000 (UTC) Received: by mail-lf0-x234.google.com with SMTP id r125-v6so1459288lfe.2 for ; Wed, 18 Apr 2018 01:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=+h5217YrUL4fVme654aS8Guz6uZZZdmbAtT3U2Z9SAE=; b=P2YLUrWVFh6foLZ4Q2HxfGd0Jym/MWmOxWqoDr8iWr9oqew4dpFEqkHhrWQ8XJjHo7 nFNqYinaZ0aUM9LeG3sl6teoaECbzznEF1Kq825qtQQ9paY1tWL6knW9SkQyoJAgYgbQ YnfPqMPMrhw/y+eKYJFcglrozDAW4inxodZLE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+h5217YrUL4fVme654aS8Guz6uZZZdmbAtT3U2Z9SAE=; b=m74AT0Wxz2zCvcobgfnKX1V/90t21HPBxcaXgCzByvGPbXPZ4rcwGyZA3hcVn7Zzee fIq2dnzdpDuE1MPkrRmBobVhK/P0qsEQMczkos4qZeadcg6FQTOCK/tEAeBzZCpEep8X rYCeVh+Twj8ND/W6rd0S5VStPGlSCtViPxE5jAcSX0ibwk9bYynyGUp5OtIDyqGxhKYs f0qk6mA2KGbwdxbBLAopldgtHH53CU/Png1UZwtp0IdEVAqosUBM3kos3xXOn0Ub2rB5 f9lwS1A3AoxdiSrrQFZRpw0JZ0dzvBk83HtUN+116ysGMEOkOpLXxec0hPU4Ixou18Dq Gqvg== X-Gm-Message-State: ALQs6tBf6QtqRnyijN4RJ803bX5ops2+DS5XQlRe1vdcxXqZaVu91E2C 8zJ0lyUpwMzsMDHXEec3eZX8Yg== X-Received: by 2002:a19:d34c:: with SMTP id k73-v6mr830085lfg.118.1524041588298; Wed, 18 Apr 2018 01:53:08 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id x62-v6sm162225lfd.82.2018.04.18.01.53.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Apr 2018 01:53:07 -0700 (PDT) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt , Liviu Dudau Subject: [PATCH 1/2 v3] drm/pl111: Support the Versatile Express Date: Wed, 18 Apr 2018 10:52:41 +0200 Message-Id: <20180418085242.19525-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pawel Moll , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Versatile Express uses a special configuration controller deeply embedded in the system motherboard FPGA to multiplex the two to three (!) display controller instances out to the single SiI9022 bridge. Set up an extra file with the logic to probe to the FPGA mux register on the system controller bus, then parse the device tree to see if there is a CLCD or HDLCD instance on the core tile (also known as the daughterboard) by looking in the root of the device tree for compatible nodes. - If there is a HDLCD on the core tile, and there is a driver for it, we exit probe and deactivate the motherboard CLCD. We do not touch the DVI mux in this case, to make sure we don't break HDLCD. - If there is a CLCD on both the motherboard and the core tile (only the CA9 has this) the core tile CLCD takes precedence and get muxed to the DVI connector. - Only if there is no working graphics on the core tile, the motherboard CLCD is probed and muxed to the DVI connector. Core tile graphics should always take precedence as it can address all memory and is also faster, however the motherboard CLCD is good to have around for diagnostics and testing. It is possible to test the motherboard CLCD by setting the status = "disabled" property on the core tile CLCD or HDLCD. Scale down the Versatile Express to 16BPP so we can support a 1024x768 display despite the bus bandwidth restrictions on this platform. (The motherboard CLCD supports slightly lower resolution.) Cc: Liviu Dudau Cc: Pawel Moll Signed-off-by: Linus Walleij Acked-by: Eric Anholt --- ChangeLog v2->v3: - Rewrite CLCD detection and mux priority logic, look in the device tree root for core tile graphics. ChangeLog v1->v2: - No changes just reposting rebased on mainline changes. --- drivers/gpu/drm/pl111/Makefile | 1 + drivers/gpu/drm/pl111/pl111_versatile.c | 48 +++++++++++- drivers/gpu/drm/pl111/pl111_vexpress.c | 127 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/pl111/pl111_vexpress.h | 22 ++++++ 4 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/pl111/pl111_vexpress.c create mode 100644 drivers/gpu/drm/pl111/pl111_vexpress.h diff --git a/drivers/gpu/drm/pl111/Makefile b/drivers/gpu/drm/pl111/Makefile index 9c5e8dba8ac6..19a8189dc54f 100644 --- a/drivers/gpu/drm/pl111/Makefile +++ b/drivers/gpu/drm/pl111/Makefile @@ -3,6 +3,7 @@ pl111_drm-y += pl111_display.o \ pl111_versatile.o \ pl111_drv.o +pl111_drm-$(CONFIG_ARCH_VEXPRESS) += pl111_vexpress.o pl111_drm-$(CONFIG_DEBUG_FS) += pl111_debugfs.o obj-$(CONFIG_DRM_PL111) += pl111_drm.o diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c index 9302f516045e..569edf02a36a 100644 --- a/drivers/gpu/drm/pl111/pl111_versatile.c +++ b/drivers/gpu/drm/pl111/pl111_versatile.c @@ -1,12 +1,14 @@ #include #include #include +#include #include #include #include #include #include #include "pl111_versatile.h" +#include "pl111_vexpress.h" #include "pl111_drm.h" static struct regmap *versatile_syscon_map; @@ -22,6 +24,7 @@ enum versatile_clcd { REALVIEW_CLCD_PB11MP, REALVIEW_CLCD_PBA8, REALVIEW_CLCD_PBX, + VEXPRESS_CLCD_V2M, }; static const struct of_device_id versatile_clcd_of_match[] = { @@ -53,6 +56,10 @@ static const struct of_device_id versatile_clcd_of_match[] = { .compatible = "arm,realview-pbx-syscon", .data = (void *)REALVIEW_CLCD_PBX, }, + { + .compatible = "arm,vexpress-muxfpga", + .data = (void *)VEXPRESS_CLCD_V2M, + }, {}, }; @@ -286,12 +293,26 @@ static const struct pl111_variant_data pl111_realview = { .fb_bpp = 16, }; +/* + * Versatile Express PL111 variant, again we just push the maximum + * BPP to 16 to be able to get 1024x768 without saturating the memory + * bus. The clockdivider also seems broken on the Versatile Express. + */ +static const struct pl111_variant_data pl111_vexpress = { + .name = "PL111 Versatile Express", + .formats = pl111_realview_pixel_formats, + .nformats = ARRAY_SIZE(pl111_realview_pixel_formats), + .fb_bpp = 16, + .broken_clockdivider = true, +}; + int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv) { const struct of_device_id *clcd_id; enum versatile_clcd versatile_clcd_type; struct device_node *np; struct regmap *map; + int ret; np = of_find_matching_node_and_match(NULL, versatile_clcd_of_match, &clcd_id); @@ -301,7 +322,25 @@ int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv) } versatile_clcd_type = (enum versatile_clcd)clcd_id->data; - map = syscon_node_to_regmap(np); + /* Versatile Express special handling */ + if (versatile_clcd_type == VEXPRESS_CLCD_V2M) { + struct platform_device *pdev; + + /* Call into deep Vexpress configuration API */ + pdev = of_find_device_by_node(np); + if (!pdev) { + dev_err(dev, "can't find the sysreg device, deferring\n"); + return -EPROBE_DEFER; + } + map = dev_get_drvdata(&pdev->dev); + if (!map) { + dev_err(dev, "sysreg has not yet probed\n"); + return -EPROBE_DEFER; + } + } else { + map = syscon_node_to_regmap(np); + } + if (IS_ERR(map)) { dev_err(dev, "no Versatile syscon regmap\n"); return PTR_ERR(map); @@ -340,6 +379,13 @@ int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv) priv->variant_display_disable = pl111_realview_clcd_disable; dev_info(dev, "set up callbacks for RealView PL111\n"); break; + case VEXPRESS_CLCD_V2M: + priv->variant = &pl111_vexpress; + dev_info(dev, "initializing Versatile Express PL111\n"); + ret = pl111_vexpress_clcd_init(dev, priv, map); + if (ret) + return ret; + break; default: dev_info(dev, "unknown Versatile system controller\n"); break; diff --git a/drivers/gpu/drm/pl111/pl111_vexpress.c b/drivers/gpu/drm/pl111/pl111_vexpress.c new file mode 100644 index 000000000000..56908027659f --- /dev/null +++ b/drivers/gpu/drm/pl111/pl111_vexpress.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Versatile Express PL111 handling + * Copyright (C) 2018 Linus Walleij + * + * This module binds to the "arm,vexpress-muxfpga" device on the + * Versatile Express configuration bus and sets up which CLCD instance + * gets muxed out on the DVI bridge. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "pl111_drm.h" +#include "pl111_vexpress.h" + +#define VEXPRESS_FPGAMUX_MOTHERBOARD 0x00 +#define VEXPRESS_FPGAMUX_DAUGHTERBOARD_1 0x01 +#define VEXPRESS_FPGAMUX_DAUGHTERBOARD_2 0x02 + +int pl111_vexpress_clcd_init(struct device *dev, + struct pl111_drm_dev_private *priv, + struct regmap *map) +{ + struct device_node *root; + struct device_node *child; + struct device_node *ct_clcd = NULL; + bool has_coretile_clcd = false; + bool has_coretile_hdlcd = false; + bool mux_motherboard = true; + u32 val; + int ret; + + /* + * Check if we have a CLCD or HDLCD on the core tile by checking if a + * CLCD or HDLCD is available in the root of the device tree. + */ + root = of_find_node_by_path("/"); + if (!root) + return -EINVAL; + + for_each_child_of_node(root, child) { + if (of_device_is_compatible(child, "arm,pl111") + && of_device_is_available(child)) { + has_coretile_clcd = true; + ct_clcd = child; + break; + } + if (of_device_is_compatible(child, "arm,hdlcd") + && of_device_is_available(child)) { + has_coretile_hdlcd = true; + break; + } + } + + /* + * If there is a coretile HDLCD and it has a driver, + * do not mux the CLCD on the motherboard to the DVI. + */ + if (has_coretile_hdlcd && IS_ENABLED(CONFIG_DRM_HDLCD)) + mux_motherboard = false; + + /* + * On the Vexpress CA9 we let the CLCD on the coretile + * take precedence, so also in this case do not mux the + * motherboard to the DVI. + */ + if (has_coretile_clcd) + mux_motherboard = false; + + if (mux_motherboard) { + dev_info(dev, "DVI muxed to motherboard CLCD\n"); + val = VEXPRESS_FPGAMUX_MOTHERBOARD; + } else if (ct_clcd == dev->of_node) { + dev_info(dev, + "DVI muxed to daughterboard 1 (core tile) CLCD\n"); + val = VEXPRESS_FPGAMUX_DAUGHTERBOARD_1; + } else { + dev_info(dev, "core tile graphics present\n"); + dev_info(dev, "this device will be deactivated\n"); + return -ENODEV; + } + + ret = regmap_write(map, 0, val); + if (ret) { + dev_err(dev, "error setting DVI muxmode\n"); + return -ENODEV; + } + + return 0; +} + +/* + * This sets up the regmap pointer that will then be retrieved by + * the detection code in pl111_versatile.c and passed in to the + * pl111_vexpress_clcd_init() function above. + */ +static int vexpress_muxfpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *map; + + map = devm_regmap_init_vexpress_config(&pdev->dev); + if (IS_ERR(map)) + return PTR_ERR(map); + dev_set_drvdata(dev, map); + + return 0; +} + +static const struct of_device_id vexpress_muxfpga_match[] = { + { .compatible = "arm,vexpress-muxfpga", } +}; + +static struct platform_driver vexpress_muxfpga_driver = { + .driver = { + .name = "vexpress-muxfpga", + .of_match_table = of_match_ptr(vexpress_muxfpga_match), + }, + .probe = vexpress_muxfpga_probe, +}; + +module_platform_driver(vexpress_muxfpga_driver); diff --git a/drivers/gpu/drm/pl111/pl111_vexpress.h b/drivers/gpu/drm/pl111/pl111_vexpress.h new file mode 100644 index 000000000000..49876417f7b6 --- /dev/null +++ b/drivers/gpu/drm/pl111/pl111_vexpress.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 + +struct device; +struct pl111_drm_dev_private; +struct regmap; + +#ifdef CONFIG_ARCH_VEXPRESS + +int pl111_vexpress_clcd_init(struct device *dev, + struct pl111_drm_dev_private *priv, + struct regmap *map); + +#else + +static int inline pl111_vexpress_clcd_init(struct device *dev, + struct pl111_drm_dev_private *priv, + struct regmap *map) +{ + return -ENODEV; +} + +#endif From patchwork Wed Apr 18 08:52:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 133602 Delivered-To: patch@linaro.org Received: by 10.46.84.18 with SMTP id i18csp5640399ljb; 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[131.252.210.177]) by mx.google.com with ESMTPS id i12si735876pgr.256.2018.04.18.01.53.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Apr 2018 01:53:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kKU65vwW; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A642C6E54F; Wed, 18 Apr 2018 08:53:20 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id A44186E547 for ; Wed, 18 Apr 2018 08:53:15 +0000 (UTC) Received: by mail-lf0-x244.google.com with SMTP id x130-v6so1455541lff.9 for ; Wed, 18 Apr 2018 01:53:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=17/vWLNSIpPCwggiM+YLfpPQIpO3Ay55/URXqyl5eWg=; b=kKU65vwWavYnphpwX23sTGkPtL+WbitcL5+E+k9O4VaJXnx1JtXrIr/J0DpTPg05Bk zudT9CpYauKYeGST8k3XWbmWYYmuRxXdq7xEC85O/GxTc4ch1YSIgYeESXFdYbIL5wol ziP+pAevJLIBxaQ7RLd6mQRRlANNDqnlsZzO8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=17/vWLNSIpPCwggiM+YLfpPQIpO3Ay55/URXqyl5eWg=; b=Dm4QqR6/Zru5+HddSPAIS4RrsFiRGMpWWQnbW7bZijlW3IG++w2uVzQm/g3uulDNEh SSKhPBkqRGmrwkf2Aavx4fYMYxA9Flb6rv3ueizCEsiOVAkXwlF6aaX8HbF+t9UtLPb2 J9lfkjK+X1Y5Bqd7QEvaqmkc+kN8R+E48+KiVaqvIti7/++DDCCXkOfgNuGHWFU4xY0K 9oLCPX2Edt3UeNMM22O5v8Qvw2N69Ki9WWQiKz0+rD98ghiTfa2B1ZEZuLV+uTND7dZr ktdAXUPna/fL0M5uVEqOH55X5AjnovmemlIChOfE7gpjhznczX/8bQfjSRiG7+BWc3jw +MPQ== X-Gm-Message-State: ALQs6tBymIDf6JOlTcBlpM5pKHCoDTxx0H6cKCKTxKTrI7havP+OI8P1 Q+CkfFd2gCbSzD49v/nIVLIdsw== X-Received: by 10.46.135.68 with SMTP id q4mr837924ljj.125.1524041593993; Wed, 18 Apr 2018 01:53:13 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id x62-v6sm162225lfd.82.2018.04.18.01.53.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Apr 2018 01:53:12 -0700 (PDT) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt , Liviu Dudau Subject: [PATCH 2/2 v3] drm/pl111: Enable device-specific assigned memory Date: Wed, 18 Apr 2018 10:52:42 +0200 Message-Id: <20180418085242.19525-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180418085242.19525-1-linus.walleij@linaro.org> References: <20180418085242.19525-1-linus.walleij@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mali DP Maintainers , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Versatile Express has 8 MB of dedicated video RAM (VRAM) on the motherboard, which is what we should be using for the PL111 if available. On this platform, the memory backplane is constructed so that only this memory will work properly with the CLCD on the motherboard, using any other memory area just gives random snow on the display. The CA9 Versatile Express also has a PL111 instance on its core tile that can address all memory, and this does not have the restriction. The memory is assigned to the device using the memory-region device tree property and a "shared-dma-pool" reserved memory pool like this: reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; vram: vram@48000000 { compatible = "shared-dma-pool"; reg = <0x48000000 0x00800000>; no-map; }; }; clcd@1f000 { compatible = "arm,pl111", "arm,primecell"; (...) memory-region = <&vram>; }ยท; Cc: Liviu Dudau Cc: Mali DP Maintainers Signed-off-by: Linus Walleij Reviewed-by: Eric Anholt --- ChangeLog v2->v3: - Fix error path so we uref the memory properly. - Augment the GEM buffer import to return an error pointer if we try to import a buffer when using device-assigned memory: we can only scan out the special memory and the GEM buffers are not copied but referenced by pointer. ChangeLog v1->v2: - Make sure to also call of_reserved_mem_device_release() at remove() and errorpath. --- drivers/gpu/drm/pl111/pl111_drm.h | 1 + drivers/gpu/drm/pl111/pl111_drv.c | 33 +++++++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl111_drm.h index 8639b2d4ddf7..ce4501d0ab48 100644 --- a/drivers/gpu/drm/pl111/pl111_drm.h +++ b/drivers/gpu/drm/pl111/pl111_drm.h @@ -79,6 +79,7 @@ struct pl111_drm_dev_private { const struct pl111_variant_data *variant; void (*variant_display_enable) (struct drm_device *drm, u32 format); void (*variant_display_disable) (struct drm_device *drm); + bool use_device_memory; }; int pl111_display_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl111_drv.c index 4621259d5387..5fcf21837746 100644 --- a/drivers/gpu/drm/pl111/pl111_drv.c +++ b/drivers/gpu/drm/pl111/pl111_drv.c @@ -60,6 +60,7 @@ #include #include #include +#include #include #include @@ -207,6 +208,23 @@ static int pl111_modeset_init(struct drm_device *dev) return ret; } +struct drm_gem_object *pl111_gem_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sgt) +{ + struct pl111_drm_dev_private *priv = dev->dev_private; + + /* + * When using device-specific reserved memory we can't import + * DMA buffers: those are passed by reference in any global + * memory and we can only handle a specific range of memory. + */ + if (priv->use_device_memory) + return ERR_PTR(-EINVAL); + + return drm_gem_cma_prime_import_sg_table(dev, attach, sgt); +} + DEFINE_DRM_GEM_CMA_FOPS(drm_fops); static struct drm_driver pl111_drm_driver = { @@ -227,7 +245,7 @@ static struct drm_driver pl111_drm_driver = { .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = drm_gem_prime_import, - .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_import_sg_table = pl111_gem_import_sg_table, .gem_prime_export = drm_gem_prime_export, .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, @@ -257,6 +275,12 @@ static int pl111_amba_probe(struct amba_device *amba_dev, drm->dev_private = priv; priv->variant = variant; + ret = of_reserved_mem_device_init(dev); + if (!ret) { + dev_info(dev, "using device-specific reserved memory\n"); + priv->use_device_memory = true; + } + if (of_property_read_u32(dev->of_node, "max-memory-bandwidth", &priv->memory_bw)) { dev_info(dev, "no max memory bandwidth specified, assume unlimited\n"); @@ -275,7 +299,8 @@ static int pl111_amba_probe(struct amba_device *amba_dev, priv->regs = devm_ioremap_resource(dev, &amba_dev->res); if (IS_ERR(priv->regs)) { dev_err(dev, "%s failed mmio\n", __func__); - return PTR_ERR(priv->regs); + ret = PTR_ERR(priv->regs); + goto dev_unref; } /* This may override some variant settings */ @@ -305,11 +330,14 @@ static int pl111_amba_probe(struct amba_device *amba_dev, dev_unref: drm_dev_unref(drm); + of_reserved_mem_device_release(dev); + return ret; } static int pl111_amba_remove(struct amba_device *amba_dev) { + struct device *dev = &amba_dev->dev; struct drm_device *drm = amba_get_drvdata(amba_dev); struct pl111_drm_dev_private *priv = drm->dev_private; @@ -319,6 +347,7 @@ static int pl111_amba_remove(struct amba_device *amba_dev) drm_panel_bridge_remove(priv->bridge); drm_mode_config_cleanup(drm); drm_dev_unref(drm); + of_reserved_mem_device_release(dev); return 0; }