From patchwork Wed Mar 3 19:21:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 392718 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp251824jai; Thu, 4 Mar 2021 11:39:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwgS0mMYSjiH5DHTaHLS3Ff/j6BNi6zssVajAbsdNQMvBxZDPr7tLkq61NUPcQARYkljCM/ X-Received: by 2002:a05:6402:375:: with SMTP id s21mr6180506edw.287.1614886773035; Thu, 04 Mar 2021 11:39:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614886773; cv=none; d=google.com; s=arc-20160816; b=nSJSKe2eLIwQ/3OOahEWjausEYijuQDBXIMFmYFGgOTGC0OiL4w3JNnJZP4yKtePLj oz+p4IrDBHJx3h0p5LzqbHQ3F2tlXE2CserpRK+QmLAg9zPObeL8cMGvospp0d6kUYQ8 7JazbWTJRY/lae4VKyvENLSJ6n9PDBgOgSE3HsVwgu+Bnkz5PXhiHrEcDJqLfipqQU+K 2fCEZKRfRI8ZBU9R1YvcbV4FHfB/pUiXmnBgSXro+0B1uACPRK4I4oY0BzA2+kmhu6/Y XLgIqu3D/VwkQR+grAXGkC77VPIfC1QgQowk98qXf6TyGGK+CQiPMAz8YAaa9RsrWOFn H2DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oncgwn+mGdD6WlHFoBrw92BzHVUErtzYWLf3huz2pc0=; b=Ot1Jdpz+3QA2Kk8QZtpVXTalKqQI+4BsYjOS0eNxMLW46wzFsfIPDBxTCtg9Kof4Rg V6gmW4feaUgREuY3voIzfK1WBZvIoW4mij3UZu4lkwrmROHkXZKPe5KZnu8zHqHFYCb2 2dibiKnaWYRQwiiqRV4AEuHYzXS6srSpFAunhHJ8MTLh9lUw2phCgBWQ7VBUE7UG0MHg 2d6QzNToDtuIeW/4TktV9LTQgX9pi4MLZerEGHW43dTuAH7OBoPrcA0SOkMHL+/Vu2do l9uLaZiecYM7VZvL1DVGfNEGW/iUbspjR4T1zBfU4v73bomXIdkF0bAf6CtYmM7SsxmW Gg5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TPSFTsoa; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c3si324572edj.192.2021.03.04.11.39.32; Thu, 04 Mar 2021 11:39:33 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TPSFTsoa; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237400AbhCDAv5 (ORCPT + 6 others); Wed, 3 Mar 2021 19:51:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54706 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351026AbhCCTXV (ORCPT ); Wed, 3 Mar 2021 14:23:21 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 123JLY4n100372; Wed, 3 Mar 2021 13:21:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614799294; bh=oncgwn+mGdD6WlHFoBrw92BzHVUErtzYWLf3huz2pc0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TPSFTsoaJ33WCuTPdcRygQva0DgDrkT1WY+AtVOvNkkQ6UhC+dWoDt8nm7Z4pmcYX SHw7FlnXCjzfFoDKrdLBpyAX/nrXbHP0e1s/6LMX2MweVMxDSnMrcx47yaPvxgN64K Wr6mQmU78upm5vE/XrW2I1U6S9ECqv3fLjMvhC8A= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 123JLXMv096855 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 Mar 2021 13:21:34 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 3 Mar 2021 13:21:33 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 3 Mar 2021 13:21:33 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 123JLWUK038320; Wed, 3 Mar 2021 13:21:33 -0600 From: Grygorii Strashko To: Nishanth Menon , , , Vignesh Raghavendra , Lokesh Vutla CC: , Rob Herring , Kishon Vijay Abraham I , Tero Kristo , Grygorii Strashko Subject: [PATCH 1/4] arm64: dts: ti: am64-main: Add CPSW DT node Date: Wed, 3 Mar 2021 21:21:11 +0200 Message-ID: <20210303192114.12292-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210303192114.12292-1-grygorii.strashko@ti.com> References: <20210303192114.12292-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vignesh Raghavendra Add CPSW3g DT node with two external ports, MDIO and CPTS support. For CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency feature), so that CPSW DMA channel participates in Coherency and thus avoid need to cache maintenance for SKBs. This improves bidirectional TCP performance by up to 100Mbps (on 1G link). Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 + 2 files changed, 76 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 5f85950daef7..80443dbf272c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -178,6 +178,12 @@ compatible = "ti,am654-chipid"; reg = <0x00000014 0x4>; }; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; }; main_uart0: serial@2800000 { @@ -402,4 +408,72 @@ ti,otap-del-sel-ddr50 = <0x9>; ti,clkbuf-sel = <0x7>; }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x8000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 1>; + assigned-clock-parents = <&k3_clks 13 9>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_pktdma 0xC500 15>, + <&main_pktdma 0xC501 15>, + <&main_pktdma 0xC502 15>, + <&main_pktdma 0xC503 15>, + <&main_pktdma 0xC504 15>, + <&main_pktdma 0xC505 15>, + <&main_pktdma 0xC506 15>, + <&main_pktdma 0xC507 15>, + <&main_pktdma 0x4500 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 de ad be ef]; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 01 de ad be ef]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 13 1>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 0ae8c844c482..de6805b0c72c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -28,6 +28,8 @@ serial6 = &main_uart4; serial7 = &main_uart5; serial8 = &main_uart6; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; chosen { }; From patchwork Wed Mar 3 19:21:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 392716 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp248608jai; Thu, 4 Mar 2021 11:34:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJwvBZ3F2anmMbDCHKtrkh9kdHaIVwwHy3LNT7ZXdgfUtlOqZizdTz4S2CY0MwlTzM4y1YYs X-Received: by 2002:a50:fd15:: with SMTP id i21mr4865742eds.384.1614886469270; Thu, 04 Mar 2021 11:34:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614886469; cv=none; d=google.com; s=arc-20160816; b=N1T9sHXwVIP2jocHaES+En4R3FE+BSBCx6/PTfT2/ZuUA/uZ0BhEDBHmR86FXlrOyr CzRSN4mw1p3tw7mOBIHNA2v0G+oecSSrZVm9dS+aW8BNq7wtZinMmEBCj5PiaRvfG8sW gdBZ+zJv+JEH+JeQomYOZK4WJtf7T184IE74lz40GMEyRWsA5VFoqs0YXn87a3LAaycL yJzMEExYF0NehV/iw90G/w3CcHJVQHwIShjasKmQSet4dpr1roesDfSCEpO9ukQhH0R9 rFjUrgBvHjjT0TFzXAYmkZOZdzv8iD71YZlQpkdkcOaVkIgFoT/DHycWxM2x8w6HDBa+ JoFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=g5bA4TxNTkNpSyJeswh+tz6oQDdUJZwyCz+VpHY0Bto=; b=VBYRzZf+o7eUOaSzYR9HQOeb7gt3ZOZV+DccA2G3fQgFqaTdOD9eDNN2S8AaVKMzaT NxTqMZ9bpc2LTLGkHlBqqBFmPenFJvnJlfRdWJMsxcBWlAgeYR4jWRLf4Vi5P8LKrK7f Ld5eDF1gCghcq9DOFl+ssU2z+ivTH5KvCLmTwfBXYp500NyP9xBFJAqKgo05Mg+BVoYp tOHgOoPM5ie8sg+8LB5H8gdiEet903lwTGg8JZ91vH7gr8HdoAFo/hOaU+EYBQecVHCh 5r23OkZvhvZBu520ur1LkAcCUnPh5s2lqh7BqqyHDXRYrxC+9Ama8RWgDoRYPqxXc64+ uSSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yNTQbdWb; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 80443dbf272c..0cf727e3d1e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -476,4 +476,19 @@ ti,cpts-periodic-outputs = <2>; }; }; + + cpts@39000000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x39000000 0x0 0x400>; + reg-names = "cpts"; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 84 0>; + clock-names = "cpts"; + assigned-clocks = <&k3_clks 84 0>; + assigned-clock-parents = <&k3_clks 84 8>; + interrupts = ; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; }; From patchwork Wed Mar 3 19:21:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 392715 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp247772jai; Thu, 4 Mar 2021 11:33:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJxE+mZZEnNF2ZF5YnzW5vrLyI5SGMdzoKCOdCL+agEM5Oyl2PyHhJLQI9eJvH8mz4sgXP0T X-Received: by 2002:a50:cdd1:: with SMTP id h17mr6187994edj.178.1614886393384; Thu, 04 Mar 2021 11:33:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614886393; cv=none; d=google.com; s=arc-20160816; b=FQx1yEzQHoLg92KLwYG67lDuHq4TNP93TJ0RHj6etx+7fhWjXsrOlFSngZkGO1YS7m nSRVJlNwgQ6k9Z8pcgCss9DOxn+XEfvUVoWZv6m6qccGHMM5TfUcFgtZdoJsg3WGF36P oOrxkwORM8PdGedwQHgzaGXvDfIId1wnjhZlFvBGnQaw/b8Giyy5xgnIA+s9R1ElZ638 +caArUNayTB0y+7dHQ2RXzQNeY7UesNF+gvuj3CX/jX4X9FQVez8OxpkPL7uGbrcEXow Lv6AaWQOq74Hhq1QZZZUJTUCcbp2uJjeEliztW4+P1i5VFTRdtksnMf7wVxcjMAJiaeT 7lbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qMb4P4HjbzyrvAYPa1BnhHFeKU+YNnJIJA0aEYTmYH0=; b=l2b8sUwoJYKgyTnf6uFi4zdEZ4GBt1HDBQt+QV5QFo8bcv0HrnBL3D/xvqSnqkPunI o8Cto+h/yjxgT1Enm3eAFT/bJnl2Jan2o8pIEuAaNvB6FGBNiMe68r+9gBzXBOrft3Jr UT4gL6vpJIuBCsheKHM0Zt+IIBMPFr7twGTOUb+KkZ5JtS4nXX0LdvdfO14pUmY2QBCs hfheshKkB0go9igWZhPOf7FanECwAGbhsvBzzGL7Gc5qvrBrL7B4jNeCEXU3DRc/2qxP WraZTXnXUC0JH+Z3RecWY6yurbLe3/5nLp13nOnvFjLXLvAKMemDG3VfXWbZHQbqLyBh eKqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=st3FKmUP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t13si82744ejf.189.2021.03.04.11.33.13; Thu, 04 Mar 2021 11:33:13 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=st3FKmUP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238723AbhCDAv4 (ORCPT + 6 others); Wed, 3 Mar 2021 19:51:56 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45170 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245303AbhCCTWx (ORCPT ); Wed, 3 Mar 2021 14:22:53 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 123JLmCK019579; Wed, 3 Mar 2021 13:21:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614799308; bh=qMb4P4HjbzyrvAYPa1BnhHFeKU+YNnJIJA0aEYTmYH0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=st3FKmUPhxRm28HdqDyebBTWou1JR0Vu+zyw3EJQmp4GsQkVqO/Z3kuz7S2L8TlK1 eLlqQvxRfGR6OrKTGBMpWxXejqnW1Mxu/n232LsExnvixWvIloa4jLinS451R3zafa hZyNh6SXdkkt4dJUswXbB+NVUwakx7lpEBHFWtfY= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 123JLmJC070222 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 Mar 2021 13:21:48 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 3 Mar 2021 13:21:48 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 3 Mar 2021 13:21:48 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 123JLlFp038503; Wed, 3 Mar 2021 13:21:47 -0600 From: Grygorii Strashko To: Nishanth Menon , , , Vignesh Raghavendra , Lokesh Vutla CC: , Rob Herring , Kishon Vijay Abraham I , Tero Kristo , Grygorii Strashko Subject: [PATCH 3/4] arm64: dts: ti: k3-am642-evm: add CPSW3g DT nodes Date: Wed, 3 Mar 2021 21:21:13 +0200 Message-ID: <20210303192114.12292-4-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210303192114.12292-1-grygorii.strashko@ti.com> References: <20210303192114.12292-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vignesh Raghavendra On am642-evm the CPSW3g ext. Port1 is directly connected to TI DP83867 PHY and Port2 is connected to TI DP83869 PHY which is shared with ICSS subsystem. The TI DP83869 PHY MII interface is configured using pinmux for CPSW3g, while MDIO bus is connected through GPIO controllable 2:1 TMUX154E switch (MDIO GPIO MUX) which has to be configured to route MDIO bus from CPSW3g to TI DP83869 PHY. Hence add networking support for am642-evm: - add CPSW3g MDIO and RGMII pinmux entries for both ext. ports; - add CPSW3g nodes; - add mdio-mux-multiplexer DT nodes to represent above topology. Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 93 +++++++++++++++++++++++++ 1 file changed, 93 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 1f1787750fef..962ef807e286 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -6,6 +6,8 @@ /dts-v1/; #include +#include +#include #include "k3-am642.dtsi" / { @@ -101,6 +103,31 @@ default-state = "off"; }; }; + + mdio_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; + }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&cpsw3g_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &main_pmx0 { @@ -133,6 +160,47 @@ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; + + mdio1_pins_default: mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; }; &main_uart0 { @@ -244,3 +312,28 @@ ti,driver-strength-ohm = <50>; disable-wp; }; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default + &rgmii1_pins_default + &rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; From patchwork Wed Mar 3 19:21:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 392719 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp256545jai; Thu, 4 Mar 2021 11:47:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJwEqDINmNltL6VMCpbas/52McUw1BddfoWPb35LxExCtr64ZTFQH1LGAxwinUSX8RaXcaYj X-Received: by 2002:aa7:c447:: with SMTP id n7mr6113579edr.171.1614887229096; Thu, 04 Mar 2021 11:47:09 -0800 (PST) ARC-Seal: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id b22si106101ejj.279.2021.03.04.11.47.08; Thu, 04 Mar 2021 11:47:09 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=W3NlrZaX; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237477AbhCDAv6 (ORCPT + 6 others); Wed, 3 Mar 2021 19:51:58 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54740 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378145AbhCCTXg (ORCPT ); Wed, 3 Mar 2021 14:23:36 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 123JLtiA100450; Wed, 3 Mar 2021 13:21:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614799315; bh=Yt5R1eGC4ciGzvBmbYfVzacv0wWSiJR2kx699Wn9L/k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W3NlrZaX8aM+ZWFQea7cwxzExMH1itjvPPuVSm8KElEIHwjCvl2/wfd4DB4ibxIs6 C9hnj4v3INbTLX2epiti1iOD96PmQGMPSDpAEmvb5ikublKWdnH5bzugGJR+nvfDt4 PkTK/PXYoA58QMZ2Q75k7Y6b4zo/ibylFunmnU80= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 123JLt5g097088 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 3 Mar 2021 13:21:55 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 3 Mar 2021 13:21:55 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 3 Mar 2021 13:21:55 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 123JLsdf013214; Wed, 3 Mar 2021 13:21:54 -0600 From: Grygorii Strashko To: Nishanth Menon , , , Vignesh Raghavendra , Lokesh Vutla CC: , Rob Herring , Kishon Vijay Abraham I , Tero Kristo , Grygorii Strashko Subject: [PATCH 4/4] arm64: dts: ti: k3-am642-sk: Add CPSW DT nodes Date: Wed, 3 Mar 2021 21:21:14 +0200 Message-ID: <20210303192114.12292-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210303192114.12292-1-grygorii.strashko@ti.com> References: <20210303192114.12292-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vignesh Raghavendra AM642 SK board has 2 CPSW3g ports connected through TI DP83867 PHYs. Add DT entries for the same. Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 73 ++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index aa6ca4c49153..397ed3b2e121 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "k3-am642.dtsi" / { @@ -90,6 +91,47 @@ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; + + mdio1_pins_default: mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ + AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ + AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ + AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; }; &mcu_uart0 { @@ -171,3 +213,34 @@ ti,driver-strength-ohm = <50>; disable-wp; }; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default + &rgmii1_pins_default + &rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +};