From patchwork Tue Mar 2 13:15:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Devera X-Patchwork-Id: 392484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D183C2BA13 for ; Wed, 3 Mar 2021 02:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF95664E75 for ; Wed, 3 Mar 2021 02:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349164AbhCCCRb (ORCPT ); Tue, 2 Mar 2021 21:17:31 -0500 Received: from ms9.eaxlabs.cz ([147.135.177.209]:47084 "EHLO ms9.eaxlabs.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575729AbhCBPgw (ORCPT ); Tue, 2 Mar 2021 10:36:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=eaxlabs.cz; s=mail; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=65e45oHZO+BxFf5UqN9fVtID/K010U91Mz2QcQ/swdo=; b=W0CSeYqtKX1Fo9IiZ2gD/lsrmkNl5mc18rDmr54RX98DO+epfDea2DwP1u8Ik3EoRQvjtTb2uy5nGXqoOg+buliEafOYLrkLFjYbrOgkHUmOkJj63n0UW8I0hDiBZu8HkX4iC0aRyAGna93+b8jpO3SgbXOJfUwhVqM09mFsjag=; Received: from [82.99.129.6] (helo=localhost.localdomain) by ms9.eaxlabs.cz with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1lH4sj-0000g6-Un; Tue, 02 Mar 2021 14:16:12 +0100 From: Martin Devera To: linux-kernel@vger.kernel.org Cc: Martin Devera , Greg Kroah-Hartman , Rob Herring , Maxime Coquelin , Alexandre Torgue , Jiri Slaby , Le Ray , fabrice.gasnier@foss.st.com, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] dt-bindings: serial: Add rx-tx-swap to stm32-usart Date: Tue, 2 Mar 2021 14:15:57 +0100 Message-Id: <20210302131558.19375-1-devik@eaxlabs.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: <439a0d7a-cc0e-764b-7ed8-668b5a85f4a7@foss.st.com> References: <439a0d7a-cc0e-764b-7ed8-668b5a85f4a7@foss.st.com> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add new rx-tx-swap property to allow for RX & TX pin swapping. Signed-off-by: Martin Devera --- .../devicetree/bindings/serial/st,stm32-uart.yaml | 32 +++++++++++++++------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 8631678283f9..6eab2debebb5 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -9,9 +9,6 @@ maintainers: title: STMicroelectronics STM32 USART bindings -allOf: - - $ref: rs485.yaml - properties: compatible: enum: @@ -40,6 +37,10 @@ properties: uart-has-rtscts: true + rx-tx-swap: + type: boolean + maxItems: 1 + dmas: minItems: 1 maxItems: 2 @@ -66,13 +67,24 @@ properties: linux,rs485-enabled-at-boot-time: true rs485-rx-during-tx: true -if: - required: - - st,hw-flow-ctrl -then: - properties: - cts-gpios: false - rts-gpios: false +allOf: + - $ref: rs485.yaml + - if: + required: + - st,hw-flow-ctrl + then: + properties: + cts-gpios: false + rts-gpios: false + - if: + required: + - rx-tx-swap + then: + properties: + compatible: + enum: + - st,stm32f7-uart + - st,stm32h7-uart required: - compatible From patchwork Tue Mar 2 13:15:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Devera X-Patchwork-Id: 392483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB074C2BA11 for ; Wed, 3 Mar 2021 02:20:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D36364E7A for ; Wed, 3 Mar 2021 02:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349163AbhCCCRb (ORCPT ); Tue, 2 Mar 2021 21:17:31 -0500 Received: from ms9.eaxlabs.cz ([147.135.177.209]:46936 "EHLO ms9.eaxlabs.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1384624AbhCBPda (ORCPT ); Tue, 2 Mar 2021 10:33:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=eaxlabs.cz; s=mail; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=DV5p333v2jKUPIpG+adysRuHr9qmQs+BdQUH7O5bVcU=; b=1/GVlipD6xAf2VV4JGK4d5RrHTbw/uYOs2CAue7JLK+s6zMwQ/8O/+5XxEj5+CD6AyC2HZlO4hLOe+unnJ4pMVqKfy7DleP1RsjgRU8Ud2NNmpkue0l2ke/r5rIpLAQqoMKMYutmVqRC0XDZPtALXougjadCABKFX5wTPNhOQOc=; Received: from [82.99.129.6] (helo=localhost.localdomain) by ms9.eaxlabs.cz with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1lH4sn-0000g6-K5; Tue, 02 Mar 2021 14:16:15 +0100 From: Martin Devera To: linux-kernel@vger.kernel.org Cc: Martin Devera , Greg Kroah-Hartman , Rob Herring , Maxime Coquelin , Alexandre Torgue , Jiri Slaby , Le Ray , fabrice.gasnier@foss.st.com, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart Date: Tue, 2 Mar 2021 14:15:58 +0100 Message-Id: <20210302131558.19375-2-devik@eaxlabs.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210302131558.19375-1-devik@eaxlabs.cz> References: <439a0d7a-cc0e-764b-7ed8-668b5a85f4a7@foss.st.com> <20210302131558.19375-1-devik@eaxlabs.cz> Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org STM32 F7/H7 usarts supports RX & TX pin swapping. Add option to turn it on. Tested on STM32MP157. Signed-off-by: Martin Devera --- drivers/tty/serial/stm32-usart.c | 11 ++++++++++- drivers/tty/serial/stm32-usart.h | 5 +++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index b3675cf25a69..d390f7da1441 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port) if (ret) return ret; + if (stm32_port->swap) { + val = readl_relaxed(port->membase + ofs->cr2); + val |= USART_CR2_SWAP; + writel_relaxed(val, port->membase + ofs->cr2); + } + /* RX FIFO Flush */ if (ofs->rqr != UNDEF_REG) stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); @@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port, cr1 = USART_CR1_TE | USART_CR1_RE; if (stm32_port->fifoen) cr1 |= USART_CR1_FIFOEN; - cr2 = 0; + cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; cr3 = readl_relaxed(port->membase + ofs->cr3); cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE | USART_CR3_TXFTCFG_MASK; @@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port *stm32port, return stm32port->wakeirq ? : -ENODEV; } + stm32port->swap = stm32port->info->cfg.has_swap && + of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); + stm32port->fifoen = stm32port->info->cfg.has_fifo; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index cb4f327c46db..bd18dd1c1bcd 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -25,6 +25,7 @@ struct stm32_usart_offsets { struct stm32_usart_config { u8 uart_enable_bit; /* USART_CR1_UE */ bool has_7bits_data; + bool has_swap; bool has_wakeup; bool has_fifo; int fifosize; @@ -55,6 +56,7 @@ struct stm32_usart_info stm32f4_info = { .cfg = { .uart_enable_bit = 13, .has_7bits_data = false, + .has_swap = false, .fifosize = 1, } }; @@ -76,6 +78,7 @@ struct stm32_usart_info stm32f7_info = { .cfg = { .uart_enable_bit = 0, .has_7bits_data = true, + .has_swap = true, .fifosize = 1, } }; @@ -97,6 +100,7 @@ struct stm32_usart_info stm32h7_info = { .cfg = { .uart_enable_bit = 0, .has_7bits_data = true, + .has_swap = true, .has_wakeup = true, .has_fifo = true, .fifosize = 16, @@ -271,6 +275,7 @@ struct stm32_port { int last_res; bool tx_dma_busy; /* dma tx busy */ bool hw_flow_control; + bool swap; /* swap RX & TX pins */ bool fifoen; int wakeirq; int rdr_mask; /* receive data register mask */