From patchwork Wed Apr 11 21:16:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 133172 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1037314ljb; Wed, 11 Apr 2018 14:16:41 -0700 (PDT) X-Google-Smtp-Source: AIpwx49yMjdPQrji6tcAR6xfm3Fxvw+Pg9TepFGMNRt3ZKV5/y5xCQ86qHVpvPY7pp0J0lbC+NJx X-Received: by 10.99.186.26 with SMTP id k26mr3255684pgf.39.1523481401052; Wed, 11 Apr 2018 14:16:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523481401; cv=none; d=google.com; s=arc-20160816; b=dJuTbegs9WAi0thbMYoysN3+5+L/8PtX3v6oWM0Qdi1qUujzFF+wh3joYRzpt8Fy1h Sg3uQk6JsAv50Ao9U28LcNcIK3OK0++5cmsRm9Um3XNFOBZ4XPQmGsRgQFxM1aiDIwrU hYwiGf3Xtr6lzsRuBiWUd5AZn3uTGz/okmrwaXzzXgv5qUDk8foOx1wuuDEJrK4fDb0A c+qrklKYoSC/PsKrJ4r+TmAcFNeEN7q7bOimM/AnI/6HK5b2/po/EfceiIy/Hw2SEW31 0PXLIZmoEI85QHESqNRxZ5dBDJGJjAL1JSMhDTCcRTmMyVelLoiWBcYPqh+oMu2BkPtW CsNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:to:from:delivered-to:sender:list-help :list-post:list-archive:list-subscribe:list-unsubscribe:list-id :precedence:mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=/58BtFjtASY33cpSfVmiwgP6rfD1BfvlfF+4gZiXpwM=; b=eX3kMK++IvPlwmcjLj3z0Xde9GUhWdPls3ioWZTdwO+U/Qwzfolkq7/07/+DP2gcEM cb1ypmPRBtzZGnPkrk068PdAQdoLCa0M+PWXQ+mAn3Hc8bOZcBmoYe52bUoA7DUhkE/q pSmv9KPAXky5G0/uazBwp9Q7hM3YzU/Lm91lYlBarxzOniFI+8BZ5bSZhDLCkBGtZY4E AGk1H3/zfbFyjkDAweFsgni2pCQUbdMcx0xwjBYlZC1QJFIGoPu2CpJ7m6nrch8pYr/3 UwK7SurVF879CAXJXJIbszC5mKsd8NAyaSgBW77Exh69bw6nkvGoSgJUVMzrp4CI43+B y4ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=RdZrascw; spf=pass (google.com: domain of libc-alpha-return-91503-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91503-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id i63si1320071pge.219.2018.04.11.14.16.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 14:16:41 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-91503-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=RdZrascw; spf=pass (google.com: domain of libc-alpha-return-91503-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91503-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; q=dns; s= default; b=UvZvUVpCsb/2cZmviK8aDljqHMzn8jg//7sjdguY0CWQnVOJ+d7g1 OXnxJItRnUulwVEvgYrr8O2KSb8Z+5M+yTKOKbuFR6K+6oafFCGEyj1NXw0zkzDJ tOrtHqD1LRfoJ4uYiIp3+FkTwtsI7tyOs7ottLrr4b68ITq8/h36Q8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id; s=default; bh=aiJeB/048WUdfWF7LfrPWN4Ypmg=; b=RdZrascwDxeQLdy1ADjLL6Z20p+h dBpcXFPuONfcdhNd9n9jQJDa4itHdFsID2Q0cvKt/EdQZezaWZITU8WofW9lrp16 mQ+UfIO1KjXuumqaOLEHMyYbQCMo0T7qgfPMLPOv9htKwQUjdE0QXWDlqXrEuko1 lq8urS030lExCyQ= Received: (qmail 117516 invoked by alias); 11 Apr 2018 21:16:30 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 117501 invoked by uid 89); 11 Apr 2018 21:16:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-qt0-f177.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=/58BtFjtASY33cpSfVmiwgP6rfD1BfvlfF+4gZiXpwM=; b=Kyer78jRfTC/PMXgYiIorVaDaKkyGvk2Nuc6XD+gBwRlWUprvU//OBJxBJLyR7o3sq jRf1W11VdD5IQB1NNBT2unvd1UVR+KVjstbfP9BlYsIi2EMytdruaOv3gUw8ZBJdPOY9 FYjtJxGM+Ga8utoZXPeinVbafqOdYEkuC2BgPnrEja/wb4JCucJlih20hWKXexv+UXIQ VmVxeYRmROmwkkQA8dqCr4UeLe1coTmwecqlofllsTTIWv2RXMZ7gItwKzNio+Vl1rOe Yj4lKNAFW4vF+COXdfamuI4FeUfZsQS1XyNr1p/tCxFTMayOvCYXNXq3hhyERhRVSYFU zcKA== X-Gm-Message-State: ALQs6tAUk1n6nLzo1NvisrNeiAngpvBh7V6kFlm5Owpj1Y86CmqB7ykk fC5t+QBrvMctPyI3wLVg7+41+vHVl5s= X-Received: by 10.200.4.9 with SMTP id v9mr9642389qtg.69.1523481385978; Wed, 11 Apr 2018 14:16:25 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 1/4] arm: Fix armv7 neon memchr on ARM mode Date: Wed, 11 Apr 2018 18:16:15 -0300 Message-Id: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv7 neon memchr uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Also, even if the implementation is fixed to not use thumb instructions it was clearly not proper checked in ARM mode: the carry bit flag will be reset in previous 'cmp synd, #0' and thus the 'bhi cntin, #0' won't be able to branch correctly if the loop finishes with 'cntin' being negative (indicating that some bytes still require to be checked). This patch also fixes it by checking the carry flag in previous loop iteration directly (in ARM mode it will run both '.Lmasklast' and '.Ltail' even if no byte is found in last loop iteration). Checked on arm-linux-gnueabihf (with -marm and -mthumb mode). [BZ #23031] * sysdeps/arm/armv7/multiarch/memchr_neon.S (memchr): Fix tail check on ARM mode. (NO_THUMB): Check __thumb__ instead. --- ChangeLog | 7 +++++++ sysdeps/arm/armv7/multiarch/memchr_neon.S | 9 +++------ 2 files changed, 10 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/sysdeps/arm/armv7/multiarch/memchr_neon.S b/sysdeps/arm/armv7/multiarch/memchr_neon.S index 1b2ae75..1b2a69d 100644 --- a/sysdeps/arm/armv7/multiarch/memchr_neon.S +++ b/sysdeps/arm/armv7/multiarch/memchr_neon.S @@ -68,7 +68,7 @@ * allows to identify exactly which byte has matched. */ -#ifndef NO_THUMB +#ifdef __thumb__ .thumb_func #else .arm @@ -132,7 +132,7 @@ ENTRY(memchr) /* The first block can also be the last */ bls .Lmasklast /* Have we found something already? */ -#ifndef NO_THUMB +#ifdef __thumb__ cbnz synd, .Ltail #else cmp synd, #0 @@ -176,14 +176,11 @@ ENTRY(memchr) vpadd.i8 vdata0_0, vdata0_0, vdata1_0 vpadd.i8 vdata0_0, vdata0_0, vdata0_0 vmov synd, vdata0_0[0] -#ifndef NO_THUMB +#ifdef __thumb__ cbz synd, .Lnotfound bhi .Ltail /* Uses the condition code from subs cntin, cntin, #32 above. */ #else - cmp synd, #0 - beq .Lnotfound - cmp cntin, #0 bhi .Ltail #endif From patchwork Wed Apr 11 21:16:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 133173 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1037419ljb; Wed, 11 Apr 2018 14:16:49 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+MyBX/OWHJ0YllN/pG+tP7x8DV6mmSVn/KDrT/LscykOzQltlnv6S+1uIN2ViQ1GHSgo/N X-Received: by 10.99.95.142 with SMTP id t136mr4494142pgb.302.1523481409326; Wed, 11 Apr 2018 14:16:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523481409; cv=none; d=google.com; s=arc-20160816; b=Kxk02zhCqb4BPj5kV96bkH70Dt8VhgYgSbXLiaETF7UyVr1amSxIyfHg0kFbust6BK KIvwu9UgoWZrPZogdoPQF72bsH8TrHwWMvswn8xvCdsjfQrqnV7j9+t985WKWJe1+03Z qJjF/ZXr0lXfI+gE51cDRTl9YCgysbVqwK7ASDJNyHmV46NHR1qpE2UaTd9hKCY01LW2 fYpwmtyBgJW+luLSxGKfL9bWJRLamvg6SLQAAl4Tg7/3Y4d8CmhOBCwk9Vxw7W6dJFnh Y/AUyiJCzFnC0KYqL50/sbYZ+zBOTL1xyi1sdAyJhFdY4suwGkQ6W3bn6SpXRMIJ7szv eOhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from:delivered-to :sender:list-help:list-post:list-archive:list-subscribe :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=k2PURCzAKrYq84Ui92ryKubW2SLZnlspVYb5f72V3gg=; b=rTe+w1EKBE4XS3YLKXhaKLpK8jGCo5bECLBv6JrQ8ngZrju2SiikGOlk/T0tbbUDOP B60cxQ5fTht9Y4O04ZeEzXupj1Jyaj0hcHHYzgvCh3ik9mErMPBnK1TrVC5kLn9MWrre pCeHpAMu6n3rV55Jhi8H1He3S1niMIyW27W8pLhc4yJsFoV+7g3U76OuitW4qZbZFt3u HkXDtIFm9h84BN8z4rblmGNpqzBCUpaUrqmv0L5NFW5UXp2C5nLj6vB/RWYb8cI89y1d TKTgOZaAsdV5dejlvNSCox53aU3ZK3Z6+N0U59rwtEAUzty41M/a4CJf1RN6fgu7o5WN t1sA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=mz0NwISE; spf=pass (google.com: domain of libc-alpha-return-91504-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91504-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id q64si1456741pfq.385.2018.04.11.14.16.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 14:16:49 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-91504-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=mz0NwISE; spf=pass (google.com: domain of libc-alpha-return-91504-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91504-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=as9RRMaNsbMel3SkZVRjIOVtOCAzK4W iWusklXjSQ3gNyqoMCjsAutDo9Zpv6pSkJEgbtdrpn+5AA9hDe3isWjp1s/5XGM7 m8H4PbAyuh4nehTeTsaD/bZdxirGY9p/k/1zlR/sDIOqojUQT3FRZLcAxGdqdGS4 dfzXjitVmUo8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=DXC/Y+GyHERX9sKWUbQ4fiQaj+A=; b=mz0Nw ISE667I9rxWSx6zr8txKI/eu4iI9P6Tm5dEtpnmsjfgPlqsw+StYbcoYmxlVMlG0 u6tCyxTNUxGgqenT2GB0pbASLWR7VnMLtFdGj1jx6qAMmliMdbu48CWbauL8198W kli26/Ry4tDI4OOOiueITHnbZzev5xUXXRnp/M= Received: (qmail 117673 invoked by alias); 11 Apr 2018 21:16:31 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 117583 invoked by uid 89); 11 Apr 2018 21:16:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=mvn X-HELO: mail-qt0-f179.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=k2PURCzAKrYq84Ui92ryKubW2SLZnlspVYb5f72V3gg=; b=aToadpgHGBBaz4MgqVDGzLHJxibqFjprq1bhooDs0gIyHNSE1h348rZUizeYfQhXDf mbh7DBv/Gagx1bc57uvyjzlRrujbZFn+cqO6YmsTYQYnUfW4NMXzrniSU++NI+sGP/RG SuePiccFNIGUnbyjTVy9z0D237x6cM9v9OoCP1JQ7vtu4hJX0DLdTfWrXkKjgtnm5AmU kj9zdtflms95eYkwD9mHiDrBvFk8gKs/R2VPR9OOAm7Dcnlo2zqXg0ZbyOjSOpnBxvN8 ZdlPRH7oqFyuohEKt2wja01iZ1D3hHIHaHVpWsnZfJpqE6EdL9Soh/kxe2YCfDBDCQHw h//w== X-Gm-Message-State: ALQs6tBy9oM2oDcQVXEf8aa1EZsDZhbMWiFl2S20EMfBxBIzGztPqs+b cPxMZAI00WY/vz/mXlXLw1jH1pPibAA= X-Received: by 10.200.81.200 with SMTP id d8mr9608352qtn.1.1523481387207; Wed, 11 Apr 2018 14:16:27 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 2/4] arm: Fix armv7 neon strcmp on ARM mode Date: Wed, 11 Apr 2018 18:16:16 -0300 Message-Id: <1523481378-16290-2-git-send-email-adhemerval.zanella@linaro.org> In-Reply-To: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> References: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv7 neon strcmp uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Also, even if the implementation is fixed to not use thumb instructions it was clearly not proper checked in ARM mode: the 'prepare_mask' does not build (it sets the 'mvn' instruction to use register predicate in shift amount). This patch fixes it by using a S2HI plus mvn to mimic the expected nor operation. Checked on arm-linux-gnueabihf (with -marm and -mthumb mode). [BZ #23031] * sysdeps/arm/armv7/strcmp.S [!__thumb__] (prepare_mask): Fix build and logic. --- ChangeLog | 4 ++++ sysdeps/arm/armv7/strcmp.S | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/sysdeps/arm/armv7/strcmp.S b/sysdeps/arm/armv7/strcmp.S index 060b865..a20b3e5 100644 --- a/sysdeps/arm/armv7/strcmp.S +++ b/sysdeps/arm/armv7/strcmp.S @@ -82,8 +82,7 @@ #define data2 r3 #define syndrome tmp2 - -#ifndef NO_THUMB +#ifdef __thumb__ /* This code is best on Thumb. */ .thumb @@ -97,7 +96,8 @@ #else /* In ARM code we don't have ORN, but we can use MVN with a register shift. */ .macro prepare_mask mask_reg, nbits_reg - mvn \mask_reg, const_m1, S2HI \nbits_reg + S2HI \mask_reg, const_m1, \nbits_reg + mvn \mask_reg, \mask_reg .endm .macro apply_mask data_reg, mask_reg orr \data_reg, \data_reg, \mask_reg From patchwork Wed Apr 11 21:16:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 133174 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1037518ljb; Wed, 11 Apr 2018 14:16:59 -0700 (PDT) X-Google-Smtp-Source: AIpwx48KjRObYQBCmOhVgrur7kqMzuk4I2Aqkb7vrWhjdoAu42QirW11746g53u/mmhWN3lniNt3 X-Received: by 2002:a17:902:bc89:: with SMTP id bb9-v6mr6598585plb.285.1523481419113; Wed, 11 Apr 2018 14:16:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523481419; cv=none; d=google.com; s=arc-20160816; b=FT9J0BUeGcEuXddG5MITYfby7yOXnl0mE95fEgGEL4CVa5QI2vlNTFlz72Ko6ooLa0 QV9NbxdapgBqj+S8UglPOOLQQ5QroyG2lMjsV6VU8ZKxjlYtrhlA7vfbPSHWPIVidHBm 8Bffwoom0ZUs/90Ut82lVA0eoz/kngMDFpCcweeLgFln7J7eKlLuyvb+3dLnzL2UyVyv QnLk0Er0ehU7zsTLFnhqlnwLjfhqcNSFB7SfGQZ0Bx+vSoulm8bSENPX3iuD/twSGDR9 sMoC19ASLikjscI3hW33Vu1j1eCEBl0of4IN5qCzuXz6yDuPZU4ifsIu3210/Xg88sU/ uvpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from:delivered-to :sender:list-help:list-post:list-archive:list-subscribe :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=0xt6HHZb6s6E+hJnS8iCVYKgwYg2GnlNDvMxd4DGV/0=; b=flClg6HnalBzBtsTp5E6LgFuMrs8nzO29MK/yuDPoZgMzijj2NEi3lms5sJIQiSEkw 98NYZYVUd6oW2TlJzquP5VmtRzsd7CymUogLDjQ6YJhLGvsIOnTEDbogPaTpu3t4KGat SnTkBvPBRBVUakurBALvtWfjomgYaqrjtzNykRyFGgHW4rTwS23jCC57ek/F1a6vNPKn +6kbmSONZh01L47hNg1bddAKsGbFp9CSxobTUXde4liow571aiBG6i3ivmPtVY05mniC S5a8BA1v1R6BW3bSm3D2sDuajn/4B1cd70180bkU7NYYVAX9JZf6vpoI1xHrLEzFUiwh qyZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=abtSJvbP; spf=pass (google.com: domain of libc-alpha-return-91505-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91505-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id e125si1484071pfe.244.2018.04.11.14.16.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 14:16:59 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-91505-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=abtSJvbP; spf=pass (google.com: domain of libc-alpha-return-91505-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91505-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=UdqmnkTR/bsVc9G7vhHCLTa8E0dl0yU M6hc5b7016kIKFuGBSJQ+oNbB+cYWaMcVe8jAkEzFJgJH7ENUlZnSu/w1U+GGEzE oNxMG6vqzY01V9uIwkNtvFn4ze2mFqdUsClzkQT8Rt9JDneBksixDhfko1HB9ARR 2TedDaY7yMTo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=CjPeuyPhHdyXDlC7ZQjByzM44tY=; b=abtSJ vbPIMaDZ+/VRZMHJkj1MmCJLhOyiGbgCFKhhHR8YhhMYIFZJWXpPn+Esp1iyeldo 7CDBa+6C1tKY4EE9ys/JUIsRP7vj5t2HCTOSJs25IgqUinO6SNQ+38lz5IwZX2tQ ZTZ5loGRM9+Q2y39SyXewsk/oES4/F18fWBjPQ= Received: (qmail 118082 invoked by alias); 11 Apr 2018 21:16:33 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 117834 invoked by uid 89); 11 Apr 2018 21:16:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=eor X-HELO: mail-qt0-f181.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=0xt6HHZb6s6E+hJnS8iCVYKgwYg2GnlNDvMxd4DGV/0=; b=t/XR0TuCb7hJi1URrqTxiG/GMBfoFysykCv7WtWxM+3TDl9TCE14sY4dHD4a0BgO+S z65CEXhSFEClhBpAlyQK+Xv/Nl9/FMg11SKS37XGTbzzsd5vlrBBGje85wQPN2ViioCd 23f5J8Bgn/iGWO4ScdgPviUdyoPEFYi/N2iX8kxxegt45VcJnjPRzxDQ0uHqLQshGxAo vS7h2tx613Y0awJwKAdwkgNjdSoIUZRhXVhsPPrnBovN1qVZ/hDnnV0T5aFAm37sgmfL 9Zq2MTkdzCo4E0YC6eaHoWJdsviBci+oNayYVa7HexAvFtBYCsIiwz1SOzgTq5WZ7hlm ZtaQ== X-Gm-Message-State: ALQs6tA7fRI+/eis/lJ9vomkoCA7o+HzXp3rbGEZrrR6oyoHS9kyJ8M+ xrFPkxScphSXX2OfC2oYJ8wEqk/YU5Y= X-Received: by 10.200.7.69 with SMTP id k5mr9924846qth.165.1523481388565; Wed, 11 Apr 2018 14:16:28 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 3/4] arm: Enable ARM mode for armv6 memchr Date: Wed, 11 Apr 2018 18:16:17 -0300 Message-Id: <1523481378-16290-3-git-send-email-adhemerval.zanella@linaro.org> In-Reply-To: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> References: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv6t2 memchr uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Checked on arm-linux-gnueabihf (with -marm -march=armv6t2). * sysdeps/arm/armv6t2/memchr.S (NO_THUMB): Check for __thumb__ instead. --- ChangeLog | 3 +++ sysdeps/arm/armv6t2/memchr.S | 10 +++++----- 2 files changed, 8 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/sysdeps/arm/armv6t2/memchr.S b/sysdeps/arm/armv6t2/memchr.S index bdd385b..03b7f32 100644 --- a/sysdeps/arm/armv6t2/memchr.S +++ b/sysdeps/arm/armv6t2/memchr.S @@ -42,7 +42,7 @@ .syntax unified .text -#ifdef NO_THUMB +#ifndef __thumb__ .arm #else .thumb @@ -91,7 +91,7 @@ ENTRY(memchr) 15: ldrd r4,r5, [r0],#8 -#ifndef NO_THUMB +#ifdef __thumb__ subs r6, r6, #8 #endif eor r4,r4, r1 @ Get it so that r4,r5 have 00's where the bytes match the target @@ -100,7 +100,7 @@ ENTRY(memchr) sel r4, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 sel r5, r4, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION -#ifndef NO_THUMB +#ifdef __thumb__ cbnz r5, 60f #else cmp r5, #0 @@ -120,7 +120,7 @@ ENTRY(memchr) and r2,r2,#7 @ Leave the count remaining as the number after the double words have been done 20: -#ifndef NO_THUMB +#ifdef __thumb__ cbz r2, 40f @ 0 length or hit the end already then not found #else cmp r2, #0 @@ -129,7 +129,7 @@ ENTRY(memchr) 21: @ Post aligned section, or just a short call ldrb r3,[r0],#1 -#ifndef NO_THUMB +#ifdef __thumb__ subs r2,r2,#1 eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub cbz r3, 50f From patchwork Wed Apr 11 21:16:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 133175 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1037614ljb; Wed, 11 Apr 2018 14:17:07 -0700 (PDT) X-Google-Smtp-Source: AIpwx48EUZH0ViGqEvIJRCQWjR8bP+OQVSKJes1RWcRsrs8WbY2ftZYLXxeGoSVoBd+zcElk9tq+ X-Received: by 2002:a17:902:bd03:: with SMTP id p3-v6mr6913042pls.236.1523481427278; Wed, 11 Apr 2018 14:17:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523481427; cv=none; d=google.com; s=arc-20160816; b=q6FBgBnCwfVkpmmpZv0axd70y9zAAttDX1GRJr/Nca56CPVYud0XetKAZ2t4oyRC02 xGeTR68U/3UJl9LN3WcM5aJmZpCr3H0ZEEZn4vxoDehpLl4WRebD60S0BXwo7cnUsa0x jbTUKyOrl+6Fo3Y08UUnS6gsAq0fsv4u4tXcxT7ASTn0XA1Hj9qPtsaHvnn1aaOdKcjW v+C2qTEo486tY1JCcf4TepkNkZrQnsrQ7DYNeidQhFEJH1XJRp3qhWFliFx/Ztd+tdVH 50YmHCpz8ONaPqIly3iXlXKZyyzhAKEN2uXso/Zb2Sr9qQSVE7wsiZzfKr79POCwMcD6 ftCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from:delivered-to :sender:list-help:list-post:list-archive:list-subscribe :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=yI4OijDmohPHDdwCQ1qgbCVd3Lt47FrajgQIGVQrgBU=; b=x9Wr7bh6+bg+ty2aHyKNrq94DOS4OdOmueSmlq4modaugRg4elUICUEesKOx1v2kRq yFmC/EMHdbSgv4/cfdM7Es8B3n2p3gctjHGaXjuT/H6yl4j4Av6n2dZCM51wdWzkg2JC 9uUHPia58OgGrcmIevKzW5M1xdIDE1vOU8a5fzstgS8fvkbcqPOcd4EFhSpiVBTqTt3z ctPbaUKh/oCK+iHiMJNBcOUmijo1pWAIsb0tGE5naoRKYAI0mlSjtZrAlGSZK3DDyGKA HyS8sB/4ExD5k6vKEHbEDf2soRzkuIwAbrTGCDEJp34U9L4zDBPtF/TjMhAsdKdiSnoH aovQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=amqSO+Ta; spf=pass (google.com: domain of libc-alpha-return-91506-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91506-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id b25si1266269pgn.747.2018.04.11.14.17.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 14:17:07 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-91506-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=amqSO+Ta; spf=pass (google.com: domain of libc-alpha-return-91506-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91506-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=rg0zjyjgoJyupR2VQKd43aK5MMh9mp3 V2109N4XGFfFuuUvdSGhm4kIAlIt5UVmtEtc60r9m423JB1Qytq+oiBP862u6YfX bOILNa66oDgDp66uIhIdlqq5mAXAEF3AtfAF63jhfEOPy2RcRE/Q+5MSPb5aCP3t z+DBhNU/ihI8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=Awc7b/g3vhNH/IkAxAhZNCLfsME=; b=amqSO +TaE987CL8a8j4AcQgUDU8MNKwQeP6rP0x0LzQJnSIMIXB1H7/ocjL+A83Xjk8qx S1gwYx8xxPNfwV4lOEFjvkIyGqRifv+90WNyyiWbOjjT+HBPiX8ZzGVOM6auFEeN iff8TmJA3wURN+nCu8Wo96PKeH1ekxGtbmh3IQ= Received: (qmail 118343 invoked by alias); 11 Apr 2018 21:16:34 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 118132 invoked by uid 89); 11 Apr 2018 21:16:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-qk0-f172.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=yI4OijDmohPHDdwCQ1qgbCVd3Lt47FrajgQIGVQrgBU=; b=ne39Y/SJ/3GvB1j00qB3rEJK3BEaBgzUpaBFdLQ19BpZ+NHbzR/oBSYL7z015SYl/u ZHcTzTyy8xqySKyORBXEDMUS+qTH0KwE/d9BWAG/lJ28qujTCEJ/53rc6IFSLgTWdbQ3 h48rQXjHdL4EU7l7TgDk5CQkhCVSZjvJg8VanY24vJJhVO1qJkT/Hf566lRQX3GPkNf4 px0QxeLa6SsFKhUGFbCYFZKJHz6bxCZbamfGTdOrYcn3z3BJvUMO8m4HfZ8dCH3RncTO RozFFEKoiffiD76KRJg/E13DU6BwdA1wdsqivhvRh4H/w8egH/v6XcrH3eU7d7ox/bBz 9rQA== X-Gm-Message-State: ALQs6tBztaKpK+E2DyhQ9BrevEZ3AFxnXTUEmTOT1bOedqmfc6LMhf47 BxFYaaTgipYZAR3UpEkNYKSIn3fUJks= X-Received: by 10.55.76.146 with SMTP id z140mr9569816qka.224.1523481389922; Wed, 11 Apr 2018 14:16:29 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 4/4] arm: Enable ARM mode for armv6 strlen Date: Wed, 11 Apr 2018 18:16:18 -0300 Message-Id: <1523481378-16290-4-git-send-email-adhemerval.zanella@linaro.org> In-Reply-To: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> References: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv6t2 strlen uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Checked on arm-linux-gnueabihf (with -marm -march=armv6t2). * sysdeps/arm/armv6t2/strlen.S (NO_THUMB): Check for __thumb__ instead. --- ChangeLog | 3 +++ sysdeps/arm/armv6t2/strlen.S | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/sysdeps/arm/armv6t2/strlen.S b/sysdeps/arm/armv6t2/strlen.S index 6988183..f4111c3 100644 --- a/sysdeps/arm/armv6t2/strlen.S +++ b/sysdeps/arm/armv6t2/strlen.S @@ -21,7 +21,7 @@ */ -#include /* This might #define NO_THUMB. */ +#include #include #ifdef __ARMEB__ @@ -32,7 +32,7 @@ #define S2HI lsl #endif -#ifndef NO_THUMB +#ifdef __thumb__ /* This code is best on Thumb. */ .thumb #else @@ -146,7 +146,7 @@ ENTRY(strlen) tst tmp1, #4 pld [src, #64] S2HI tmp2, const_m1, tmp2 -#ifdef NO_THUMB +#ifndef __thumb__ mvn tmp1, tmp2 orr data1a, data1a, tmp1 itt ne