From patchwork Sun Feb 28 15:43:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E61EC433E6 for ; Sun, 28 Feb 2021 15:44:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6064E64EB1 for ; Sun, 28 Feb 2021 15:44:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230406AbhB1Po1 (ORCPT ); Sun, 28 Feb 2021 10:44:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230408AbhB1PoZ (ORCPT ); Sun, 28 Feb 2021 10:44:25 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 033B5C061786 for ; Sun, 28 Feb 2021 07:43:45 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id s7so1106840plg.5 for ; Sun, 28 Feb 2021 07:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OhHoaAc908YGCrOivRRjATckooWceYbaO17T4MROb8E=; b=hWTIya6fV8QafabjWHwFKCFrder2AqZhaL9y3XRoT8m+KYpxrofvTyQMW5xMC9D/jf +LFWmV4wh2UQGc5e8FGTUV3uR1GJ2tsZSi/doqlp8YJxks69FeV3hGx13N8+/G12nT0S laBlSYeBJj82znYZoxhH0vhLyOrVAOf/cdjLU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OhHoaAc908YGCrOivRRjATckooWceYbaO17T4MROb8E=; b=ULwig3yHVun0L7v0wOOocS2FaKVRV9Opx6xv6asEWO0xzjEeyAGoC3Pax4gYphFJiD oQsV67Hs/KRiMF9+yCn3FfYSbqDJ8SzL+/33qyNxZhU4tNYGni7axJR6OrWF7tL3XpRu B4hf1EP9EjUyq1cFUkk6r9RIMfQCOLD9p8UMradqa+k6Oc+rR8sAeGEAq2nd3r6qGLdk mOEG2d/b7DwaaNS43VAgyZX3yUKlG+UdANMlnxiWbfZDH25dOFyzSah28znuQJJ/eWSm 2gPY/814nwkfcIc7V4PDRKAxVdOiZ+sbpqrnL1oLBzrjX9ik+YpiNBvMy9K2vzVsC8M4 o9nQ== X-Gm-Message-State: AOAM5317aaidWFj/wYqiL2mHQEP9o00aRqPMTbsRBXjpD2O6YGTn8ls4 sZYWUdaM2T3AR0GWYbJLVUAwTEQY4aVWd2K0 X-Google-Smtp-Source: ABdhPJxYnlP3oakIHukHfbf/OdhxGzvpAbg0ms/Mom97T/YMvB+mEJrLmVG4JMawtHjQkNc2rhtvQg== X-Received: by 2002:a17:902:7286:b029:e3:cec5:f0cb with SMTP id d6-20020a1709027286b02900e3cec5f0cbmr11608677pll.70.1614527024617; Sun, 28 Feb 2021 07:43:44 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:43:44 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 01/10] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 Date: Sun, 28 Feb 2021 21:13:14 +0530 Message-Id: <20210228154323.76911-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. Add bindings for it. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Changes for v3: - updated commit message Changes for v2: - none Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index e7525a3395e5..56b7e0b800b3 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -64,6 +64,13 @@ properties: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + + - description: Engicam MicroGEA STM32MP1 SoM based Boards + items: + - const: engicam,microgea-stm32mp1-microdev2.0 + - const: engicam,microgea-stm32mp1 + - const: st,stm32mp157 + - description: Octavo OSD32MP15x System-in-Package based boards items: - enum: From patchwork Sun Feb 28 15:43:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D58C4C433E0 for ; Sun, 28 Feb 2021 15:44:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3EC264E4A for ; Sun, 28 Feb 2021 15:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230438AbhB1Poc (ORCPT ); Sun, 28 Feb 2021 10:44:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230420AbhB1Poa (ORCPT ); Sun, 28 Feb 2021 10:44:30 -0500 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19B3BC06178A for ; Sun, 28 Feb 2021 07:43:50 -0800 (PST) Received: by mail-pf1-x431.google.com with SMTP id m6so9770705pfk.1 for ; Sun, 28 Feb 2021 07:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d8lgPS/H9UcN3+rMEGcheSYADrMFG557zp/WU7zuATY=; b=ZevkZMuKc2kHRQBdRPmP1lSgBnj4dYd+gpqQ6+pqsg3ErUUfJDOC4QTwuyuJ5DgoDw +kVSWw/GwALM1irm6nvHhsA0Xpv+/QALnkx5cKVucnvQl8NStEF3f+SXAj5h/OYO/mCJ XDZu9/My2Mk6ABpAoEbGG8NMRYhPzGJAGwOas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d8lgPS/H9UcN3+rMEGcheSYADrMFG557zp/WU7zuATY=; b=MCMR6ij1KKkk2XN52K97lCacSr2fX2N/iw5MPEjn+HGmaoTt00SYm+zKT9T2XSIF2C gDa6IX9/DdmYpQnQvfY25GUdTalNb1S8nQvom0OlBO/sXjGFWr+pfQXrSfbu38eThErt ln+bRwFXwDHZ0vTV8g0Kpe7r5kJIUIfPQCepyHiOyCkM4Y3VLQwgH+JaJLoE0vswU4t4 nN7wniU4NmoJbnt2+DZSBdpq1hYIWBkJ1ynj0go8AfMmi/tR2voHcN5Mraqs4pthA0xr NS8f6pBRZWV4FCPMW7Gme/4kuFParG+ivIkGIyU6M9GO4QYGl6h6pV474a5M8mX9JGsZ KedQ== X-Gm-Message-State: AOAM531jmPMAshsBSoHuKMSubRNwjUXPpKSmsJYxIlDdjYRiuALYKp54 XiXMzVZZsGoTHmSxyVA5+GQbHg== X-Google-Smtp-Source: ABdhPJzzru+AGTbE3uVaLrzySHKIxOD7dK4JNlZ2TR5iSmanm+uWYbh3+78UNUOuKWb2QgVbCqgfrA== X-Received: by 2002:a63:c10:: with SMTP id b16mr10642346pgl.326.1614527029694; Sun, 28 Feb 2021 07:43:49 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:43:49 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki , Matteo Lisi , Francesco Utel , Mirko Ardinghi Subject: [PATCH v3 02/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM Date: Sun, 28 Feb 2021 21:13:15 +0530 Message-Id: <20210228154323.76911-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. General features: - STM32MP157AAC - Up to 1GB DDR3L-800 - 512MB Nand flash - I2S MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier boards for creating complete platform solutions. Add support for it. Signed-off-by: Matteo Lisi Signed-off-by: Francesco Utel Signed-off-by: Mirko Ardinghi Signed-off-by: Jagan Teki --- Changes for v3: - add device_type - updated commit message Changes for v2: - none .../dts/stm32mp157a-microgea-stm32mp1.dtsi | 148 ++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi new file mode 100644 index 000000000000..0b85175f151e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,microgea-stm32mp1", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddcore: regulator-vddcore { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <&vin>; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vin>; + }; + + vddq_ddr: regulator-vddq-ddr { + compatible = "regulator-fixed"; + regulator-name = "vddq_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vin>; + }; +}; + +&dts { + status = "okay"; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "okay"; + + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2{ + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; From patchwork Sun Feb 28 15:43:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C870C433DB for ; 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Sun, 28 Feb 2021 07:43:54 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:43:54 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki , Matteo Lisi , Francesco Utel , Mirko Ardinghi Subject: [PATCH v3 03/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board Date: Sun, 28 Feb 2021 21:13:16 +0530 Message-Id: <20210228154323.76911-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. Genaral features: - Ethernet 10/100 - USB Type A - Audio Out - microSD - LVDS panel connector - Wifi/BT (option) - UMTS LTE with sim connector (option) MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. Add support for it. Signed-off-by: Matteo Lisi Signed-off-by: Francesco Utel Signed-off-by: Mirko Ardinghi Signed-off-by: Jagan Teki --- Changes for v3: - updated commit message Changes for v2: - don't create carrier board dtsi, add it in final dts. arch/arm/boot/dts/Makefile | 1 + ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 55 +++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9f9f3e49132a..b4a9cd071f99 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ stm32mp157a-iot-box.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts new file mode 100644 index 000000000000..7a75868164dc --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-microgea-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board"; + compatible = "engicam,microgea-stm32mp1-microdev2.0", + "engicam,microgea-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&vdd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +/* J31: RS323 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; From patchwork Sun Feb 28 15:43:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71396C433E6 for ; Sun, 28 Feb 2021 15:45:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39D1864E4A for ; Sun, 28 Feb 2021 15:45:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230510AbhB1PpK (ORCPT ); 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Sun, 28 Feb 2021 07:43:58 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki , Rob Herring Subject: [PATCH v3 04/10] dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF Date: Sun, 28 Feb 2021 21:13:17 +0530 Message-Id: <20210228154323.76911-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. 7" OF is a capacitive touch 7" Open Frame panel solutions. MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" Open Frame Solution board. Add bindings for it. Acked-by: Rob Herring Signed-off-by: Jagan Teki --- Changes for v3: - updated commit message Changes for v2: - collect a-b Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 56b7e0b800b3..255d3ba50c63 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -67,7 +67,9 @@ properties: - description: Engicam MicroGEA STM32MP1 SoM based Boards items: - - const: engicam,microgea-stm32mp1-microdev2.0 + - enum: + - engicam,microgea-stm32mp1-microdev2.0 + - engicam,microgea-stm32mp1-microdev2.0-of7 - const: engicam,microgea-stm32mp1 - const: st,stm32mp157 From patchwork Sun Feb 28 15:43:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFB29C433E6 for ; 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Sun, 28 Feb 2021 07:44:04 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:44:03 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki , Matteo Lisi , Francesco Utel , Mirko Ardinghi Subject: [PATCH v3 05/10] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF Date: Sun, 28 Feb 2021 21:13:18 +0530 Message-Id: <20210228154323.76911-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 7" OF is a capacitive touch 7" Open Frame panel solutions with - 7" AUO B101AW03 LVDS panel - EDT, FT5526 Touch MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" Open Frame Solution board. Add support for it. Signed-off-by: Matteo Lisi Signed-off-by: Francesco Utel Signed-off-by: Mirko Ardinghi Signed-off-by: Jagan Teki --- Changes for v3: - updated commit message Changes for v2: - don't create carrier board dtsi, add it in final dts. arch/arm/boot/dts/Makefile | 1 + ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b4a9cd071f99..1332622a3f9f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1072,6 +1072,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-dk1.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts new file mode 100644 index 000000000000..674b2d330dc4 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-microgea-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame"; + compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", + "engicam,microgea-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + serial1 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + default-on; + }; + + lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + power-supply = <&panel_pwr>; + }; + + panel_pwr: regulator-panel-pwr { + compatible = "regulator-fixed"; + regulator-name = "panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + panel { + compatible = "auo,b101aw03"; + backlight = <&backlight>; + enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; + power-supply = <&lcd_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; +}; + +&i2c2 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; +}; + +<dc { + pinctrl-names = "default"; + pinctrl-0 = <<dc_pins>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pinctrl { + ltdc_pins: ltdc { + pins { + pinmux = , /* LTDC_B2 */ + , /* LTDC_R6 */ + , /* LTDC_R5 */ + , /* LTDC_B3 */ + , /* LTDC_B0 */ + , /* LTDC_G0 */ + , /* LTDC_G1 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_CLK */ + , /* LTDC_B1 */ + , /* LTDC_R0 */ + , /* LTDC_R1 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G3 */ + , /* LTDC_G4 */ + , /* LTDC_G5 */ + , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B4 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_VSYNC */ + ; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&vdd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +/* J31: RS323 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; From patchwork Sun Feb 28 15:43:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07C16C433E0 for ; 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Sun, 28 Feb 2021 07:44:08 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:44:08 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 06/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 Date: Sun, 28 Feb 2021 21:13:19 +0530 Message-Id: <20210228154323.76911-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. i.Core STM32MP1 needs to mount on top of this Carrier board for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. Add bindings for it. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Changes for v3: - none Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 255d3ba50c63..3e45516403ce 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -65,6 +65,12 @@ properties: - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: Engicam i.Core STM32MP1 SoM based Boards + items: + - const: engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM + - const: st,stm32mp157 + - description: Engicam MicroGEA STM32MP1 SoM based Boards items: - enum: From patchwork Sun Feb 28 15:43:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D117C433DB for ; Sun, 28 Feb 2021 15:45:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6E1A264E4A for ; Sun, 28 Feb 2021 15:45:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230521AbhB1PpY (ORCPT ); Sun, 28 Feb 2021 10:45:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231133AbhB1PpS (ORCPT ); Sun, 28 Feb 2021 10:45:18 -0500 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB1A5C061356 for ; Sun, 28 Feb 2021 07:44:12 -0800 (PST) Received: by mail-pg1-x534.google.com with SMTP id n10so9796370pgl.10 for ; Sun, 28 Feb 2021 07:44:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J+tLTcgEC7NuZoaHUtchsSbxzlGgEOMmhAAuknqUUUU=; b=rx4ROMwIEp314rdXOpwVr1WQ7G/EqCyB1/1vZNPqyv4lTuFwebnPAe09jle/CqkGjw uFCPjonWBETPqE9GICTPJ4/MbCXIpl1qnFKUMrvuRBWWi1tP35gSnNV+56vj8KdbRgVM J4mUwxzaeKGLd5n1MkgAIMDGzxZDXCpllib1M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J+tLTcgEC7NuZoaHUtchsSbxzlGgEOMmhAAuknqUUUU=; b=sL4luE1RXuzWC5bj6DHLbkGif7EOZ7RosYRYo8RyhBq+sYitZbdtr25dqSv1xhbO37 I7M1mFKDVvQkutc33aMQwiFO4JZtrrQC4cRjXrFArkM7lO4Z+B56WzA2Hb6LaRFmXkPY E69Zw+mLHg3c5/ZQyyfsyM7khdOfOh19Fw1inERygdK7S9h0fnKfrP5mTsbSI2XLFN9o 9YqE7pKYdyi0WvW/GuBJFjxZkCHRaaXfTpNkJNBz9ikMtM0E3hKygD4qwmhiYnpNcWTz GMU/yuTsGpCrQWT/wrGICiKGjX4e6BHDX9xJGlZZ0hQp7JwkhlxyJQhdYlYQXBtPnL+R uQ6Q== X-Gm-Message-State: AOAM533MEGVjtxEbZqoXxvl3v88K05UgLR6wbgeIKMuD+hKTRFLx7tsR kkMm+UcUwnV86kJpoGjRtISKUw== X-Google-Smtp-Source: ABdhPJzlSS9w7YsKCT9U8IESeZc3nqXf3LWJcsI7p60fO8anMofol3oH/hpeRLOVghHS5x5zYjpkcQ== X-Received: by 2002:a05:6a00:22ca:b029:1ed:f915:ca98 with SMTP id f10-20020a056a0022cab02901edf915ca98mr11319685pfj.68.1614527052458; Sun, 28 Feb 2021 07:44:12 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:44:12 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 07/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM Date: Sun, 28 Feb 2021 21:13:20 +0530 Message-Id: <20210228154323.76911-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. General features: - STM32MP157A - Up to 1GB DDR3L - 4GB eMMC - 10/100 Ethernet - USB 2.0 Host/OTG - I2S - MIPI DSI to LVDS - rest of STM32MP157A features i.Core STM32MP1 needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Jagan Teki --- Changes for v3: - add device_type .../boot/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 ++++++++++++++++++ 1 file changed, 196 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi new file mode 100644 index 000000000000..01166ccacf2b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,icore-stm32mp1", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + vddcore: regulator-vddcore { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_usb: regulator-vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_ddr: regulator-vdd-ddr { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vtt_ddr: regulator-vtt-ddr { + compatible = "regulator-fixed"; + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + regulator-always-on; + vin-supply = <&vdd>; + }; + + vref_ddr: regulator-vref-ddr { + compatible = "regulator-fixed"; + regulator-name = "vref_ddr"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <675000>; + regulator-always-on; + vin-supply = <&vdd>; + }; + + vdd_sd: regulator-vdd-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2v8: regulator-v2v8 { + compatible = "regulator-fixed"; + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + v1v8: regulator-v1v8 { + compatible = "regulator-fixed"; + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; +}; + +&dts { + status = "okay"; +}; + +&i2c2 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <185>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2{ + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc{ + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc{ + status = "okay"; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; From patchwork Sun Feb 28 15:43:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE6A7C433E0 for ; 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Sun, 28 Feb 2021 07:44:16 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:44:15 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 08/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 Date: Sun, 28 Feb 2021 21:13:21 +0530 Message-Id: <20210228154323.76911-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. i.Core STM32MP1 needs to mount on top of this Carrier board for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki --- Changes for v3: - none arch/arm/boot/dts/Makefile | 1 + .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 47 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1332622a3f9f..6dc39bddaf7e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1073,6 +1073,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-iot-box.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts new file mode 100644 index 000000000000..d3058a036c74 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 C.TOUCH 2.0"; + compatible = "engicam,icore-stm32mp1-ctouch2", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; From patchwork Sun Feb 28 15:43:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28019C433E6 for ; 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Sun, 28 Feb 2021 07:44:20 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:44:20 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 09/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit Date: Sun, 28 Feb 2021 21:13:22 +0530 Message-Id: <20210228154323.76911-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. i.Core STM32MP1 needs to mount on top of this Evaluation board for creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. Add bindings for it. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Changes for v3: - none Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 3e45516403ce..01f595b8ae1b 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -67,7 +67,9 @@ properties: - description: Engicam i.Core STM32MP1 SoM based Boards items: - - const: engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - enum: + - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM - const: st,stm32mp157 From patchwork Sun Feb 28 15:43:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 388502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42F56C433E0 for ; Sun, 28 Feb 2021 15:45:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2139F64EB3 for ; Sun, 28 Feb 2021 15:45:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231164AbhB1Ppj (ORCPT ); Sun, 28 Feb 2021 10:45:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231158AbhB1Pp3 (ORCPT ); Sun, 28 Feb 2021 10:45:29 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28917C061224 for ; Sun, 28 Feb 2021 07:44:25 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id c19so9299115pjq.3 for ; Sun, 28 Feb 2021 07:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P8xuLB+PW3vzd/2H+nv/FYwlg2xPXL9X/0ZCidUY03A=; b=GTHfepeMME8ETHJ9D17UUQlIWYTFf4lYClQwCQIUOC1oKAGJgzR3euzonM0vWhJci7 TSppLrKhyfNsWCsXIJqzg5FXr0v1J95UnRMiUrzOyX8byY+RtVKhUubnX9B9qNo442jJ Fnnv6pSzMiAS8udimqeZ651R7iVF1iwjSC0cY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P8xuLB+PW3vzd/2H+nv/FYwlg2xPXL9X/0ZCidUY03A=; b=imWWxPPEtORXpR4zoFtn79Bbn8UdG2MDBBekYmg2flgDZyAup/JQwDFPFJj5LcfzpK HpKIO5I3uut82IwdZb1TW1LTaOPJIcYKVydbIhezLH9OmUpqtTaIhgKMHNwD8W1zHo+g udIpaqzeuwB/F4Bi2telVWJN5+TanBaRUaXoqV0YibZAWFQGgMNAdvPaNB3BrD9oo8F4 SXYg5VMCDOjd0w1AIdMgSVEJaZRsPGVoRLPZmEt7igo9F385G7fYMwK/xQNqf+pmoqqz DTvcwT+tQ1mfEwbyf9gltGonWZVYztVF5aZXJPhe3KxFKXT1IcnwxkqRUgJVHRByO7ER TdPw== X-Gm-Message-State: AOAM530vQWjL39yD7YSdgz+KxTwv/vJo6mAqcDmwXJOmM8O9rFnU3PDH U7mmv153G49SkIwR311xH6lbgw== X-Google-Smtp-Source: ABdhPJxfIBewbERSLjK/TGwJqJEMQTPLphwQZKKTzUvXvWHtlP24xZS8O3qwJbFmLnm3mZesUyhs+g== X-Received: by 2002:a17:903:1cc:b029:de:98bb:d46d with SMTP id e12-20020a17090301ccb02900de98bbd46dmr11601415plh.54.1614527064698; Sun, 28 Feb 2021 07:44:24 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.225]) by smtp.gmail.com with ESMTPSA id j3sm13522133pgk.24.2021.02.28.07.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 07:44:24 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 10/10] ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit Date: Sun, 28 Feb 2021 21:13:23 +0530 Message-Id: <20210228154323.76911-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228154323.76911-1-jagan@amarulasolutions.com> References: <20210228154323.76911-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. i.Core STM32MP1 needs to mount on top of this Evaluation board for creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki --- Changes for v3: - none arch/arm/boot/dts/Makefile | 1 + .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 47 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6dc39bddaf7e..e86c46d7ca66 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1074,6 +1074,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts new file mode 100644 index 000000000000..ec9f1d1cd50f --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) STMicroelectronics 2019 - All Rights Reserved + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp157a-icore-stm32mp1.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include + +/ { + model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit"; + compatible = "engicam,icore-stm32mp1-edimm2.2", + "engicam,icore-stm32mp1", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdmmc1 { + bus-width = <4>; + disable-wp; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + st,neg-edge; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +};