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[209.132.180.67]) by mx.google.com with ESMTP id i4si1830233plk.335.2017.04.06.06.17.08; Thu, 06 Apr 2017 06:17:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934759AbdDFNRG (ORCPT + 14 others); Thu, 6 Apr 2017 09:17:06 -0400 Received: from mail-pg0-f54.google.com ([74.125.83.54]:34898 "EHLO mail-pg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934715AbdDFNQe (ORCPT ); Thu, 6 Apr 2017 09:16:34 -0400 Received: by mail-pg0-f54.google.com with SMTP id 81so36234364pgh.2 for ; Thu, 06 Apr 2017 06:16:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bqJHojYH4zH27VAYD/IIz6NoUGefaNIbta7z6UHc7+U=; b=NPQMI8quWCH4Pd1kKt4zUd5NuxIUwkmM5CG8Oif6s0RO9hi2bI76AhjankOfLQvcoI +Xag+q+kq4kQ6y622yMgAfbVGvdIKShd9Fb3qWzOQgqdS/1QSYH3aloL1JiucTh3EtAf QMCGYlIfThJQdpCqWEMGiLQAqL1G5LGR7+lBM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bqJHojYH4zH27VAYD/IIz6NoUGefaNIbta7z6UHc7+U=; b=DOnLYmZBECjgjfoJG599Q2P/gb3gVF5kPuJKv+l+22m2jgiVU7KqQEF4zsSZ+J2Srk B7sAk40zAWzdhQs9DwwKphVx2yTMzWzks2N3c4c+tYjMBGz3UfH2glg67ZF63kMJF1D3 1ZnWu5tt/FzEWlCqRbF83MsWGJhE38azdz1WomEuq5FFAH24XS+/xF86GZ90fO2mGlu6 epDfzvFyo0bq1jjilRacZrNYfE+G7FLtuNaAVj6QRY2hdFwuL3sTaA/szIEjb4l0S5qD dDOGxFES8/DxQMrlEH2+2lyfoJdcpxqNgABa9E74U8xdzgb2jDRoW7y5wm96Mm+KX8Tg MMZg== X-Gm-Message-State: AFeK/H2l5SVU+SvrOlO4rp+utKSRJQN1M4xHCaUYV4A6hCb7Lwxs/1axbxcmroemXXPO2dV/ X-Received: by 10.99.56.66 with SMTP id h2mr27611466pgn.40.1491484593106; Thu, 06 Apr 2017 06:16:33 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:32 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paul Burton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.9 4/7] MIPS: Switch to the irq_stack in interrupts Date: Thu, 6 Apr 2017 18:46:10 +0530 Message-Id: <1491484573-6228-5-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matt Redfearn When enterring interrupt context via handle_int or except_vec_vi, switch to the irq_stack of the current CPU if it is not already in use. The current stack pointer is masked with the thread size and compared to the base or the irq stack. If it does not match then the stack pointer is set to the top of that stack, otherwise this is a nested irq being handled on the irq stack so the stack pointer should be left as it was. The in-use stack pointer is placed in the callee saved register s1. It will be saved to the stack when plat_irq_dispatch is invoked and can be restored once control returns here. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14743/ Signed-off-by: Ralf Baechle (cherry picked from commit dda45f701c9d7ad4ac0bb446e3a96f6df9a468d9) Signed-off-by: Amit Pundir --- arch/mips/kernel/genex.S | 81 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index dc0b296..0a7ba4b 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -187,9 +187,44 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - PTR_LA ra, ret_from_irq - PTR_LA v0, plat_irq_dispatch - jr v0 + + /* + * SAVE_ALL ensures we are using a valid kernel stack for the thread. + * Check if we are already using the IRQ stack. + */ + move s1, sp # Preserve the sp + + /* Get IRQ stack for this CPU */ + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(irq_stack) +#else + lui k1, %highest(irq_stack) + daddiu k1, %higher(irq_stack) + dsll k1, 16 + daddiu k1, %hi(irq_stack) + dsll k1, 16 +#endif + LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_ADDU k1, k0 + LONG_L t0, %lo(irq_stack)(k1) + + # Check if already on IRQ stack + PTR_LI t1, ~(_THREAD_SIZE-1) + and t1, t1, sp + beq t0, t1, 2f + + /* Switch to IRQ stack */ + li t1, _IRQ_STACK_SIZE + PTR_ADD sp, t0, t1 + +2: + jal plat_irq_dispatch + + /* Restore sp */ + move sp, s1 + + j ret_from_irq #ifdef CONFIG_CPU_MICROMIPS nop #endif @@ -262,8 +297,44 @@ NESTED(except_vec_vi_handler, 0, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - PTR_LA ra, ret_from_irq - jr v0 + + /* + * SAVE_ALL ensures we are using a valid kernel stack for the thread. + * Check if we are already using the IRQ stack. + */ + move s1, sp # Preserve the sp + + /* Get IRQ stack for this CPU */ + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(irq_stack) +#else + lui k1, %highest(irq_stack) + daddiu k1, %higher(irq_stack) + dsll k1, 16 + daddiu k1, %hi(irq_stack) + dsll k1, 16 +#endif + LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_ADDU k1, k0 + LONG_L t0, %lo(irq_stack)(k1) + + # Check if already on IRQ stack + PTR_LI t1, ~(_THREAD_SIZE-1) + and t1, t1, sp + beq t0, t1, 2f + + /* Switch to IRQ stack */ + li t1, _IRQ_STACK_SIZE + PTR_ADD sp, t0, t1 + +2: + jal plat_irq_dispatch + + /* Restore sp */ + move sp, s1 + + j ret_from_irq END(except_vec_vi_handler) /*