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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 1/8] RISC-V: Enable CPU_IDLE drivers Date: Sun, 21 Feb 2021 15:07:51 +0530 Message-Id: <20210221093758.210981-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:38:30 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: e4b777bc-c42c-40e8-741a-08d8d64c7633 X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: h8LhvY7TOTKBXAfWbxKBvI2EgUW/yWyK2KUO+3cZQhal3RXPmnXrzOnOysDHG7iELeUOrSB2BWKpzwc51uuxYpK+9iJ7Qpy/82W9Y6TOWB62opJrn9kz7W/37EJoGbN8whhh1tEKUYa4glUmgDmqLyLF+1qMQdsKo8dU0ys514ox/WetJKpg0E3pUEY2RmxanHJ0m04xWZccvz9DnlMZ/g4I2h2+LamI4LDHyQ6iQHWyvfIQe81BiyrrB/TDYfGqklNc6KC0eZYWy48a8LrwftHboci7dysB1tLYZeRxwzPwst1tLIMPb1Og12yaWOvo3w334CwhFKV+gy8Tq3lQWwhTINAjxuE7kfZm4184yulOhH7BkpuzrL+iOAANgfAyhw076Fr+UDYWgwn/orCsus3YbPOY5ytHuhlQnFa4AuZKqLBAtL+6LS9BwhZ9N9eGJ8Q/jeaaowv67o6sM4x6UFURKBvlMmgLQ9aBR5N5yfnfymkIjYvqJEj3F57spmI9XeCU7CihcUbxilL95xrwoA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(5660300002)(54906003)(110136005)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: RUZAMJOXJDMqTCkCKvsiB294w5bocfbScPvqpg59jA82hm1YHeqLTR9YNEZZAyslXB1q6tBJVgs5oZxyZYTv8785hcjnILCYZ1s6Brgq2fQAQq90cmlaIgPc5qJP5sOafdDOvDuNLYeEguog//U2v5JmyJZsF+F3+VYkXLG5vhrwPdU9DUBWfWynzHCwzMWdyIJ6F9neF8hoZjxsoo9lMOuVofgUDj0cmi0+EG1NSoI8sBmYjT5bzW8qEOViIN5BWPMWyfB7oIxN0kGF0475j4QT7aCbsV2SwwIVb1Z3m+riNL33oZdJmcr7cDE4teja0KIjmuKnVG543kGp0kEYJg8wY2nYsyGzTdBds6+qwn3Hb2WqH8bcRQAR6/5YiDf+Ude+cICQMKB80xfHKwMRxzIMkxaRSHVlxHxEy3z3EC93SV1yeiGWMGtF+6Jgq5zDoGCmMzyCzw/KdVynuY/Ga0GRjK34TqcAL1qqnjMVYyXOn45aulO8InzGjFCfivAIhu5wYa9UIgD5C+OAs/uAbHEf7MO7cji3r4bNSQXgNtfT6kmeGy88I5Q6jUEiJ9uduflKNgIsksv//43kXgToEcgmDjI0lFPB+oVFTMi8rkEinjUkx3vszXYi8xFP5aNzqtwd1lwRk29nPMRyQlA16RxFoIa5tn/Glbl2dJaQafY/JYyS7X8NpKPdzZZHnvtrXPDnKHPtIjFND5mV2n9LCtboZl9zfAjwDYUK4ERFjg5qGg/rJ1ha3klTjoIpYfxtdqdU4ILgTqO8cLLzTnS4RlwCrSXpeOJaYSqnTDQjAr57oKqFBAC34FSlkkZxVhfYsaMWWtAJmIFEMtvmj7zcSqoUPni4VRCbyM3MlpfR1JcJIXNR248H1SaI7TCIGPpnKXDVZw5V/fw6m3enxg2QokhwMmdRSEWCzqI9X+JNJmZfeMZ8tt01AdcM6S/sPlhIc67ksOngXcAvjP91OsuWTZCoOiSlxdGXPtm3GL+Zw0x0p3mVzH4dGPcHpvMtAuwgtVfhri+QqW/JrjtORVBb/q8itA12aldejMee2iS0D5AjyBMJEATa6PXfPLx1iQKu4i8yxrcHu1XMdhxQI7jE6bfQOBd3PBTaC1UNVoedAHt/6xA+sSheqHfl/w68KcWrzMtHdo0D3Ptu39bbb2ORoOMiB2Sh8z+FeVUuykaaKEzjHjtvW0rhjTUvB2S+9Njm0DR9Gqf8kreNTTPyF+EBbRq6/aM68q2+wqtrwqRyklMTpl10aXND0farTpqpM/Jh8tHPs0aYhL2d1hYu0uIVahzvznPGj/95Dy/UF52FpJD4zkzfAZeBy+X3t6d0jxs2 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: e4b777bc-c42c-40e8-741a-08d8d64c7633 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:38:36.3416 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: o9rQAC9iDfHtUEHJid+/+KyKgp7HAFJA9UX0/Rgevu8s0VD2Jd0YNW4f5UEtH0zn7b92JoLXvf+P7rCI42kWmw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We force select CPU_PM and provide asm/cpuidle.h so that we can use CPU IDLE drivers for Linux RISC-V kernel. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/configs/defconfig | 7 +++---- arch/riscv/configs/rv32_defconfig | 4 ++-- arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++ arch/riscv/kernel/process.c | 3 ++- 5 files changed, 38 insertions(+), 7 deletions(-) create mode 100644 arch/riscv/include/asm/cpuidle.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fe6862b06ead..4901200b6b6c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -37,6 +37,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK + select CPU_PM if CPU_IDLE select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT @@ -430,4 +431,10 @@ source "kernel/power/Kconfig" endmenu +menu "CPU Power Management" + +source "drivers/cpuidle/Kconfig" + +endmenu + source "drivers/firmware/Kconfig" diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 6c0625aa96c7..dc4927c0e44b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -13,11 +13,13 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -65,10 +67,9 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_SPI=y CONFIG_SPI_SIFIVE=y +# CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIOLIB=y CONFIG_GPIO_SIFIVE=y -# CONFIG_PTP_1588_CLOCK is not set -CONFIG_POWER_RESET=y CONFIG_DRM=y CONFIG_DRM_RADEON=y CONFIG_DRM_VIRTIO_GPU=y @@ -132,5 +133,3 @@ CONFIG_DEBUG_BLOCK_EXT_DEVT=y # CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y -# CONFIG_SYSFS_SYSCALL is not set -CONFIG_EFI=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 8dd02b842fef..332e43a4a2c3 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -13,12 +13,14 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -67,7 +69,6 @@ CONFIG_HW_RANDOM_VIRTIO=y CONFIG_SPI=y CONFIG_SPI_SIFIVE=y # CONFIG_PTP_1588_CLOCK is not set -CONFIG_POWER_RESET=y CONFIG_DRM=y CONFIG_DRM_RADEON=y CONFIG_DRM_VIRTIO_GPU=y @@ -131,4 +132,3 @@ CONFIG_DEBUG_BLOCK_EXT_DEVT=y # CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y -# CONFIG_SYSFS_SYSCALL is not set diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h new file mode 100644 index 000000000000..1042d790e446 --- /dev/null +++ b/arch/riscv/include/asm/cpuidle.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Allwinner Ltd + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_CPUIDLE_H +#define _ASM_RISCV_CPUIDLE_H + +#include +#include + +static inline void cpu_do_idle(void) +{ + /* + * Add mb() here to ensure that all + * IO/MEM access are completed prior + * to enter WFI. + */ + mb(); + wait_for_interrupt(); +} + +#endif diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index dd5f985b1f40..b5b51fd26624 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -21,6 +21,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -35,7 +36,7 @@ extern asmlinkage void ret_from_kernel_thread(void); void arch_cpu_idle(void) { - wait_for_interrupt(); + cpu_do_idle(); raw_local_irq_enable(); } From patchwork Sun Feb 21 09:37:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 386009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF9F3C433DB for ; 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 2/8] RISC-V: Rename relocate() and make it global Date: Sun, 21 Feb 2021 15:07:52 +0530 Message-Id: <20210221093758.210981-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:38:36 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c361fe70-97ca-4ad6-1423-08d8d64c79b6 X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nKoL4Fy4uw2LW2LJHkImi70uve6kp0RGBC6f24mUXBgNUaKUBdPXnD8f6NQijaUiTknq9wdrj1NfgPX1jHKHvyFndbODNarBgOrVL0tnzxBkh3JW0/IJ+xxw4s8a5o8l48xfZP78tbK0VlHIfGWcy7P565g7tAmgAKYaP2Ilqv6ViTce1DByzSW7OBul8ZjkC0Nnkr7FkiAK/R1TR7nIu2MzuzaHV51K71pI398rMsdsOBjWNk2ryUiFiQR0DkXs1aYip8jWb2LdgcQ6akawoQHvB0G7Al3RLaa83gULfwa338iJceLsgSJokQ3kQqawRquRlUeGWmSIPh2gt0oSMdLXZpZB+8YitZd6vA8tQrmRKGHe9vIhqA54uq1++7mKhGvh3g5BctxH/BdEXayVe66Jls7r2R4YJxi3Sr7l0huOl547rAKwF1WZot82v6CS6zcRPPA8gxekqQgvebDxe+KWuQBdSdECrOXkMgpCrDdiZoE8hoAedVyauoKED2smFL7rcRtN1K6Mw2yzOz6t4Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(5660300002)(54906003)(110136005)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: R7Hsp9XJ4IwdR3HQJKoay7z0bKBDNi3SyAbcg9Nelmb9MLK4vJV/ilsbLIrYKrMoagjOl3IRJ2l/wDJqBox4NxV0j1DpmvEpLeKwZIazAmhDiGoeukoDObDq05SDipXbcm5jnrwqEoHE7ZxxPZKpvVqltgUaHjwYafIQkdHHzxsN4XJCj8PYWOJNLu3uF9ldywcrCmkkXKgcj0uZhkGoUbmmQT/iOuMjv1J5EfSHzd8aLFDbhd3oCbnZaKFQR9/YHVdI5Q0/OHskD0Ny3cyx80t1uwDO3s17dRxpuKvJJ+7G1QQZLqVU86q7prwa6ZmPpQf/Apl9UFxNKhc/6gS9q32dzAwcIIe48+w+ETLMOjU7eIxNUUbjLeX5t6wsc9ALwiUysHlYZNyZcJnda5q7k5azgFjQydfuhFGagl0VwASmmlI8h3gRvdoSPYR/+YYKSVtQm0DZc/w2frg5cYrsgnelhxj1DY78WbPkyeRLS+POFrNS/NehyU1dX1tR11zEiHryuGFpetAI4vl2vq53ac3FnI+NjiluJzU6Xnv9dyzZiZCbQq37GessBIoIzJoLXzR5Xn8dlHKvfznWJW5MbXUGvvgOc1/YMFIHtgYrKbGzuqM86N1TSCwnTXRNctaj1kJM9eKYuQi76iB+pAAd74ax+VTCuFWSDRy9AZNj22QE58G/cTK2OkN8k3aWDDxWqM2s0QIZ+j9Kuxci7etGcjkR0lG86o2evKfuLrlsd5nM0QFKLwRso7UIo0qRj3HSatijth7f7qVoidLeiFLz8KLiFxTjr8v+TCDDIEIWddmUEq1xpRO4JYUrsKSJHTRVilVhu93US97+M7u45eV7VnJYZBcnzpns7Ive1uMHKcgcHdCa9r8jjiPha/FBN9l9Or9yqF6CmPLlJDTPUWFXrRg8HzclobTP8iGJOGFoteSno/LIYU2E04T9DP9pTG5CawDgGJJRrIX4EaMSZHrv9bGpOoPdEuaIOpgCH37GNUEVgmsC4lYN6nkOXZRYyAxW1VS9RVPQw9FN7F6SPSXep67Pd2DI1CA9l9Br5H44nKi9z1OPZCWfofG+quaoKFCYFfvy1lA5zERtoBljC7NDg+Z23XhxKfZf6iJbL9jJZP04p03fX7Smok36a6Bu8eL6KBqlaBqWITAjaMx8w3/H/2DMTny2sF8ljzwVBKY+A2OAVnaO5wE6uAoFaH0kW+L2Yz2AYjdzlRytEhdKI6ASi4KAC2iwILq5eHstZN7Q2p032EVc1Ug35V7kvqekkjShqsYZJSc/5HeDXcxHFvzwcUeh7nRsirY5J0ogKW00MDPyx7NpAkW/l5iuMPCqJv8g X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: c361fe70-97ca-4ad6-1423-08d8d64c79b6 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:38:42.4856 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1i9RUUV8wbeGn0Z6PfVttWmLVFP7MTzQ7WD+nyETz8I6OTgXx1Umsa7a/GbwipcwJQG138QnicjCOqjBuuRnlg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The low-level relocate() function enables mmu and relocates execution to link-time addresses. We rename relocate() function to relocate_enable_mmu() function which is more informative. Also, the relocate_enable_mmu() function will be used in the resume path when a CPU wakes-up from a non-retentive suspend so we make it global symbol. Signed-off-by: Anup Patel --- arch/riscv/kernel/head.S | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 16e9941900c4..a8aca43929d8 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -67,7 +67,8 @@ pe_head_start: .align 2 #ifdef CONFIG_MMU -relocate: + .global relocate_enable_mmu +relocate_enable_mmu: /* Relocate return address */ li a1, PAGE_OFFSET la a2, _start @@ -156,7 +157,7 @@ secondary_start_common: #ifdef CONFIG_MMU /* Enable virtual memory and relocate to virtual address */ la a0, swapper_pg_dir - call relocate + call relocate_enable_mmu #endif call setup_trap_vector tail smp_callin @@ -264,7 +265,7 @@ clear_bss_done: call setup_vm #ifdef CONFIG_MMU la a0, early_pg_dir - call relocate + call relocate_enable_mmu #endif /* CONFIG_MMU */ call setup_trap_vector From patchwork Sun Feb 21 09:37:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 385653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 419F6C433E6 for ; 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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM5PR04MB0459.namprd04.prod.outlook.com (2603:10b6:3:9d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.25; Sun, 21 Feb 2021 09:38:48 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868%7]) with mapi id 15.20.3868.029; Sun, 21 Feb 2021 09:38:48 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 3/8] RISC-V: Add arch functions for non-retentive suspend entry/exit Date: Sun, 21 Feb 2021 15:07:53 +0530 Message-Id: <20210221093758.210981-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:38:42 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6bc29b22-c57a-46ef-b957-08d8d64c7d61 X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TLiNgF9/xMoOQ50kFAPBQbvoaj6BtoTD87eYcPed6T+QFG9bleEWP085JkSlo1nYCOiIsiwEhKTHM3CxaLNi25oxnZeKed4W+52Q3vU9Ku9hOcFkoD4Su9VYh5Mgkgzyk7IpdmbgabCwGWF9+I4GPjVZxOZu4xh09scCAqc4Kg34uvgtHCvHp3pYHa+WHb4m9ij6iifAGoosWGxu6UTpff+frKl0b+NjWL94of72rk5mUfNHtLST6rQUbyzF5+UP0+g4w2QE7NaVuUDE2flQdWJI4005Hgwq5ETr9xyognclX5ej8o1QE2dJJwAV4uTc5uJe7RzXYzZoM0MK3Y0Fmf+tpaWlot0GISFAP12m6u4z0zjeB7xj6Rq7GeyRe4n8x8mOfSrKAL/TKPlBKR2jNDgH5tc4mW2ZtTDnabQgYKFcxXYok5nLrkcIC9Ozhl54EnYV24AxBJ2tnF9Tv/Pf6Y2LFTpOyinF8BTClU5m8jzAsweS0M/K2YfMac+/7I45g5V40/InOZTJE7p3fDt2Bg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(15650500001)(5660300002)(54906003)(110136005)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: USW9rQgAefcG0B1w1Hopr/oRVAgUnBTlLFUZQ0hclWlJ0v9QpesZ+JDsufz2GUcZyz+X5hE2Tm/TR3QuegYs/cF5Hgko1WswoCBeVwUtHz7g9gEx+xC1MVDmCvJ1oBn9RwITH9IA8ZqhQAxErIz6EdgT8YXCUXQM7T7VDciGFwd+TzY407xpydC2bK4V779552ARWd3IbhrZlD34dYAmmTPuKhNva5iRDEh+lV3ZW3eo5DEkeTEftZYpjQbihzD+44/lS//E6ky3Wd0RD59B7ApSqgfAUizmPKSzDXthOs/dYKIHcpA2lAHO/J0kLjUesp9IaREtitCssJdm3k5yX+e3nzJAeqbmhq957mko4h4Hw5Vz+yFd3qKx8tQpYs6c7A9mo4CpsNkPEDS4mwUWtC/DPBLmfUUA8BGgIwY+M5yHYoutL2/TZWc/HD7lySERb/nGUjCxztaqrBVmSM5lvbYhYr6ZJw20HfarY4ikNuAjBJy4O8zgj7rYYaBhr4RC9F0NRCXHeEhHLB4g3/tYZW7cmD1pgMFnmbN1upiShJI5f5svBudD4jJh4QcM+loTKfvofKqBthiepaWDKArX4/KeAUz6DBp5ZbaIaBMJuQ5aEtU/1YGY7RWjHQSxYliKfreF3BaHtHbqfdF/OejRzuj+2jMfnTsNuQpM3asD+a/IqTn8ol6tgBDnIA0qK6e8UbtCb2wWMq7DMS3fsiAr+1ayIiXGBJivI/sN9Pbc12H0A62oToQmrc1j+qAoD68WiKGi5BhRWJ4gSTkDTO9RnxWMhp5FEK0/eHOw5KuwNhDa16/rhOr4+baxS0OaKxF6z5aaAo8+SPBilf8254gqKfEoxqmXF1DWUBzdhcdUCZ1XeUjpAMURFo45+TncSlDLJI4Tw3rxDBXniYiS9qiVNYYrkBpJn7xdCK6AOFfIeyF6BXq6j4TGw8vxFriYGAgRDZ8z4QDQyKaw9WC+sxd4qzj54vlbO5yZ8NS2JFVL7P9GUzdO16JT7usa3zV7DNlqZhTGwjXZijhLjZ91I1YAu3ZCLwna50Qii/wyuEFi9G4kWezMn1qHsESrFeWu93Uy+DrVBBGy/R/u2E9zEKzBIetbtm9Abh9NBnkFRpIELRHba8ja025LMl1d73kjT9xAeCILRu9a4kNDlAEw6mR+xQEmxZwblhRpeJ+EbcbNTK3Tn2hvNcHwvHnNI1IuPkpS/t3ikNQAV7ZBdGRqakZhg8RcyKtbvoB/B3HnSwUUbhrXaYHobR/CYTcEL9HwmI2C5ZxYD3MEhs5koMsMJgU5acusD+HtEQlUaAUmKNgN3aGwaneoMJymMMsdYB8CyJ7i X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6bc29b22-c57a-46ef-b957-08d8d64c7d61 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:38:48.4788 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Cu9uR5X5As4L1rdaegNwX7HH2T9rfRVDMoNpO16CRHh8Zbjt5c+Wl5ATdPPPI7EFPd7cuHJKUEOW2bV642jj5g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The hart registers and CSRs are not preserved in non-retentative suspend state so we provide arch specific helper functions which will save/restore hart context upon entry/exit to non-retentive suspend state. These helper functions can be used by cpuidle drivers for non-retentive suspend entry/exit. Signed-off-by: Anup Patel --- arch/riscv/include/asm/suspend.h | 35 +++++++++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/asm-offsets.c | 3 + arch/riscv/kernel/suspend.c | 86 ++++++++++++++++++++++ arch/riscv/kernel/suspend_entry.S | 116 ++++++++++++++++++++++++++++++ 5 files changed, 242 insertions(+) create mode 100644 arch/riscv/include/asm/suspend.h create mode 100644 arch/riscv/kernel/suspend.c create mode 100644 arch/riscv/kernel/suspend_entry.S diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h new file mode 100644 index 000000000000..63e9f434fb89 --- /dev/null +++ b/arch/riscv/include/asm/suspend.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#ifndef _ASM_RISCV_SUSPEND_H +#define _ASM_RISCV_SUSPEND_H + +#include + +struct suspend_context { + /* Saved and restored by low-level functions */ + struct pt_regs regs; + /* Saved and restored by high-level functions */ + unsigned long scratch; + unsigned long tvec; + unsigned long ie; +#ifdef CONFIG_MMU + unsigned long satp; +#endif +}; + +/* Low-level CPU suspend entry function */ +int __cpu_suspend_enter(struct suspend_context *context); + +/* High-level CPU suspend which will save context and call finish() */ +int cpu_suspend(unsigned long arg, + int (*finish)(unsigned long arg, + unsigned long entry, + unsigned long context)); + +/* Low-level CPU resume entry function */ +int __cpu_resume_enter(unsigned long hartid, unsigned long context); + +#endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f6caf4d9ca15..d83038bf93b2 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -40,6 +40,8 @@ obj-$(CONFIG_SMP) += cpu_ops_spinwait.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o +obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o + obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index b79ffa3561fd..8259f5f16da8 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -10,6 +10,7 @@ #include #include #include +#include void asm_offsets(void); @@ -108,6 +109,8 @@ void asm_offsets(void) OFFSET(PT_BADADDR, pt_regs, badaddr); OFFSET(PT_CAUSE, pt_regs, cause); + OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs); + /* * THREAD_{F,X}* might be larger than a S-type offset can handle, but * these are used in performance-sensitive assembly so we can't resort diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c new file mode 100644 index 000000000000..49dddec30e99 --- /dev/null +++ b/arch/riscv/kernel/suspend.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include +#include +#include + +static void suspend_save_csrs(struct suspend_context *context) +{ + context->scratch = csr_read(CSR_SCRATCH); + context->tvec = csr_read(CSR_TVEC); + context->ie = csr_read(CSR_IE); + + /* + * No need to save/restore IP CSR (i.e. MIP or SIP) because: + * + * 1. For no-MMU (M-mode) kernel, the bits in MIP are set by + * external devices (such as interrupt controller, timer, etc). + * 2. For MMU (S-mode) kernel, the bits in SIP are set by + * M-mode firmware and external devices (such as interrupt + * controller, etc). + */ + +#ifdef CONFIG_MMU + context->satp = csr_read(CSR_SATP); +#endif +} + +static void suspend_restore_csrs(struct suspend_context *context) +{ + csr_write(CSR_SCRATCH, context->scratch); + csr_write(CSR_TVEC, context->tvec); + csr_write(CSR_IE, context->ie); + +#ifdef CONFIG_MMU + csr_write(CSR_SATP, context->satp); +#endif +} + +int cpu_suspend(unsigned long arg, + int (*finish)(unsigned long arg, + unsigned long entry, + unsigned long context)) +{ + int rc = 0; + struct suspend_context context = { 0 }; + + /* Finisher should be non-NULL */ + if (!finish) + return -EINVAL; + + /* Save additional CSRs*/ + suspend_save_csrs(&context); + + /* + * Function graph tracer state gets incosistent when the kernel + * calls functions that never return (aka finishers) hence disable + * graph tracing during their execution. + */ + pause_graph_tracing(); + + /* Save context on stack */ + if (__cpu_suspend_enter(&context)) { + /* Call the finisher */ + rc = finish(arg, __pa_symbol(__cpu_resume_enter), + (ulong)&context); + + /* + * Should never reach here, unless the suspend finisher + * fails. Successful cpu_suspend() should return from + * __cpu_resume_entry() + */ + if (!rc) + rc = -EOPNOTSUPP; + } + + /* Enable function graph tracer */ + unpause_graph_tracing(); + + /* Restore additional CSRs */ + suspend_restore_csrs(&context); + + return rc; +} diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S new file mode 100644 index 000000000000..dee85c86e177 --- /dev/null +++ b/arch/riscv/kernel/suspend_entry.S @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include +#include +#include +#include + + .text + .altmacro + .option norelax + +ENTRY(__cpu_suspend_enter) + /* Save registers (except A0 and T0-T6) */ + REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) + REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) + REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) + REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) + REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) + REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) + REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) + REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) + REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) + REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) + REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) + REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) + REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) + REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) + REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) + REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) + REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) + REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) + REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) + REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) + REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) + REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) + REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) + + /* Save CSRs */ + csrr t0, CSR_EPC + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) + csrr t0, CSR_STATUS + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) + csrr t0, CSR_TVAL + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) + csrr t0, CSR_CAUSE + REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) + + /* Return non-zero value */ + li a0, 1 + + /* Return to C code */ + ret +END(__cpu_suspend_enter) + +ENTRY(__cpu_resume_enter) +#ifdef CONFIG_MMU + /* Save A0 and A1 */ + add t0, a0, zero + add t1, a1, zero + + /* Enable MMU */ + la a0, swapper_pg_dir + call relocate_enable_mmu + + /* Restore A0 and A1 */ + add a0, t0, zero + add a1, t1, zero +#endif + + /* Make A0 point to suspend context */ + add a0, a1, zero + + /* Restore CSRs */ + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) + csrw CSR_EPC, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) + csrw CSR_STATUS, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) + csrw CSR_TVAL, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) + csrw CSR_CAUSE, t0 + + /* Restore registers (except A0 and T0-T6) */ + REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) + REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) + REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) + REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) + REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) + REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) + REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) + REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) + REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) + REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) + REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) + REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) + REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) + REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) + REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) + REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) + REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) + REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) + REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) + REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) + REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) + REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) + REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) + + /* Return zero value */ + add a0, zero, zero + + /* Return to C code */ + ret +END(__cpu_resume_enter) From patchwork Sun Feb 21 09:37:54 2021 Content-Type: text/plain; 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Sun, 21 Feb 2021 09:38:54 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 4/8] RISC-V: Add SBI HSM suspend related defines Date: Sun, 21 Feb 2021 15:07:54 +0530 Message-Id: <20210221093758.210981-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:38:48 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 23bdb66a-6942-4e15-4edb-08d8d64c80fa X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:220; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ya02Q5WWaxKGWHPHYhHgK7uxrvg1veyA83zI63b9WtuU57wgdZjEjX3o781hhYGI4vdFoOpjb7H36FiiXg0vfOnHXTakLlQs0URehbAXx5/PMNSNoFkv9zN1eenKJUQK30kZsT4A+QkDv0Xw4PytiG3pg+6ReUdNRVhVzM6u/bpjKHSYq17wGRhiKu4ShjBhXMEKgque/pNObBbw+IbgtDyGWEq3j4uOof74p+L8NK2PtvKBTIolrCv2gNtir3eudHpsc/Hdw+Y5CCj6oMIxzmz/cF9OtNwxMUVwe61NoEEVQ8pxrZWXcSSLhzA1hIm0d7xj/pNiFRUmmDq39LUYPZF9NTmF+4ZTh37GjluvdTGhJuZ9dCPnhCL0abBfqmlVNj5qrRWEtNJnzDWqy6k9akge0xCUUIkpKdjFjEUD/jWvwnkZuudO+e01bGyO+7oXn39bfNtbtYYXeDTBbpnXG+iPy2c9SjLgb0qKyyuRq+MY4B7PEQ7LWX2riHfeS+hKWAMRQDadyIfg/AZkk5y3BA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(15650500001)(5660300002)(54906003)(110136005)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: aUQKotkDUOfn5CS6abD7IJNmteaKGarrUA+5gJbtOX6fZatp0G3TC/vBP/+6/4zBq3aOI2LqA+c5lHHv95NMUo8Jq8Ni1IhPTqW3Ht1ecxngeUtIZzao6E5c0+C/k4Aae+IaGS4WEAU/g6blP61qpq7EEq1WOnMKdRiSUjmzd37MhG4eBbjYW3zbZsd0l8m64ib9gZgKc+kFEjF84Fq1iWBlBI2in2j3ynCVRrpx5AuJhxopx/s8zB46cE1hI7p302CP1wZk6W4ko/uM0H27ve98xSBBQ5AZKk849Nj9OjjpGKxt0ljcN501pBoJdtRs3Kx+E+lcH5dbu3NAIb0J5gaqtbMWE0RAcnIZBXSKFtYf4+XlX9WXYqV6MwkIMdPEy9tYPeUaUD+PpdBevDfGAwTlL4GG9oQTE45EMX2EAwKkVp7zeK7Mf5IOOkIf829S/znoWvJgKO8TdKmHaSz+93OW0Di/ukAuRj3rIuiBUVOEnKC3NGlQGgR+w6Wv7WgTquIhkBaOeUoCcEDm5oP6nsyOsC6hgczQRdHI1488suK0dNFFCEBkhslCEr4wPOwJ8/g3tiRupwzlL948xax5ntBGzADO+0nOSRGtd2I8OWar45zXHPNh0CJMAKjilRwzh7LUL5Vhx7rGyu8thih3Xo30EJ/pn041fZClAnqexN3cHXq7WzN/n/Y5dqcB+BPJm7t1PaEcIi7d2xmSPGSg8flhq3StZj2ycSFE2sax9pqanQqfB5YydZ5TCYSFAOCt5tJm43wL5JaWDCrcW6BkzRmYrHHhBM2tpv3Pl/wj9kaVxxG8E35qRpj+9QxxdKlY/0rT29CmL3S0WLehqaaQ3Z/GyPxagugKKQQ3v0CoQBHghl+pkW1x3eXTHTC4qEi40Wr57SQ5w9fvAjLC0fzRdN0mEvGtrYQ9Yy1FVupgbmfp0Ml6lkmt9HD4qCj2ikU+++L24423u6O/2bs6HjSY8KKmRSCuzSavpaQBzNni/U4s8Tfl3pJAhfQGEi688pwjteNC4CZ2pYLe9FKNpcCKNR2Yu6np4pJhSY3XyBMcZO3OpX0T7keV0VrjgoeazZbJ38klzRD16eNLh4lP17mGFgBKrA5mebXp5+8zH1+Eccr2OVS5rLinbzykRbaVJmDc45E08WwhOvOuH0PXPpP5rpH3+CDXozDDmzWoUX1l1OjTqhLEfKslObBenR10fwtfXTi5Ci3gcHlg/kROYa/YOmVir66TIYCjCz+5A7oXXNNrvVQR8wr9QWyuU6RPKBVTmmFXHCHBMnPV/uOt4x9APVqTx6Y7ii9fMonkp9IqQp7mVUa8iskBXMoNF0sCQYRm X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 23bdb66a-6942-4e15-4edb-08d8d64c80fa X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:38:54.4200 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DuSowIbT1fZzc97VT1oi89g0QEMLDqvhc0nTxxzZV7uM1CYU+SjvXkhXoBLVjKiymE6rjYO7qiqbVtlN9DB2qA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We add defines related to SBI HSM suspend call and also update HSM states naming as-per latest SBI specification. Signed-off-by: Anup Patel --- arch/riscv/include/asm/sbi.h | 27 ++++++++++++++++++++++----- arch/riscv/kernel/cpu_ops_sbi.c | 2 +- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b2d6d614c20..4f101f1aa4ea 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -62,15 +62,32 @@ enum sbi_ext_hsm_fid { SBI_EXT_HSM_HART_START = 0, SBI_EXT_HSM_HART_STOP, SBI_EXT_HSM_HART_STATUS, + SBI_EXT_HSM_HART_SUSPEND, }; -enum sbi_hsm_hart_status { - SBI_HSM_HART_STATUS_STARTED = 0, - SBI_HSM_HART_STATUS_STOPPED, - SBI_HSM_HART_STATUS_START_PENDING, - SBI_HSM_HART_STATUS_STOP_PENDING, +enum sbi_hsm_hart_state { + SBI_HSM_STATE_STARTED = 0, + SBI_HSM_STATE_STOPPED, + SBI_HSM_STATE_START_PENDING, + SBI_HSM_STATE_STOP_PENDING, + SBI_HSM_STATE_SUSPENDED, + SBI_HSM_STATE_SUSPEND_PENDING, + SBI_HSM_STATE_RESUME_PENDING, }; +#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff +#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 +#define SBI_HSM_SUSP_PLAT_BASE 0x10000000 + +#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 +#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE +#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK +#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT +#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ + SBI_HSM_SUSP_PLAT_BASE) +#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ + SBI_HSM_SUSP_BASE_MASK) + enum sbi_ext_srst_fid { SBI_EXT_SRST_RESET = 0, }; diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c index 685fae72b7f5..5fd90f03a3e9 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -97,7 +97,7 @@ static int sbi_cpu_is_stopped(unsigned int cpuid) rc = sbi_hsm_hart_get_status(hartid); - if (rc == SBI_HSM_HART_STATUS_STOPPED) + if (rc == SBI_HSM_STATE_STOPPED) return 0; return rc; } From patchwork Sun Feb 21 09:37:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 386006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2F68C433E6 for ; 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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM5PR04MB0459.namprd04.prod.outlook.com (2603:10b6:3:9d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.25; Sun, 21 Feb 2021 09:39:00 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868%7]) with mapi id 15.20.3868.029; Sun, 21 Feb 2021 09:39:00 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 5/8] cpuidle: Factor-out power domain related code from PSCI domain driver Date: Sun, 21 Feb 2021 15:07:55 +0530 Message-Id: <20210221093758.210981-6-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:38:54 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7b70b017-7975-435f-bee3-08d8d64c8480 X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:359; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: p09NH6YfRVakBm0j43j5BZJqoTjUSjXac4Mn9SV8Ky2Sb3R+MvxBwTJV3HGc+TQjNwpdYAo2DrLWBhp4g14MuhiMqYqew1P1jjKRS7J/kb93miN1pcKxJpxLlquOeHP1R2JhfRM/KGfg6qqVZDfC/s5X2pGcgqocypDVf24GLxLkDAIxlpyqojaZEB4g51CZ7jj5kry3IV7lvwsXfIyBhIw4BW9ygyf1w/fH/gsbsznKWghEKsaWCCMXDyv7Wyl4t34SNL+Ie31M+XyTHDK2NQjx6fD3DOyda8MQrQIoPbMh62A560GyncJdLZfCPSIkqHjnDyvyEmc+Dgs+tuwWFAWjqB0UjyHwuE4zdMyjLQSykWda+xhUTyC6J0VZeZ/eYgO1wMeXAi6p7vOGWcaYi/2R7ZrcibwkOfIE8TqqxQzxCjqmLfDpr5JOei/6f0El8eAPuf/mfbkUpajs+K9IQ/PG+MrQm3d3p4zSXEtB3yfWPPjcPIcDB8aHlYlCDYWeVnnHsV53U+X5uzOGI+Lfdw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(16526019)(7696005)(5660300002)(54906003)(110136005)(30864003)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: cT4hFEq84RXb+PGpPlqlGVmS9rSvkTDC7utJ9SySsH4FUu96ct6jg3Z5aHF3KZmkMGriFELqREQdp2wEmUTx6Qw1ip2SP0EUbWFr++Dr+jAkh8mWmVxNYodGoDf4ETtWN694J+C1Rt19fSNawLbCRKCgamYARWjxBElLgc/bAD63VqilUp+qrqK6lh5neLzeqh9Rlv4cOu7m4WR5JH9krKtfW7z5aJz1OIUCOWh1BL9LhQDhAzCISSva89QbOrveSBpCLXLcNyUe0OaWbpiHNjs0JWBbespcPEKdU2xf4ZH5oM/fcHo07xcH7xumNGGpGKqgjwjdrCAcexho28OVnRNTPtZbmu6KnaUs9p6BcwjnokHTsjXrIe1mSu5PEg39LlICr38C13CdCBXFFCdE0Fz7eCyM7C/HUDGuxjXI5zcLBPr8ZFFou2NWVaV6kqfsHlJ8+skMwCL2Kb6KcOXZWV2YiGnqtDTDMd6tgTEh6ZXXPqKsSUBnidsikCr3Kw6qwCu46a54n6l0atDmKVRjGzB2cQCx2uX+/DTAUJvmhdjHso8RZHfXeTb7gq95oSx+wFGhmvTsjn49HjhiIoSI+3AkrPfbgsjw0P0BwYVNvSxhLV1UJo3FiZ6q46d7mWT4UxTL4X/XNN/wFIo+KARajrnbD8L7DKRXoGWU2Rx01yAk1c5lMib1n9oL80BI0vZJw5y7ybMZUtE0URLNNrdrpodRawpdcMqBFnyWVao/V2ivRiM76lw0ey8CynuOfape4hJd0WG4dE32YZc2uJARoG5PDi/UB6kbrqC9Twrn1GnvFkV7BwQUFikZ1pre/hQQRxsCZ3c79ClhCyfc6aw3RA9luAwuzRBtf+TetzJjMTWYmbRJyX4aLdJR1dUFEfow5WPXEDm8YfJ92zB7Pr9kQnalxclwA7f24XMu0Up50TP6NSKI0KAB+mVlYFkEiTIa8q0WDBrPfVflf3Ds5xAdJWEvkEHkweIqEF+9MhrxIWp9mz4dwVu+/9EjQuOyPjw6JAnOVatiiE/fdvgZEFt8cSA2Xf0YPdFwTdHQ60LB98jQ9XdjINoPCtQxkOIk8Vq83sZFSqAMQRoeXXC2T93wDh9qZS0rWAmCxFIkaFKMCx0bBgvkzuKsup4/sA6lIblHn9eSzWPjeYALQItnjaf5r8T7Yam3pJoC9BIXliOB3TAn1vvvWzQfWJt8bJcYyVjCfILzqWH6oauAV2d/psVByY9PzB7/J3WhD6DP3zBf9VLExoD/LUzoqPqhnAQftLPFt/GafjW3D0FFDh1JIqa6X0SGlt2CR9sdnmadfP/BC8EiNUWTnImLwYtt5j9XoClq X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7b70b017-7975-435f-bee3-08d8d64c8480 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:39:00.5631 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fEmRdpbWz6R8FPizOy9XIdQMaUU/3uq7rJBCvKr6Ynm5GqyPUf+lrfwgPBbJfhvxDL/B7jlWccFEcRxf9bEY4A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The generic power domain related code in PSCI domain driver is largely independent of PSCI and can be shared with RISC-V SBI domain driver hence we factor-out this code into dt_idle_genpd.c and dt_idle_genpd.h. Signed-off-by: Anup Patel --- drivers/cpuidle/Kconfig | 4 + drivers/cpuidle/Kconfig.arm | 1 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-psci-domain.c | 244 +----------------- drivers/cpuidle/cpuidle-psci.h | 15 +- ...{cpuidle-psci-domain.c => dt_idle_genpd.c} | 165 ++++-------- drivers/cpuidle/dt_idle_genpd.h | 42 +++ 7 files changed, 121 insertions(+), 351 deletions(-) copy drivers/cpuidle/{cpuidle-psci-domain.c => dt_idle_genpd.c} (52%) create mode 100644 drivers/cpuidle/dt_idle_genpd.h diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig index c0aeedd66f02..f1afe7ab6b54 100644 --- a/drivers/cpuidle/Kconfig +++ b/drivers/cpuidle/Kconfig @@ -47,6 +47,10 @@ config CPU_IDLE_GOV_HALTPOLL config DT_IDLE_STATES bool +config DT_IDLE_GENPD + depends on PM_GENERIC_DOMAINS_OF + bool + menu "ARM CPU Idle Drivers" depends on ARM || ARM64 source "drivers/cpuidle/Kconfig.arm" diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 0844fadc4be8..1007435ae298 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -27,6 +27,7 @@ config ARM_PSCI_CPUIDLE_DOMAIN bool "PSCI CPU idle Domain" depends on ARM_PSCI_CPUIDLE depends on PM_GENERIC_DOMAINS_OF + select DT_IDLE_GENPD default y help Select this to enable the PSCI based CPUidle driver to use PM domains, diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 26bbc5e74123..11a26cef279f 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -6,6 +6,7 @@ obj-y += cpuidle.o driver.o governor.o sysfs.o governors/ obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o +obj-$(CONFIG_DT_IDLE_GENPD) += dt_idle_genpd.o obj-$(CONFIG_ARCH_HAS_CPU_RELAX) += poll_state.o obj-$(CONFIG_HALTPOLL_CPUIDLE) += cpuidle-haltpoll.o diff --git a/drivers/cpuidle/cpuidle-psci-domain.c b/drivers/cpuidle/cpuidle-psci-domain.c index ff2c3f8e4668..b0621d890ab7 100644 --- a/drivers/cpuidle/cpuidle-psci-domain.c +++ b/drivers/cpuidle/cpuidle-psci-domain.c @@ -16,17 +16,9 @@ #include #include #include -#include -#include #include "cpuidle-psci.h" -struct psci_pd_provider { - struct list_head link; - struct device_node *node; -}; - -static LIST_HEAD(psci_pd_providers); static bool psci_pd_allow_domain_state; static int psci_pd_power_off(struct generic_pm_domain *pd) @@ -47,178 +39,6 @@ static int psci_pd_power_off(struct generic_pm_domain *pd) return 0; } -static int psci_pd_parse_state_nodes(struct genpd_power_state *states, - int state_count) -{ - int i, ret; - u32 psci_state, *psci_state_buf; - - for (i = 0; i < state_count; i++) { - ret = psci_dt_parse_state_node(to_of_node(states[i].fwnode), - &psci_state); - if (ret) - goto free_state; - - psci_state_buf = kmalloc(sizeof(u32), GFP_KERNEL); - if (!psci_state_buf) { - ret = -ENOMEM; - goto free_state; - } - *psci_state_buf = psci_state; - states[i].data = psci_state_buf; - } - - return 0; - -free_state: - i--; - for (; i >= 0; i--) - kfree(states[i].data); - return ret; -} - -static int psci_pd_parse_states(struct device_node *np, - struct genpd_power_state **states, int *state_count) -{ - int ret; - - /* Parse the domain idle states. */ - ret = of_genpd_parse_idle_states(np, states, state_count); - if (ret) - return ret; - - /* Fill out the PSCI specifics for each found state. */ - ret = psci_pd_parse_state_nodes(*states, *state_count); - if (ret) - kfree(*states); - - return ret; -} - -static void psci_pd_free_states(struct genpd_power_state *states, - unsigned int state_count) -{ - int i; - - for (i = 0; i < state_count; i++) - kfree(states[i].data); - kfree(states); -} - -static int psci_pd_init(struct device_node *np, bool use_osi) -{ - struct generic_pm_domain *pd; - struct psci_pd_provider *pd_provider; - struct dev_power_governor *pd_gov; - struct genpd_power_state *states = NULL; - int ret = -ENOMEM, state_count = 0; - - pd = kzalloc(sizeof(*pd), GFP_KERNEL); - if (!pd) - goto out; - - pd_provider = kzalloc(sizeof(*pd_provider), GFP_KERNEL); - if (!pd_provider) - goto free_pd; - - pd->name = kasprintf(GFP_KERNEL, "%pOF", np); - if (!pd->name) - goto free_pd_prov; - - /* - * Parse the domain idle states and let genpd manage the state selection - * for those being compatible with "domain-idle-state". - */ - ret = psci_pd_parse_states(np, &states, &state_count); - if (ret) - goto free_name; - - pd->free_states = psci_pd_free_states; - pd->name = kbasename(pd->name); - pd->states = states; - pd->state_count = state_count; - pd->flags |= GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; - - /* Allow power off when OSI has been successfully enabled. */ - if (use_osi) - pd->power_off = psci_pd_power_off; - else - pd->flags |= GENPD_FLAG_ALWAYS_ON; - - /* Use governor for CPU PM domains if it has some states to manage. */ - pd_gov = state_count > 0 ? &pm_domain_cpu_gov : NULL; - - ret = pm_genpd_init(pd, pd_gov, false); - if (ret) { - psci_pd_free_states(states, state_count); - goto free_name; - } - - ret = of_genpd_add_provider_simple(np, pd); - if (ret) - goto remove_pd; - - pd_provider->node = of_node_get(np); - list_add(&pd_provider->link, &psci_pd_providers); - - pr_debug("init PM domain %s\n", pd->name); - return 0; - -remove_pd: - pm_genpd_remove(pd); -free_name: - kfree(pd->name); -free_pd_prov: - kfree(pd_provider); -free_pd: - kfree(pd); -out: - pr_err("failed to init PM domain ret=%d %pOF\n", ret, np); - return ret; -} - -static void psci_pd_remove(void) -{ - struct psci_pd_provider *pd_provider, *it; - struct generic_pm_domain *genpd; - - list_for_each_entry_safe(pd_provider, it, &psci_pd_providers, link) { - of_genpd_del_provider(pd_provider->node); - - genpd = of_genpd_remove_last(pd_provider->node); - if (!IS_ERR(genpd)) - kfree(genpd); - - of_node_put(pd_provider->node); - list_del(&pd_provider->link); - kfree(pd_provider); - } -} - -static int psci_pd_init_topology(struct device_node *np) -{ - struct device_node *node; - struct of_phandle_args child, parent; - int ret; - - for_each_child_of_node(np, node) { - if (of_parse_phandle_with_args(node, "power-domains", - "#power-domain-cells", 0, &parent)) - continue; - - child.np = node; - child.args_count = 0; - ret = of_genpd_add_subdomain(&parent, &child); - of_node_put(parent.np); - if (ret) { - of_node_put(node); - return ret; - } - } - - return 0; -} - static bool psci_pd_try_set_osi_mode(void) { int ret; @@ -244,6 +64,10 @@ static void psci_cpuidle_domain_sync_state(struct device *dev) psci_pd_allow_domain_state = true; } +static struct dt_idle_genpd_ops psci_genpd_ops = { + .parse_state_node = psci_dt_parse_state_node, +}; + static const struct of_device_id psci_of_match[] = { { .compatible = "arm,psci-1.0" }, {} @@ -252,48 +76,25 @@ static const struct of_device_id psci_of_match[] = { static int psci_cpuidle_domain_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - struct device_node *node; bool use_osi; - int ret = 0, pd_count = 0; + int ret = 0; if (!np) return -ENODEV; /* If OSI mode is supported, let's try to enable it. */ use_osi = psci_pd_try_set_osi_mode(); + if (use_osi) + psci_genpd_ops.power_off = psci_pd_power_off; - /* - * Parse child nodes for the "#power-domain-cells" property and - * initialize a genpd/genpd-of-provider pair when it's found. - */ - for_each_child_of_node(np, node) { - if (!of_find_property(node, "#power-domain-cells", NULL)) - continue; - - ret = psci_pd_init(node, use_osi); - if (ret) - goto put_node; - - pd_count++; - } - - /* Bail out if not using the hierarchical CPU topology. */ - if (!pd_count) - goto no_pd; - - /* Link genpd masters/subdomains to model the CPU topology. */ - ret = psci_pd_init_topology(np); + /* Generic power domain probing based on DT node. */ + ret = dt_idle_genpd_probe(&psci_genpd_ops, np); if (ret) - goto remove_pd; + goto no_pd; pr_info("Initialized CPU PM domain topology\n"); return 0; -put_node: - of_node_put(node); -remove_pd: - psci_pd_remove(); - pr_err("failed to create CPU PM domains ret=%d\n", ret); no_pd: if (use_osi) psci_set_osi_mode(false); @@ -314,28 +115,3 @@ static int __init psci_idle_init_domains(void) return platform_driver_register(&psci_cpuidle_domain_driver); } subsys_initcall(psci_idle_init_domains); - -struct device *psci_dt_attach_cpu(int cpu) -{ - struct device *dev; - - dev = dev_pm_domain_attach_by_name(get_cpu_device(cpu), "psci"); - if (IS_ERR_OR_NULL(dev)) - return dev; - - pm_runtime_irq_safe(dev); - if (cpu_online(cpu)) - pm_runtime_get_sync(dev); - - dev_pm_syscore_device(dev, true); - - return dev; -} - -void psci_dt_detach_cpu(struct device *dev) -{ - if (IS_ERR_OR_NULL(dev)) - return; - - dev_pm_domain_detach(dev, false); -} diff --git a/drivers/cpuidle/cpuidle-psci.h b/drivers/cpuidle/cpuidle-psci.h index d8e925e84c27..70de1e3c00af 100644 --- a/drivers/cpuidle/cpuidle-psci.h +++ b/drivers/cpuidle/cpuidle-psci.h @@ -10,8 +10,19 @@ void psci_set_domain_state(u32 state); int psci_dt_parse_state_node(struct device_node *np, u32 *state); #ifdef CONFIG_ARM_PSCI_CPUIDLE_DOMAIN -struct device *psci_dt_attach_cpu(int cpu); -void psci_dt_detach_cpu(struct device *dev); + +#include "dt_idle_genpd.h" + +static inline struct device *psci_dt_attach_cpu(int cpu) +{ + return dt_idle_genpd_attach_cpu(cpu, "psci"); +} + +static inline void psci_dt_detach_cpu(struct device *dev) +{ + dt_idle_genpd_detach_cpu(dev); +} + #else static inline struct device *psci_dt_attach_cpu(int cpu) { return NULL; } static inline void psci_dt_detach_cpu(struct device *dev) { } diff --git a/drivers/cpuidle/cpuidle-psci-domain.c b/drivers/cpuidle/dt_idle_genpd.c similarity index 52% copy from drivers/cpuidle/cpuidle-psci-domain.c copy to drivers/cpuidle/dt_idle_genpd.c index ff2c3f8e4668..805c4c81d60f 100644 --- a/drivers/cpuidle/cpuidle-psci-domain.c +++ b/drivers/cpuidle/dt_idle_genpd.c @@ -1,71 +1,52 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * PM domains for CPUs via genpd - managed by cpuidle-psci. + * PM domains for CPUs via genpd. * * Copyright (C) 2019 Linaro Ltd. * Author: Ulf Hansson * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. */ -#define pr_fmt(fmt) "CPUidle PSCI: " fmt +#define pr_fmt(fmt) "dt-idle-genpd: " fmt #include #include #include -#include #include #include -#include #include #include -#include "cpuidle-psci.h" +#include "dt_idle_genpd.h" -struct psci_pd_provider { +struct dt_pd_provider { struct list_head link; struct device_node *node; }; -static LIST_HEAD(psci_pd_providers); -static bool psci_pd_allow_domain_state; +static LIST_HEAD(dt_pd_providers); -static int psci_pd_power_off(struct generic_pm_domain *pd) -{ - struct genpd_power_state *state = &pd->states[pd->state_idx]; - u32 *pd_state; - - if (!state->data) - return 0; - - if (!psci_pd_allow_domain_state) - return -EBUSY; - - /* OSI mode is enabled, set the corresponding domain state. */ - pd_state = state->data; - psci_set_domain_state(*pd_state); - - return 0; -} - -static int psci_pd_parse_state_nodes(struct genpd_power_state *states, - int state_count) +static int dt_pd_parse_state_nodes(const struct dt_idle_genpd_ops *ops, + struct genpd_power_state *states, + int state_count) { int i, ret; - u32 psci_state, *psci_state_buf; + u32 state, *state_buf; for (i = 0; i < state_count; i++) { - ret = psci_dt_parse_state_node(to_of_node(states[i].fwnode), - &psci_state); + ret = ops->parse_state_node(to_of_node(states[i].fwnode), + &state); if (ret) goto free_state; - psci_state_buf = kmalloc(sizeof(u32), GFP_KERNEL); - if (!psci_state_buf) { + state_buf = kmalloc(sizeof(u32), GFP_KERNEL); + if (!state_buf) { ret = -ENOMEM; goto free_state; } - *psci_state_buf = psci_state; - states[i].data = psci_state_buf; + *state_buf = state; + states[i].data = state_buf; } return 0; @@ -77,8 +58,10 @@ static int psci_pd_parse_state_nodes(struct genpd_power_state *states, return ret; } -static int psci_pd_parse_states(struct device_node *np, - struct genpd_power_state **states, int *state_count) +static int dt_pd_parse_states(const struct dt_idle_genpd_ops *ops, + struct device_node *np, + struct genpd_power_state **states, + int *state_count) { int ret; @@ -87,15 +70,15 @@ static int psci_pd_parse_states(struct device_node *np, if (ret) return ret; - /* Fill out the PSCI specifics for each found state. */ - ret = psci_pd_parse_state_nodes(*states, *state_count); + /* Fill out the dt specifics for each found state. */ + ret = dt_pd_parse_state_nodes(ops, *states, *state_count); if (ret) kfree(*states); return ret; } -static void psci_pd_free_states(struct genpd_power_state *states, +static void dt_pd_free_states(struct genpd_power_state *states, unsigned int state_count) { int i; @@ -105,10 +88,11 @@ static void psci_pd_free_states(struct genpd_power_state *states, kfree(states); } -static int psci_pd_init(struct device_node *np, bool use_osi) +static int dt_pd_init(const struct dt_idle_genpd_ops *ops, + struct device_node *np) { struct generic_pm_domain *pd; - struct psci_pd_provider *pd_provider; + struct dt_pd_provider *pd_provider; struct dev_power_governor *pd_gov; struct genpd_power_state *states = NULL; int ret = -ENOMEM, state_count = 0; @@ -129,19 +113,19 @@ static int psci_pd_init(struct device_node *np, bool use_osi) * Parse the domain idle states and let genpd manage the state selection * for those being compatible with "domain-idle-state". */ - ret = psci_pd_parse_states(np, &states, &state_count); + ret = dt_pd_parse_states(ops, np, &states, &state_count); if (ret) goto free_name; - pd->free_states = psci_pd_free_states; + pd->free_states = dt_pd_free_states; pd->name = kbasename(pd->name); pd->states = states; pd->state_count = state_count; pd->flags |= GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; - /* Allow power off when OSI has been successfully enabled. */ - if (use_osi) - pd->power_off = psci_pd_power_off; + /* Allow power off when available. */ + if (ops->power_off) + pd->power_off = ops->power_off; else pd->flags |= GENPD_FLAG_ALWAYS_ON; @@ -150,7 +134,7 @@ static int psci_pd_init(struct device_node *np, bool use_osi) ret = pm_genpd_init(pd, pd_gov, false); if (ret) { - psci_pd_free_states(states, state_count); + dt_pd_free_states(states, state_count); goto free_name; } @@ -159,7 +143,7 @@ static int psci_pd_init(struct device_node *np, bool use_osi) goto remove_pd; pd_provider->node = of_node_get(np); - list_add(&pd_provider->link, &psci_pd_providers); + list_add(&pd_provider->link, &dt_pd_providers); pr_debug("init PM domain %s\n", pd->name); return 0; @@ -177,12 +161,12 @@ static int psci_pd_init(struct device_node *np, bool use_osi) return ret; } -static void psci_pd_remove(void) +static void dt_pd_remove(void) { - struct psci_pd_provider *pd_provider, *it; + struct dt_pd_provider *pd_provider, *it; struct generic_pm_domain *genpd; - list_for_each_entry_safe(pd_provider, it, &psci_pd_providers, link) { + list_for_each_entry_safe(pd_provider, it, &dt_pd_providers, link) { of_genpd_del_provider(pd_provider->node); genpd = of_genpd_remove_last(pd_provider->node); @@ -195,7 +179,7 @@ static void psci_pd_remove(void) } } -static int psci_pd_init_topology(struct device_node *np) +static int dt_pd_init_topology(struct device_node *np) { struct device_node *node; struct of_phandle_args child, parent; @@ -219,49 +203,15 @@ static int psci_pd_init_topology(struct device_node *np) return 0; } -static bool psci_pd_try_set_osi_mode(void) -{ - int ret; - - if (!psci_has_osi_support()) - return false; - - ret = psci_set_osi_mode(true); - if (ret) { - pr_warn("failed to enable OSI mode: %d\n", ret); - return false; - } - - return true; -} - -static void psci_cpuidle_domain_sync_state(struct device *dev) +int dt_idle_genpd_probe(const struct dt_idle_genpd_ops *ops, + struct device_node *np) { - /* - * All devices have now been attached/probed to the PM domain topology, - * hence it's fine to allow domain states to be picked. - */ - psci_pd_allow_domain_state = true; -} - -static const struct of_device_id psci_of_match[] = { - { .compatible = "arm,psci-1.0" }, - {} -}; - -static int psci_cpuidle_domain_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; struct device_node *node; - bool use_osi; int ret = 0, pd_count = 0; - if (!np) + if (!np || !ops || !ops->parse_state_node) return -ENODEV; - /* If OSI mode is supported, let's try to enable it. */ - use_osi = psci_pd_try_set_osi_mode(); - /* * Parse child nodes for the "#power-domain-cells" property and * initialize a genpd/genpd-of-provider pair when it's found. @@ -270,7 +220,7 @@ static int psci_cpuidle_domain_probe(struct platform_device *pdev) if (!of_find_property(node, "#power-domain-cells", NULL)) continue; - ret = psci_pd_init(node, use_osi); + ret = dt_pd_init(ops, node); if (ret) goto put_node; @@ -282,44 +232,27 @@ static int psci_cpuidle_domain_probe(struct platform_device *pdev) goto no_pd; /* Link genpd masters/subdomains to model the CPU topology. */ - ret = psci_pd_init_topology(np); + ret = dt_pd_init_topology(np); if (ret) goto remove_pd; - pr_info("Initialized CPU PM domain topology\n"); return 0; put_node: of_node_put(node); remove_pd: - psci_pd_remove(); + dt_pd_remove(); pr_err("failed to create CPU PM domains ret=%d\n", ret); no_pd: - if (use_osi) - psci_set_osi_mode(false); return ret; } +EXPORT_SYMBOL_GPL(dt_idle_genpd_probe); -static struct platform_driver psci_cpuidle_domain_driver = { - .probe = psci_cpuidle_domain_probe, - .driver = { - .name = "psci-cpuidle-domain", - .of_match_table = psci_of_match, - .sync_state = psci_cpuidle_domain_sync_state, - }, -}; - -static int __init psci_idle_init_domains(void) -{ - return platform_driver_register(&psci_cpuidle_domain_driver); -} -subsys_initcall(psci_idle_init_domains); - -struct device *psci_dt_attach_cpu(int cpu) +struct device *dt_idle_genpd_attach_cpu(int cpu, const char *name) { struct device *dev; - dev = dev_pm_domain_attach_by_name(get_cpu_device(cpu), "psci"); + dev = dev_pm_domain_attach_by_name(get_cpu_device(cpu), name); if (IS_ERR_OR_NULL(dev)) return dev; @@ -331,11 +264,13 @@ struct device *psci_dt_attach_cpu(int cpu) return dev; } +EXPORT_SYMBOL_GPL(dt_idle_genpd_attach_cpu); -void psci_dt_detach_cpu(struct device *dev) +void dt_idle_genpd_detach_cpu(struct device *dev) { if (IS_ERR_OR_NULL(dev)) return; dev_pm_domain_detach(dev, false); } +EXPORT_SYMBOL_GPL(dt_idle_genpd_detach_cpu); diff --git a/drivers/cpuidle/dt_idle_genpd.h b/drivers/cpuidle/dt_idle_genpd.h new file mode 100644 index 000000000000..a3d3d2e85871 --- /dev/null +++ b/drivers/cpuidle/dt_idle_genpd.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_IDLE_GENPD +#define __DT_IDLE_GENPD + +struct device_node; +struct generic_pm_domain; + +struct dt_idle_genpd_ops { + int (*parse_state_node)(struct device_node *np, u32 *state); + int (*power_off)(struct generic_pm_domain *pd); +}; + +#ifdef CONFIG_DT_IDLE_GENPD + +int dt_idle_genpd_probe(const struct dt_idle_genpd_ops *ops, + struct device_node *np); + +struct device *dt_idle_genpd_attach_cpu(int cpu, const char *name); + +void dt_idle_genpd_detach_cpu(struct device *dev); + +#else + +int dt_idle_genpd_probe(const struct dt_idle_genpd_ops *ops, + struct device_node *np) +{ + return 0; +} + +static inline struct device *dt_idle_genpd_attach_cpu(int cpu, + const char *name) +{ + return NULL; +} + +static inline void dt_idle_genpd_detach_cpu(struct device *dev) +{ +} + +#endif + +#endif From patchwork Sun Feb 21 09:37:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 385654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1371EC433E0 for ; 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dkim=none (message not signed) header.d=none; dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM5PR04MB0459.namprd04.prod.outlook.com (2603:10b6:3:9d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.25; Sun, 21 Feb 2021 09:39:06 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::38c0:cc46:192b:1868%7]) with mapi id 15.20.3868.029; Sun, 21 Feb 2021 09:39:06 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 6/8] cpuidle: Add RISC-V SBI CPU idle driver Date: Sun, 21 Feb 2021 15:07:56 +0530 Message-Id: <20210221093758.210981-7-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:39:01 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7429e729-5265-4a59-8faa-08d8d64c882a X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eP/j7LxITp7NbTAJWu6ov4diiio+2Tr8eA7A2RtRS4yXXygyPlis73k5eWrcZbKp1hfZmvTBT4oPzfAdgZDby+UrAtZMio6KuZZWuYLdXLTHxN8ofpKqrkyimE9PELY08MSVSXILsy/1qLF/fz3gBpgjmieawgqwdtv5LEYbv0MvyYUwPzGkCHmfnl/ocynl/MscAx2sAlC2K0Kc83HwFwJqqKf8blhfe5moysT1SNAaWu+GvrC1FqJ1jOroWziiYXosMpjVbd5CMxjOO5CUkUZOMjv9QVmbsUWvJ3ckXjKy+pkMbbU/K9LO67ZLx4+gP8hGbrM6xbJPuITW1+gyn2W5TghCUx43vAH+dh5SY5iTG95B+hJAN0510LcEify8u0mxVRrooq92RbvrrS+ZRj3wks+rfrpyCxKpJj6XIVLCqbve3DKbSvzOJ5dbm/KJ1S3JT16eNgdLDj0KOhrUO6hInCb4WYGbQQjqcg56qvglCS+ye/Kg8YYDpKhkFb9ZgF1mBMIvx2LTig1/qVVYkw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(5660300002)(54906003)(110136005)(30864003)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: uPhTB86Yn7qmVIfui/vc6QzGnb4fBB7CEkSiVHcLNnE3XsLrnOVaSkXr8+A5O9WTCjL3HoM7WD2/IC6N1AOzgUZOl7UEID0MvpR2x5YMzvSHJvYoQBZt7tNmR1v8p4S/U/TejVJuDNfgSWgamQs8G5tBROO1zAuSh38E7JH3cFEhHcyMnHPlYPugsojoPBfY1zP8wIrKWfR0yzy4hT1pyPBtFveIERk3EpIi9/L08etLO/6zr9K0zcBHW+g5dzG/VPo+GCjaXDZxm0wFBIxLcVwXMVNaCPRhm3MpwCeeFbW6XqDLoJ9Gtejjx7PJm2M/ZAxQpTSWIqzjO9RoMC0QGTCGrrnHinV1Ggd6L/b5+iJXq1KZQRfgXx34cDl373oEvSJny2Q6jab+3/j56Xb4ihtBZMwPCkHTlzOWYcCjDEC4937XW+Z9/9FQcV6PAb4vLOd17/cXp0bS4+mrVFpjYaKvhdMh0EuTEjnLdO4rqUtVcewU4nHdwb4j66FIuJUyQBcVbZsPnq6iY3I6OhxevfuoB/qgWMM6XcjtibnHKTkK/kMOQpwa4s8XGqqFvTv/WhYiszk8KmREhOW3BIJHDPKLWEZg2AYdLJ5NxsLvvGftGQ1VSJ9KoufAzivORGw9N6V9IUAf1yEMI2OcrSaOBGITfZqylA9npvCy1K4Lr5HfXUI4lppgwqgj0myGHGJrY0TLilADmGBpgYrUb2tjqQ8j3ukPm5272qtA4aJJ+LoRdcLFgcYfUDPf5fyPMQqBQZr92BmNId3hMOmRO3URbQ5nMdlgWOGuwtRvYXtpA/g89hgZtvFlxATWFx4LqNh3OMKQo6CNV0j3E/f2PoMxytoNaUHNh2FDBgQhS30FNOzLEdJQcKggDfM4lbPsrUaXCHPmj24CavBVlBG4Bu5BvNwoKggVXH8cnPlfpqYdryfU8HBCHa9kjasX6y19i0nqAkXwn+Iaqrmes6DmX+xUOHaH5on1NvJMpAKEtQaNFBHOVh5tcjhSFJ4ysnbrQhAJCgYn+p5bseeMCy8V5p4VZMKO066Wkz424qh55fdukAy1D8eo6anmbQgL7JgypQNMoEhyg/JRF2318MWA0ugQD8xaPmj1TaEXcPcW5yrP0BnYuoOy4cNu/EpWr+a0lUrCgreVZUn+L4+GUxTGWizEmaa5BhxBd0oOHgaJdpy2wbnyJAdP2An0HE8RLpKmiErmCqdOvER7Dj3ff+PuVl5fVf2ue0kt15liSOkP+1MJCyq2scEIyeaXViZIP3G3nMtN6R9ekhNoOK8GK7Qcxixu4GdnxYbUlri9qQsi9yIfJCFwZirWW2dFfngj+xayTD1S X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7429e729-5265-4a59-8faa-08d8d64c882a X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:39:06.5023 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GrNXpTVwHFBCLuYA4oqHzXzLp2J9DEAQXzVj3TX41RW2Wcu4hyzBx9FlVOml23fljY5LscInzLTtS8H5Jg1QlA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The RISC-V SBI HSM extension provides HSM suspend call which can be used by Linux RISC-V to enter platform specific low-power state. This patch adds a CPU idle driver based on RISC-V SBI calls which will populate idle states from device tree and use SBI calls to entry these idle states. Signed-off-by: Anup Patel --- MAINTAINERS | 8 + drivers/cpuidle/Kconfig | 5 + drivers/cpuidle/Kconfig.riscv | 15 + drivers/cpuidle/Makefile | 4 + drivers/cpuidle/cpuidle-sbi.c | 503 ++++++++++++++++++++++++++++++++++ 5 files changed, 535 insertions(+) create mode 100644 drivers/cpuidle/Kconfig.riscv create mode 100644 drivers/cpuidle/cpuidle-sbi.c diff --git a/MAINTAINERS b/MAINTAINERS index 667d03852191..eeeab188a8ac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4641,6 +4641,14 @@ S: Supported F: drivers/cpuidle/cpuidle-psci.h F: drivers/cpuidle/cpuidle-psci-domain.c +CPUIDLE DRIVER - RISC-V SBI +M: Anup Patel +R: Sandeep Tripathy +L: linux-pm@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/cpuidle/cpuidle-sbi.c + CRAMFS FILESYSTEM M: Nicolas Pitre S: Maintained diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig index f1afe7ab6b54..ff71dd662880 100644 --- a/drivers/cpuidle/Kconfig +++ b/drivers/cpuidle/Kconfig @@ -66,6 +66,11 @@ depends on PPC source "drivers/cpuidle/Kconfig.powerpc" endmenu +menu "RISC-V CPU Idle Drivers" +depends on RISCV +source "drivers/cpuidle/Kconfig.riscv" +endmenu + config HALTPOLL_CPUIDLE tristate "Halt poll cpuidle driver" depends on X86 && KVM_GUEST diff --git a/drivers/cpuidle/Kconfig.riscv b/drivers/cpuidle/Kconfig.riscv new file mode 100644 index 000000000000..78518c26af74 --- /dev/null +++ b/drivers/cpuidle/Kconfig.riscv @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RISC-V CPU Idle drivers +# + +config RISCV_SBI_CPUIDLE + bool "RISC-V SBI CPU idle Driver" + depends on RISCV_SBI + select DT_IDLE_STATES + select CPU_IDLE_MULTIPLE_DRIVERS + select DT_IDLE_GENPD if PM_GENERIC_DOMAINS_OF + help + Select this option to enable RISC-V SBI firmware based CPU idle + driver for RISC-V systems. This drivers also supports hierarchical + DT based layout of the idle state. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 11a26cef279f..a36922c18510 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -35,3 +35,7 @@ obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o # POWERPC drivers obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o + +############################################################################### +# RISC-V drivers +obj-$(CONFIG_RISCV_SBI_CPUIDLE) += cpuidle-sbi.o diff --git a/drivers/cpuidle/cpuidle-sbi.c b/drivers/cpuidle/cpuidle-sbi.c new file mode 100644 index 000000000000..abbcabca0e91 --- /dev/null +++ b/drivers/cpuidle/cpuidle-sbi.c @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V SBI CPU idle driver. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#define pr_fmt(fmt) "cpuidle-sbi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dt_idle_states.h" +#include "dt_idle_genpd.h" + +struct sbi_cpuidle_data { + u32 *states; + struct device *dev; +}; + +struct sbi_domain_state { + bool available; + u32 state; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct sbi_cpuidle_data, sbi_cpuidle_data); +static DEFINE_PER_CPU(struct sbi_domain_state, domain_state); +static bool sbi_cpuidle_use_osi; +static bool sbi_cpuidle_use_cpuhp; +static bool sbi_cpuidle_pd_allow_domain_state; + +static inline void sbi_set_domain_state(u32 state) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + data->available = true; + data->state = state; +} + +static inline u32 sbi_get_domain_state(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + return data->state; +} + +static inline void sbi_clear_domain_state(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + data->available = false; +} + +static inline bool sbi_is_domain_state_available(void) +{ + struct sbi_domain_state *data = this_cpu_ptr(&domain_state); + + return data->available; +} + +static int sbi_suspend_finisher(unsigned long suspend_type, + unsigned long resume_addr, + unsigned long opaque) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND, + suspend_type, resume_addr, opaque, 0, 0, 0); + + return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0; +} + +static int sbi_suspend(u32 state) +{ + if (state & SBI_HSM_SUSP_NON_RET_BIT) + return cpu_suspend(state, sbi_suspend_finisher); + else + return sbi_suspend_finisher(state, 0, 0); +} + +static int sbi_cpuidle_enter_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + u32 *states = __this_cpu_read(sbi_cpuidle_data.states); + + return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, idx, states[idx]); +} + +static int __sbi_enter_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx, + bool s2idle) +{ + struct sbi_cpuidle_data *data = this_cpu_ptr(&sbi_cpuidle_data); + u32 *states = data->states; + struct device *pd_dev = data->dev; + u32 state; + int ret; + + ret = cpu_pm_enter(); + if (ret) + return -1; + + /* Do runtime PM to manage a hierarchical CPU toplogy. */ + rcu_irq_enter_irqson(); + if (s2idle) + dev_pm_genpd_suspend(pd_dev); + else + pm_runtime_put_sync_suspend(pd_dev); + rcu_irq_exit_irqson(); + + if (sbi_is_domain_state_available()) + state = sbi_get_domain_state(); + else + state = states[idx]; + + ret = sbi_suspend(state) ? -1 : idx; + + rcu_irq_enter_irqson(); + if (s2idle) + dev_pm_genpd_resume(pd_dev); + else + pm_runtime_get_sync(pd_dev); + rcu_irq_exit_irqson(); + + cpu_pm_exit(); + + /* Clear the domain state to start fresh when back from idle. */ + sbi_clear_domain_state(); + return ret; +} + +static int sbi_enter_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + return __sbi_enter_domain_idle_state(dev, drv, idx, false); +} + +static int sbi_enter_s2idle_domain_idle_state(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int idx) +{ + return __sbi_enter_domain_idle_state(dev, drv, idx, true); +} + +static int sbi_cpuidle_cpuhp_up(unsigned int cpu) +{ + struct device *pd_dev = __this_cpu_read(sbi_cpuidle_data.dev); + + if (pd_dev) + pm_runtime_get_sync(pd_dev); + + return 0; +} + +static int sbi_cpuidle_cpuhp_down(unsigned int cpu) +{ + struct device *pd_dev = __this_cpu_read(sbi_cpuidle_data.dev); + + if (pd_dev) { + pm_runtime_put_sync(pd_dev); + /* Clear domain state to start fresh at next online. */ + sbi_clear_domain_state(); + } + + return 0; +} + +static void sbi_idle_init_cpuhp(void) +{ + int err; + + if (!sbi_cpuidle_use_cpuhp) + return; + + err = cpuhp_setup_state_nocalls(CPUHP_AP_CPU_PM_STARTING, + "cpuidle/sbi:online", + sbi_cpuidle_cpuhp_up, + sbi_cpuidle_cpuhp_down); + if (err) + pr_warn("Failed %d while setup cpuhp state\n", err); +} + +static const struct of_device_id sbi_cpuidle_state_match[] = { + { .compatible = "riscv,idle-state", + .data = sbi_cpuidle_enter_state }, + { }, +}; + +static bool sbi_suspend_state_is_valid(u32 state) +{ + if (state > SBI_HSM_SUSPEND_RET_DEFAULT && + state < SBI_HSM_SUSPEND_RET_PLATFORM) + return false; + if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT && + state < SBI_HSM_SUSPEND_NON_RET_PLATFORM) + return false; + return true; +} + +static int sbi_dt_parse_state_node(struct device_node *np, u32 *state) +{ + int err = of_property_read_u32(np, "riscv,sbi-suspend-param", state); + + if (err) { + pr_warn("%pOF missing riscv,sbi-suspend-param property\n", np); + return err; + } + + if (!sbi_suspend_state_is_valid(*state)) { + pr_warn("Invalid SBI suspend state %#x\n", *state); + return -EINVAL; + } + + return 0; +} + +static int sbi_dt_cpu_init_topology(struct cpuidle_driver *drv, + struct sbi_cpuidle_data *data, + unsigned int state_count, int cpu) +{ + /* Currently limit the hierarchical topology to be used in OSI mode. */ + if (!sbi_cpuidle_use_osi) + return 0; + + data->dev = dt_idle_genpd_attach_cpu(cpu, "sbi"); + if (IS_ERR_OR_NULL(data->dev)) + return PTR_ERR_OR_ZERO(data->dev); + + /* + * Using the deepest state for the CPU to trigger a potential selection + * of a shared state for the domain, assumes the domain states are all + * deeper states. + */ + drv->states[state_count - 1].enter = sbi_enter_domain_idle_state; + drv->states[state_count - 1].enter_s2idle = sbi_enter_s2idle_domain_idle_state; + sbi_cpuidle_use_cpuhp = true; + + return 0; +} + +static int sbi_cpuidle_dt_init_states(struct device *dev, + struct cpuidle_driver *drv, + unsigned int cpu, + unsigned int state_count) +{ + struct sbi_cpuidle_data *data = per_cpu_ptr(&sbi_cpuidle_data, cpu); + struct device_node *state_node; + struct device_node *cpu_node; + u32 *states; + int i, ret; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + return -ENODEV; + + states = devm_kcalloc(dev, state_count, sizeof(*states), GFP_KERNEL); + if (!states) { + ret = -ENOMEM; + goto fail; + } + + /* Parse SBI specific details from state DT nodes */ + for (i = 1; i < state_count; i++) { + state_node = of_get_cpu_state_node(cpu_node, i - 1); + if (!state_node) + break; + + ret = sbi_dt_parse_state_node(state_node, &states[i]); + of_node_put(state_node); + + if (ret) + return ret; + + pr_debug("sbi-state %#x index %d\n", states[i], i); + } + if (i != state_count) { + ret = -ENODEV; + goto fail; + } + + /* Initialize optional data, used for the hierarchical topology. */ + ret = sbi_dt_cpu_init_topology(drv, data, state_count, cpu); + if (ret < 0) + return ret; + + /* Store states in the per-cpu struct. */ + data->states = states; + +fail: + of_node_put(cpu_node); + + return ret; +} + +static void sbi_cpuidle_deinit_cpu(int cpu) +{ + struct sbi_cpuidle_data *data = per_cpu_ptr(&sbi_cpuidle_data, cpu); + + dt_idle_genpd_detach_cpu(data->dev); + sbi_cpuidle_use_cpuhp = false; +} + +static int sbi_cpuidle_init_cpu(struct device *dev, int cpu) +{ + struct cpuidle_driver *drv; + unsigned int state_count = 0; + int ret = 0; + + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); + if (!drv) + return -ENOMEM; + + drv->name = "sbi_cpuidle"; + drv->owner = THIS_MODULE; + drv->cpumask = (struct cpumask *)cpumask_of(cpu); + + /* RISC-V architectural WFI to be represented as state index 0. */ + drv->states[0].enter = sbi_cpuidle_enter_state; + drv->states[0].exit_latency = 1; + drv->states[0].target_residency = 1; + drv->states[0].power_usage = UINT_MAX; + strcpy(drv->states[0].name, "WFI"); + strcpy(drv->states[0].desc, "RISC-V WFI"); + + /* + * If no DT idle states are detected (ret == 0) let the driver + * initialization fail accordingly since there is no reason to + * initialize the idle driver if only wfi is supported, the + * default archictectural back-end already executes wfi + * on idle entry. + */ + ret = dt_init_idle_driver(drv, sbi_cpuidle_state_match, 1); + if (ret <= 0) { + pr_debug("HART%ld: failed to parse DT idle states\n", + cpuid_to_hartid_map(cpu)); + return ret ? : -ENODEV; + } + state_count = ret + 1; /* Include WFI state as well */ + + /* Initialize idle states from DT. */ + ret = sbi_cpuidle_dt_init_states(dev, drv, cpu, state_count); + if (ret) { + pr_err("HART%ld: failed to init idle states\n", + cpuid_to_hartid_map(cpu)); + return ret; + } + + ret = cpuidle_register(drv, NULL); + if (ret) + goto deinit; + + cpuidle_cooling_register(drv); + + return 0; +deinit: + sbi_cpuidle_deinit_cpu(cpu); + return ret; +} + +static int sbi_cpuidle_pd_power_off(struct generic_pm_domain *pd) +{ + struct genpd_power_state *state = &pd->states[pd->state_idx]; + u32 *pd_state; + + if (!state->data) + return 0; + + if (!sbi_cpuidle_pd_allow_domain_state) + return -EBUSY; + + /* OSI mode is enabled, set the corresponding domain state. */ + pd_state = state->data; + sbi_set_domain_state(*pd_state); + + return 0; +} + +static void sbi_cpuidle_domain_sync_state(struct device *dev) +{ + /* + * All devices have now been attached/probed to the PM domain + * topology, hence it's fine to allow domain states to be picked. + */ + sbi_cpuidle_pd_allow_domain_state = true; +} + +static struct dt_idle_genpd_ops sbi_genpd_ops = { + .parse_state_node = sbi_dt_parse_state_node, +}; + +static int sbi_cpuidle_probe(struct platform_device *pdev) +{ + int cpu, ret; + struct cpuidle_driver *drv; + struct cpuidle_device *dev; + struct device_node *np, *pds_node; + + /* Detect OSI support based on CPU DT nodes */ + sbi_cpuidle_use_osi = true; + for_each_possible_cpu(cpu) { + np = of_cpu_device_node_get(cpu); + if (np && + of_find_property(np, "power-domains", NULL) && + of_find_property(np, "power-domain-names", NULL)) { + continue; + } else { + sbi_cpuidle_use_osi = false; + break; + } + } + + if (sbi_cpuidle_use_osi) + sbi_genpd_ops.power_off = sbi_cpuidle_pd_power_off; + + /* Populate generic power domains from DT nodes */ + pds_node = of_find_node_by_path("/cpus/sbi-power-domains"); + if (pds_node) { + ret = dt_idle_genpd_probe(&sbi_genpd_ops, pds_node); + of_node_put(pds_node); + if (ret) + return ret; + } + + /* Initialize CPU idle driver for each CPU */ + for_each_possible_cpu(cpu) { + ret = sbi_cpuidle_init_cpu(&pdev->dev, cpu); + if (ret) { + pr_debug("HART%ld: idle driver init failed\n", + cpuid_to_hartid_map(cpu)); + goto out_fail; + } + } + + /* Setup CPU hotplut notifiers */ + sbi_idle_init_cpuhp(); + + pr_info("idle driver registered for all CPUs\n"); + + return 0; + +out_fail: + while (--cpu >= 0) { + dev = per_cpu(cpuidle_devices, cpu); + drv = cpuidle_get_cpu_driver(dev); + cpuidle_unregister(drv); + sbi_cpuidle_deinit_cpu(cpu); + } + + return ret; +} + +static struct platform_driver sbi_cpuidle_driver = { + .probe = sbi_cpuidle_probe, + .driver = { + .name = "sbi-cpuidle", + .sync_state = sbi_cpuidle_domain_sync_state, + }, +}; + +static int __init sbi_cpuidle_init(void) +{ + int ret; + struct platform_device *pdev; + + /* + * The SBI HSM suspend function is only available when: + * 1) SBI HSM extension is available + * 2) SBI version is 0.3 or higher + */ + if (sbi_major_version() < 0 || + sbi_minor_version() < 3 || + sbi_probe_extension(SBI_EXT_HSM) <= 0) { + pr_info("HSM suspend not available\n"); + return 0; + } + + ret = platform_driver_register(&sbi_cpuidle_driver); + if (ret) + return ret; + + pdev = platform_device_register_simple("sbi-cpuidle", + -1, NULL, 0); + if (IS_ERR(pdev)) { + platform_driver_unregister(&sbi_cpuidle_driver); + return PTR_ERR(pdev); + } + + return 0; +} +device_initcall(sbi_cpuidle_init); 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Sun, 21 Feb 2021 09:39:12 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 7/8] dt-bindings: Add bindings documentation for RISC-V idle states Date: Sun, 21 Feb 2021 15:07:57 +0530 Message-Id: <20210221093758.210981-8-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:39:06 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: a003a7d3-3049-43ee-a06d-08d8d64c8baf X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CqvOyqEceHG8HPxvjhTFNgStTIHAsy11LT7jo35kmNFNx64EW/gy0ZtEqio3g4c9Iv97xmiNMWDdyTwLvlgtDwlEFGKABrVkSEecnEZsmjUjDHfkUtacO+KMFMcGtqm6q60eFGiAYMdkUMGyPVEP37uN1/uqCge4BQM+zCb7QyORIS+qpAuF11ajFsY+X14DX/fz9vaUkp3uw23jJCgU+yQrOPd7un0nzbe9YD+q1Z7tRXiDa0KbQPcbTwu/SH2WrLPogr1EYBB4Izy4kES3DUbjka5A6wA7JU9wlSzP0ox1VUEB3D5WTgHfL4QB8+NL8Od8RbtYmby1/QC6tU7Lov0F7DtrHJig7Z1kt/rmQD0+WxKWo+gmrddnNNGMHgDEfvIJO6rgCcyVQa/n5IwdmoKfWtL0yaBM7dPZi9zNbR49UHSe+AVs3WslY+SKrAAKb6V0ddwNS2jxWrOBzULulhCwKCX3IpIao5sAz5edvfBljzAYbqf6Sb76mPNehOlcgUZ8mH7CgOxn5I92RIWkI5LqL9HKy7iKOmAquPObEDXuqcYoa17ZlenaUlCma1D8PpLGp6vwosL7r0wmJn31Xg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(5660300002)(54906003)(110136005)(966005)(4326008)(66476007)(36756003)(83380400001)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: jGL5RoVvYa7mAQxgtWh7QjiUUB8cPVAbCv+ykOUukIvzOdNFBa6+rUrP//DeVkxMqsHp6NRchZPJgSWc8g0V3n8xlzHNUeFRHA0Y7yPgUVmhSzl3xOdqn5iyaGY+WGwpctDpsMZHfn8vLUbPr9K/xN6u3LuUImQ9YIVW9yX5YJnRYlIY/QlHJQa6+57s548z260coYBG7o3D4yhEPIHZgMwTQtEVYU8vgexLd90PNqFIYsXdtllWI7Dqn/5U0r5+W2jLAUJ4CERgSpUU8gzZYLdCkTrp9ujBlVzMxm2WCu6bJhrqk4ySlbnRhuvX7PkJYNOlUY5wtz6mJGXec8HzYHTnRqtnXosuC09O7tH7dZSonEFQKVDsoEjrLN+OAi9Hx63i7+Ravsd3XhIvtxoq5Wdt41OrtvkNdHhfSNUZVYg2O4XwNr/7CSbK1cHaCbLVoDGxyECwJojC/0Nz+l8PHaE6f1tExqNFIiGuKuHJEdI5nwBWul0ehYFRlCR9Ykg/F6t3IYrUjCjk83qumLjy0WQyQKPxy+Ton6TwuS4+sueP9WbOvDY1NWxIqszuJpBt7fHCh4U98vJNjajT2wIoEiQ72n+r7bwDYZlsWbZsAoe9Jwkr0YHGwAi+Vs2yiSlzIsN+2dr5bJK2ZS/M3rzqAJ+TeEIrvnq2+FFRojfonIzMy7RLXrRZ6QDsz8F1rgQekf4Euqo/zX3DRgleeV2PyLRdFi9omjUugMdbvdGKrTz79XSsyDSrfkPf2KOPl/pTyTe4UKjAfubl4kwVQ54cwFxd4Q2xxdpcuaO8sCOwiyjvVRwzv2NCnGeWBfVG5QzCpaPrEEaEFm7KVjaKqUyvA3r6AwmJM6QsR+CjQWEWS7yaFe4H/sCcl/7qP/eAk1C6FwSmxUdpI6xRtlFE3GNX2DggikOFU+NauOyJVZiLvISxEsaA21nwGX25mkKewo5RdBUo3iq+nGQ9lL9HkUQPppIlABXkNUkntFjZWlC7QmeHuiwDR0XNaN1hAnOazMACRR3lq6mB+czEg+yxacrvHOhvLktB+jCywMjyg9zKfG7OW6izZu0M1+hMjhaODQx4fQ58J7oDkMei4qPlA8uNEiHgo6mqmS01+ygZE9CLVWz3He+JRsEL8ElJHjomNuqWSSIRE6DDcVGTcKoKjv+Ck1kHdn+PQimhwKywIz1a4BC92T9FPXaYA9VZ0AWzne2cUMyGEp8f2q9FCVFbj5Mbg0P22VwelYQ6/1dFWLSsTWyMtMTEk87MBGaIyFahTVuDg/ux14uMf7uBbBVXgQkGbny1gnAA96Sik0BeZ6C5w5tSSWwEM2pCaf9oNlDG69P/ X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: a003a7d3-3049-43ee-a06d-08d8d64c8baf X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:39:12.4095 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pcP1tl2zSRJTiqHvl/lbE6IEIHh0fyZVVXnnJyBGXMFTbIxDbLXuqii4iL+baYGrJMBTfl2M/mCqAHhxkbI3+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The RISC-V CPU idle states will be described in DT under the /cpus/riscv-idle-states DT node. This patch adds the bindings documentation for riscv-idle-states DT nodes and idle state DT nodes under it. Signed-off-by: Anup Patel --- .../bindings/riscv/idle-states.yaml | 250 ++++++++++++++++++ 1 file changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/idle-states.yaml diff --git a/Documentation/devicetree/bindings/riscv/idle-states.yaml b/Documentation/devicetree/bindings/riscv/idle-states.yaml new file mode 100644 index 000000000000..3eff763fed23 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/idle-states.yaml @@ -0,0 +1,250 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/idle-states.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V idle states binding description + +maintainers: + - Anup Patel + +description: |+ + RISC-V systems can manage power consumption dynamically, where HARTs + (or CPUs) [1] can be put in different platform specific suspend (or + idle) states (ranging from simple WFI, power gating, etc). The RISC-V + SBI [2] hart state management extension provides a standard mechanism + for OSes to request HART state transitions. + + The platform specific suspend (or idle) states of a hart can be either + retentive or non-rententive in nature. A retentive suspend state will + preserve hart register and CSR values for all privilege modes whereas + a non-retentive suspend state will not preserve hart register and CSR + values. The suspend (or idle) state entered by executing the WFI + instruction is considered standard on all RISC-V systems and therefore + must not be listed in device tree. + + The device tree binding definition for RISC-V idle states described + in this document is quite similar to the ARM idle states [3]. + + References + + [1] RISC-V Linux Kernel documentation - CPUs bindings + Documentation/devicetree/bindings/riscv/cpus.yaml + + [2] RISC-V Supervisor Binary Interface (SBI) + http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc + + [3] ARM idle states binding description - Idle states bindings + Documentation/devicetree/bindings/arm/idle-states.yaml + +properties: + $nodename: + const: riscv-idle-states + +patternProperties: + "^(cpu|cluster)-": + type: object + description: | + Each state node represents an idle state description and must be + defined as follows. + + properties: + compatible: + const: riscv,idle-state + + local-timer-stop: + description: + If present the CPU local timer control logic is lost on state + entry, otherwise it is retained. + type: boolean + + entry-latency-us: + description: + Worst case latency in microseconds required to enter the idle state. + + exit-latency-us: + description: + Worst case latency in microseconds required to exit the idle state. + The exit-latency-us duration may be guaranteed only after + entry-latency-us has passed. + + min-residency-us: + description: + Minimum residency duration in microseconds, inclusive of preparation + and entry, for this idle state to be considered worthwhile energy + wise (refer to section 2 of this document for a complete description). + + wakeup-latency-us: + description: | + Maximum delay between the signaling of a wake-up event and the CPU + being able to execute normal code again. If omitted, this is assumed + to be equal to: + + entry-latency-us + exit-latency-us + + It is important to supply this value on systems where the duration + of PREP phase (see diagram 1, section 2) is non-neglibigle. In such + systems entry-latency-us + exit-latency-us will exceed + wakeup-latency-us by this duration. + + idle-state-name: + $ref: /schemas/types.yaml#/definitions/string + description: + A string used as a descriptive name for the idle state. + + required: + - compatible + - entry-latency-us + - exit-latency-us + - min-residency-us + +additionalProperties: false + +examples: + - | + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x0>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 + &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + + cpu_intc0: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x1>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 + &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + + cpu_intc1: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@10 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x10>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 + &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + + cpu_intc10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@11 { + device_type = "cpu"; + compatible = "riscv"; + reg = <0x11>; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 + &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + + cpu_intc11: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + riscv-idle-states { + CPU_RET_0_0: cpu-retentive-0-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x10000000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CPU_NONRET_0_0: cpu-nonretentive-0-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x90000000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_RET_0: cluster-retentive-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x11000000>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CLUSTER_NONRET_0: cluster-nonretentive-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x91000000>; + local-timer-stop; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + + CPU_RET_1_0: cpu-retentive-1-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x10000010>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CPU_NONRET_1_0: cpu-nonretentive-1-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x90000010>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_RET_1: cluster-retentive-1 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x11000010>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CLUSTER_NONRET_1: cluster-nonretentive-1 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x91000010>; + local-timer-stop; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; + +... 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Wysocki" , Pavel Machek , Rob Herring Cc: Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Anup Patel Subject: [RFC PATCH 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Date: Sun, 21 Feb 2021 15:07:58 +0530 Message-Id: <20210221093758.210981-9-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210221093758.210981-1-anup.patel@wdc.com> References: <20210221093758.210981-1-anup.patel@wdc.com> X-Originating-IP: [122.171.171.12] X-ClientProxiedBy: MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.171.12) by MA1PR0101CA0009.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; Sun, 21 Feb 2021 09:39:12 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: a89fd469-a531-4f92-6311-08d8d64c8f34 X-MS-TrafficTypeDiagnostic: DM5PR04MB0459: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:849; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /tE9OkLir7zd2rs1U0zbacDO2r1C9EZ18Zu62+8Jw/3SQ/w0rjm86HyPVJDOkfK7nQ6hnYvwZogmGs6wnD/ME20D0EQ7iILrNtxPkvSasLbvCkC+P7pCKH57dkLHP5N+1XAMdWIEZ8b502rmN4+PYABcVt+ah4m45JLVC8SMhCFugnBknhDB8/BX6V/edi3+wpn9nUOdFVCxTuh5TaRu/YLsvE5DWzyEbaMEF5ziwVTJ0EUMDvzf48+g13bDYsf1XsBJPm+L9892YX4D6zOySiLOz86QMvkjlWMKwvD5YhCV2XZYvsv481hcRp8Et/1GtrlNaytCKfOAaUQ65qVnW5yybU+d9MXC960Jkb8r6fd0VsEUXYwDx22BSXqM2kW+AZBKP7F1DtRxQsTyCDq6Gjvi2htLBzvvcFzaGT49FTfJLzAJITdxyppppxVbeEI9ylMceXGfkVFK4rkywZp1HCbiEH06Fsyyz6J7s7ePjzUSfTUsZvcM63Uj0TabFPq2PrvfvLZopEIfaBcJAgEkNw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR04MB6201.namprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(376002)(396003)(346002)(39860400002)(136003)(55016002)(44832011)(66556008)(8676002)(2616005)(6666004)(16526019)(7696005)(5660300002)(54906003)(110136005)(4326008)(66476007)(36756003)(478600001)(1076003)(956004)(8886007)(316002)(2906002)(66946007)(86362001)(52116002)(7416002)(8936002)(26005)(186003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: +p5XIvWMHE1CKtH0bnPvkZDmUVuyer0LPRcyKhqgT16KyPNge31u63NQrxEhWvudbeiASYZC01Jg96+HblgTzpmZvwBnq31JNpzDbEAxbCgdleW1JViWvMqMnFknPx8sUvByAZ0gzBsGjtx7AuTMpGi3TNexcJ8k6l0RSvTNRfbkXqYuFQFoNl2uzb1MArZzQ3gwofMnICSzVFud7pnI5q0JY0JdOv/NZy1qyPeOCTl3NEwyVbtO6/lFAQyQEAYEyKkE+XrIo34t61nlsrwPcgHpwKN1NndRYZAd1htSNIxXCtvgFXiJZb8WeoCVVqP1b48MhHzVAfW7TZbXv23l1JlsHg4Vz3OEWPEHOWyEXnQjK8whGdKzilhh3PPna+iR7JxsiKsfJxwm6x2i3yPpYwQxhJCstDTATgGw2I2F5Sp5tkvLQJ/H2xq1vSktNKJfZ2Y8V8Lhi4+uUi0FrXeCWS1GnUnGTdv/dn8lq9PYGM8hJMNWMH4dE7lICMcbLITXycTs8bv/KxJU6WbUsKDjP0nUeqCWg+YwkiYI/QPpE5gdSOgtvSiKim3w0XYfwwkdDJOL66R5jtJZE9Z/NUky/QLcd6NGMhCd8FP/11Sv95OfGkn/IHa1uIEue0uZ9iZcvcwX6dXIpAovhkVW8oG7TfkF1FV4ZtD5GmHu9GLNIXKd1ydCpN+KSeeLSCx6qjKgHkBnNZVA/EjHSFuHcEbgytsSw/cLr8SzGvtiuWwPs6B0LR+HcNNHJZKnna5qod+yrFVEdoeS5zjCLCrV9IbdLHWAJS8gRKkTrrkXDCIrMzlBRuBQQ0B5l3wR8LOuMhChv2xEv5/K4obyniT+fzPZ+iKfu4DnjliF7XNfyTbNXCYkFK7y0J1z4Ov4IpRrEN4EfULNeNJDeKvMZCiG7AuOArWx3XoKK38HSiUue9Av5BTKeM9FgDKPwyNFC+fW5cwufMCu0rU2c+4Uh4jJ5X1e6qW0V1YKjw+CoxMGIEG6A9hM/VvQT9+++0ZZ55pGf4C0VTT/M7DX7DeltE+PvMRURu6fr+/4Zhdj26X75ufSvEKPFoDZbOsuMRBHjHdQ4ANvRx6NYZE+o7sp7p/POwiAn/yVxgSYpM1Gwte3BH0AeI5bNOZAleQ3DmIsL93JXy4Zr3BkVvaJ1sAFw+cFhbP28HRGpLHB22RzAr/QCb39+5CemPR0nTgoCjIi7yaVnzToTs1OnbCj3aIjn2Fkavp0EV+lnkB0ugfKq+P51arAXHFsLEYM10pD+KUpaJVbudqwZ1FhwhOaLbzw8GEqUL5//jv1103s/Cp6Rr+WywwfDtaq/uuk8clkSIHUVdr8AlF3 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: a89fd469-a531-4f92-6311-08d8d64c8f34 X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2021 09:39:18.3087 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XTKccmaHJ8s/xfEJAH2NNkIMXe70m5VaXPNQY1CsfTk0nyIvFpEeAwfuFNZXUoInanIhew8kns59tyerEjsp4w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR04MB0459 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test SBI HSM Supend on QEMU. Signed-off-by: Anup Patel --- arch/riscv/Kconfig.socs | 3 +++ arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 3284d5c291be..5f6f4a520772 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -19,6 +19,9 @@ config SOC_VIRT select GOLDFISH select RTC_DRV_GOLDFISH if RTC_CLASS select SIFIVE_PLIC + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select RISCV_SBI_CPUIDLE if CPU_IDLE help This enables support for QEMU Virt Machine. diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index dc4927c0e44b..aac26c20bbf5 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -19,6 +19,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 332e43a4a2c3..2285c95e34b3 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y CONFIG_ARCH_RV32I=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y