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[209.132.180.67]) by mx.google.com with ESMTP id z64si5697404pgb.183.2018.03.30.07.36.49; Fri, 30 Mar 2018 07:36:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x7OOpeXF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752086AbeC3Ogr (ORCPT + 29 others); Fri, 30 Mar 2018 10:36:47 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:47062 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751163AbeC3Ogp (ORCPT ); Fri, 30 Mar 2018 10:36:45 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w2UEUtBB009411; Fri, 30 Mar 2018 09:30:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1522420255; bh=0ObDBsF0R8EyioL6mtnqU0UsedPXPXHiKgnKSTlj1Z8=; h=From:To:CC:Subject:Date; b=x7OOpeXFQFdnxI+fjLGlCCT48I7YRU0qt4b8VOv/KNvRdako1t5IGvLx2ScK7IXpH eEVz95gJhBsnhliC+wLQnL+97V5+naU0JXSB7/KPV95tFIafwbTl0du6JBvOyHvHny LR9FWDu1UNf00mSBPTq0r4c80+JodCrZb9B9222k= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2UEUt4w022782; Fri, 30 Mar 2018 09:30:55 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 30 Mar 2018 09:30:55 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 30 Mar 2018 09:30:55 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2UEUpe4010931; Fri, 30 Mar 2018 09:30:52 -0500 From: Sekhar Nori To: Boris Brezillon CC: Richard Weinberger , David Woodhouse , Brian Norris , Marek Vasut , Cyrille Pitchen , Sekhar Nori , , , Linux ARM Mailing List , David Lechner , Bartosz Golaszewski Subject: [PATCH] mtd: nand: davinci: don't acquire and enable clock Date: Fri, 30 Mar 2018 20:00:51 +0530 Message-ID: <20180330143051.26423-1-nsekhar@ti.com> X-Mailer: git-send-email 2.16.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org NAND itself is an asynchronous interface, it does not have any clock input. DaVinci NAND driver acquires clock for AEMIF (asynchronous external memory interface) which is an on-chip IP to which NAND is connected. The same clock is also enabled in AEMIF driver (either present drivers/memory or from machine code for some older platforms). AEMIF timing must be initialized before NAND can be accessed. This ensures that AEMIF clock is enabled too. Remove the superfluous clock acquisition and enable in DaVinci NAND driver. Tested on K2L, K2HK, K2E, DA850 EVM, DA850 LCDK in device-tree boot and DM644x EVM in legacy boot. Signed-off-by: Sekhar Nori --- Hi Boris, If/when this patch gets accepted, it will nice to put this on an immutable branch others can merge. There is potential cleanup in drivers/clock and in DaVinci machine code that will depend on this. Thanks, Sekhar drivers/mtd/nand/raw/davinci_nand.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) -- 2.16.2 Tested-by: Bartosz Golaszewski diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 0f09518d980f..7255a0d94374 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -55,7 +54,6 @@ struct davinci_nand_info { struct nand_chip chip; struct device *dev; - struct clk *clk; bool is_readmode; @@ -703,22 +701,6 @@ static int nand_davinci_probe(struct platform_device *pdev) /* Use board-specific ECC config */ info->chip.ecc.mode = pdata->ecc_mode; - ret = -EINVAL; - - info->clk = devm_clk_get(&pdev->dev, "aemif"); - if (IS_ERR(info->clk)) { - ret = PTR_ERR(info->clk); - dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(info->clk); - if (ret < 0) { - dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", - ret); - goto err_clk_enable; - } - spin_lock_irq(&davinci_nand_lock); /* put CSxNAND into NAND mode */ @@ -732,7 +714,7 @@ static int nand_davinci_probe(struct platform_device *pdev) ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL); if (ret < 0) { dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); - goto err; + return ret; } switch (info->chip.ecc.mode) { @@ -838,9 +820,6 @@ static int nand_davinci_probe(struct platform_device *pdev) nand_cleanup(&info->chip); err: - clk_disable_unprepare(info->clk); - -err_clk_enable: spin_lock_irq(&davinci_nand_lock); if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) ecc4_busy = false; @@ -859,8 +838,6 @@ static int nand_davinci_remove(struct platform_device *pdev) nand_release(nand_to_mtd(&info->chip)); - clk_disable_unprepare(info->clk); - return 0; }