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Wed, 17 Feb 2021 20:50:02 -0800 Envelope-to: shubhrajyoti.datta@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com, miquel.raynal@bootlin.com Received: from [10.140.6.59] (port=35054 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lCbGM-0004qG-7d; Wed, 17 Feb 2021 20:50:02 -0800 From: Shubhrajyoti Datta To: CC: , , , , , , "Shubhrajyoti Datta" Subject: [PATCH v9 2/7] clk: clock-wizard: Add the clockwizard to clk directory Date: Thu, 18 Feb 2021 10:19:46 +0530 Message-ID: <1613623791-4598-3-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4792213b-f466-46c2-2630-08d8d3c8a94d X-MS-TrafficTypeDiagnostic: BYAPR02MB5941: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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And delete the driver from the staging as it is in drivers/clk. Signed-off-by: Shubhrajyoti Datta --- v7: Combined the patch for deletion and add of the driver dropping the ack from Greg for the staging as it is a combined patch. Add vendor prefix to speedgrade v8: No change v9: No change drivers/clk/Kconfig | 9 +++++++ drivers/clk/Makefile | 1 + .../clk-xlnx-clock-wizard.c | 6 +++-- drivers/staging/Kconfig | 2 -- drivers/staging/Makefile | 1 - drivers/staging/clocking-wizard/Kconfig | 10 -------- drivers/staging/clocking-wizard/Makefile | 2 -- drivers/staging/clocking-wizard/TODO | 12 --------- drivers/staging/clocking-wizard/dt-binding.txt | 30 ---------------------- 9 files changed, 14 insertions(+), 59 deletions(-) rename drivers/{staging/clocking-wizard => clk}/clk-xlnx-clock-wizard.c (98%) delete mode 100644 drivers/staging/clocking-wizard/Kconfig delete mode 100644 drivers/staging/clocking-wizard/Makefile delete mode 100644 drivers/staging/clocking-wizard/TODO delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c715d46..d210ed2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -359,6 +359,15 @@ config COMMON_CLK_FIXED_MMIO help Support for Memory Mapped IO Fixed clocks +config COMMON_CLK_XLNX_CLKWZRD + tristate "Xilinx Clocking Wizard" + depends on COMMON_CLK && OF + help + Support for the Xilinx Clocking Wizard IP core clock generator. + Adds support for clocking wizard and compatible. + This driver supports the Xilinx clocking wizard programmable clock + synthesizer. The number of output is configurable in the design. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index da8fcf1..1ad6414 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o # please keep this section sorted lexicographically by directory path name obj-y += actions/ diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c similarity index 98% rename from drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c rename to drivers/clk/clk-xlnx-clock-wizard.c index e52a64b..1bab68e 100644 --- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -2,9 +2,11 @@ /* * Xilinx 'Clocking Wizard' driver * - * Copyright (C) 2013 - 2014 Xilinx + * Copyright (C) 2013 - 2020 Xilinx * * Sören Brinkmann + * Shubhrajyoti Datta + * */ #include @@ -146,7 +148,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) if (IS_ERR(clk_wzrd->base)) return PTR_ERR(clk_wzrd->base); - ret = of_property_read_u32(np, "speed-grade", &clk_wzrd->speed_grade); + ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); if (!ret) { if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { dev_warn(&pdev->dev, "invalid speed grade '%d'\n", diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 2d03104..38a9287 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -76,8 +76,6 @@ source "drivers/staging/gs_fpgaboot/Kconfig" source "drivers/staging/unisys/Kconfig" -source "drivers/staging/clocking-wizard/Kconfig" - source "drivers/staging/fbtft/Kconfig" source "drivers/staging/fsl-dpaa2/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 757a892..58bceb8 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -28,7 +28,6 @@ obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/ obj-$(CONFIG_GOLDFISH) += goldfish/ obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/ obj-$(CONFIG_UNISYSSPAR) += unisys/ -obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ obj-$(CONFIG_FB_TFT) += fbtft/ obj-$(CONFIG_FSL_DPAA2) += fsl-dpaa2/ obj-$(CONFIG_MOST) += most/ diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig deleted file mode 100644 index 69cf514..0000000 --- a/drivers/staging/clocking-wizard/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Xilinx Clocking Wizard Driver -# - -config COMMON_CLK_XLNX_CLKWZRD - tristate "Xilinx Clocking Wizard" - depends on COMMON_CLK && OF && IOMEM - help - Support for the Xilinx Clocking Wizard IP core clock generator. diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile deleted file mode 100644 index b1f9152..0000000 --- a/drivers/staging/clocking-wizard/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO deleted file mode 100644 index ebe99db..0000000 --- a/drivers/staging/clocking-wizard/TODO +++ /dev/null @@ -1,12 +0,0 @@ -TODO: - - support for fractional multiplier - - support for fractional divider (output 0 only) - - support for set_rate() operations (may benefit from Stephen Boyd's - refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766) - - review arithmetic - - overflow after multiplication? - - maximize accuracy before divisions - -Patches to: - Greg Kroah-Hartman - Sören Brinkmann diff --git a/drivers/staging/clocking-wizard/dt-binding.txt b/drivers/staging/clocking-wizard/dt-binding.txt deleted file mode 100644 index efb67ff..0000000 --- a/drivers/staging/clocking-wizard/dt-binding.txt +++ /dev/null @@ -1,30 +0,0 @@ -Binding for Xilinx Clocking Wizard IP Core - -This binding uses the common clock binding[1]. Details about the devices can be -found in the product guide[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Clocking Wizard Product Guide -https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf - -Required properties: - - compatible: Must be 'xlnx,clocking-wizard' - - reg: Base and size of the cores register space - - clocks: Handle to input clock - - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' - - clock-output-names: Names for the output clocks - -Optional properties: - - speed-grade: Speed grade of the device (valid values are 1..3) - -Example: - clock-generator@40040000 { - reg = <0x40040000 0x1000>; - compatible = "xlnx,clocking-wizard"; - speed-grade = <1>; - clock-names = "clk_in1", "s_axi_aclk"; - clocks = <&clkc 15>, <&clkc 15>; - clock-output-names = "clk_out0", "clk_out1", "clk_out2", - "clk_out3", "clk_out4", "clk_out5", - "clk_out6", "clk_out7"; - }; From patchwork Thu Feb 18 04:49:48 2021 Content-Type: text/plain; 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Wed, 17 Feb 2021 20:50:12 -0800 Envelope-to: shubhrajyoti.datta@xilinx.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, gregkh@linuxfoundation.org, shubhrajyoti.datta@gmail.com, miquel.raynal@bootlin.com Received: from [10.140.6.59] (port=35054 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lCbGV-0004qG-V1; Wed, 17 Feb 2021 20:50:12 -0800 From: Shubhrajyoti Datta To: CC: , , , , , , "Shubhrajyoti Datta" , Chirag Parekh Subject: [PATCH v9 4/7] clk: clock-wizard: Add support for dynamic reconfiguration Date: Thu, 18 Feb 2021 10:19:48 +0530 Message-ID: <1613623791-4598-5-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d5e21265-2821-474f-9d6c-08d8d3c8b114 X-MS-TrafficTypeDiagnostic: PH0PR02MB7349: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1201; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2021 04:50:18.9873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5e21265-2821-474f-9d6c-08d8d3c8b114 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT047.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB7349 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The patch adds support for dynamic reconfiguration of clock output rate. Output clocks are registered as dividers and set rate callback function is used for dynamic reconfiguration. Based on the initial work from Chirag. Signed-off-by: Chirag Parekh Signed-off-by: Shubhrajyoti Datta --- v6: Remove the typecast. use min for capping frequency. use polled timeout v7: Use devm functions Add the spinlock drivers/clk/clk-xlnx-clock-wizard.c | 181 ++++++++++++++++++++++++++++++++++-- 1 file changed, 175 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index fb2d555..5581b24 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -17,6 +17,7 @@ #include #include #include +#include #define WZRD_NUM_OUTPUTS 7 #define WZRD_ACLK_MAX_FREQ 250000000UL @@ -31,8 +32,23 @@ #define WZRD_DIVCLK_DIVIDE_SHIFT 0 #define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) #define WZRD_CLKOUT_DIVIDE_SHIFT 0 +#define WZRD_CLKOUT_DIVIDE_WIDTH 8 #define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) +#define WZRD_DR_MAX_INT_DIV_VALUE 255 +#define WZRD_DR_NUM_RETRIES 10000 +#define WZRD_DR_STATUS_REG_OFFSET 0x04 +#define WZRD_DR_LOCK_BIT_MASK 0x00000001 +#define WZRD_DR_INIT_REG_OFFSET 0x25C +#define WZRD_DR_DIV_TO_PHASE_OFFSET 4 +#define WZRD_DR_BEGIN_DYNA_RECONF 0x03 + +/* Get the mask from width */ +#define div_mask(width) ((1 << (width)) - 1) + +/* Extract divider instance from clock hardware instance */ +#define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw) + enum clk_wzrd_int_clks { wzrd_clk_mul, wzrd_clk_mul_div, @@ -64,6 +80,29 @@ struct clk_wzrd { bool suspended; }; +/** + * struct clk_wzrd_divider - clock divider specific to clk_wzrd + * + * @hw: handle between common and hardware-specific interfaces + * @base: base address of register containing the divider + * @offset: offset address of register containing the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @flags: clk_wzrd divider flags + * @table: array of value/divider pairs, last entry should have div = 0 + * @lock: register lock + */ +struct clk_wzrd_divider { + struct clk_hw hw; + void __iomem *base; + u16 offset; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; + spinlock_t *lock; /* divider lock */ +}; + #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) /* maximum frequencies for input/output clocks per speed grade */ @@ -73,6 +112,132 @@ static const unsigned long clk_wzrd_max_freq[] = { 1066000000UL }; +/* spin lock variable for clk_wzrd */ +static DEFINE_SPINLOCK(clkwzrd_lock); + +static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); + void __iomem *div_addr = divider->base + divider->offset; + unsigned int val; + + val = readl(div_addr) >> divider->shift; + val &= div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int err = 0; + u32 value; + unsigned long flags = 0; + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); + void __iomem *div_addr = divider->base + divider->offset; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + value = DIV_ROUND_CLOSEST(parent_rate, rate); + + /* Cap the value to max */ + min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); + + /* Set divisor and clear phase offset */ + writel(value, div_addr); + writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); + + /* Check status register */ + err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, + value, value & WZRD_DR_LOCK_BIT_MASK, + WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); + if (err) + goto err_reconfig; + + /* Initiate reconfiguration */ + writel(WZRD_DR_BEGIN_DYNA_RECONF, + divider->base + WZRD_DR_INIT_REG_OFFSET); + + /* Check status register */ + err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, + value, value & WZRD_DR_LOCK_BIT_MASK, + WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); +err_reconfig: + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + return err; +} + +static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u8 div; + + /* + * since we don't change parent rate we just round rate to closest + * achievable + */ + div = DIV_ROUND_CLOSEST(*prate, rate); + + return (*prate / div); +} + +static const struct clk_ops clk_wzrd_clk_divider_ops = { + .round_rate = clk_wzrd_round_rate, + .set_rate = clk_wzrd_dynamic_reconfig, + .recalc_rate = clk_wzrd_recalc_rate, +}; + +static struct clk *clk_wzrd_register_divider(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *base, u16 offset, + u8 shift, u8 width, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_wzrd_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_wzrd_clk_divider_ops; + init.flags = flags; + init.parent_names = &parent_name; + init.num_parents = 1; + + div->base = base; + div->offset = offset; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + /* register the clock */ + hw = &div->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + hw = ERR_PTR(ret); + + return hw->clk; +} + static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, void *data) { @@ -223,7 +388,8 @@ static int clk_wzrd_probe(struct platform_device *pdev) clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor (&pdev->dev, clk_name, __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), - 0, 1, reg); + flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock); if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { dev_err(&pdev->dev, "unable to register divider clock\n"); ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); @@ -241,11 +407,14 @@ static int clk_wzrd_probe(struct platform_device *pdev) ret = -EINVAL; goto err_rm_int_clks; } - reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12); - reg &= WZRD_CLKOUT_DIVIDE_MASK; - reg >>= WZRD_CLKOUT_DIVIDE_SHIFT; - clk_wzrd->clkout[i] = clk_register_fixed_factor - (&pdev->dev, clkout_name, clk_name, 0, 1, reg); + clk_wzrd->clkout[i] = clk_wzrd_register_divider(&pdev->dev, + clkout_name, + clk_name, 0, + clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), + WZRD_CLKOUT_DIVIDE_SHIFT, + WZRD_CLKOUT_DIVIDE_WIDTH, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + NULL, &clkwzrd_lock); if (IS_ERR(clk_wzrd->clkout[i])) { int j; From patchwork Thu Feb 18 04:49:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shubhrajyoti Datta X-Patchwork-Id: 384533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B97C433DB for ; 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Wed, 17 Feb 2021 20:50:21 -0800 From: Shubhrajyoti Datta To: CC: , , , , , , "Shubhrajyoti Datta" Subject: [PATCH v9 7/7] clk: clock-wizard: Update the fixed factor divisors Date: Thu, 18 Feb 2021 10:19:51 +0530 Message-ID: <1613623791-4598-8-git-send-email-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9c2449e6-b176-41e2-33e0-08d8d3c8b9ca X-MS-TrafficTypeDiagnostic: SJ0PR02MB7343: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:989; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9TLe1umxsnuqFP3oIF0DpibFlvzCqf9WSTdSdvnrug4eW77aNTtlsaQLfJDzNl0l4Z/9T05dTNtQvEx15XgKe5tB44qfOxx0rAof3/K6/Eop9fo4o6+bxsTp5m5bNE9N/OP8g45QCVxujqoYOqOjDhKqPsxyk2rbelfn1KQO+O1IHm0AIkl+W2J5gov2BTV6tEjdNjBchN1KM+HrNW1asOmO40c5pUsUOXfpdtC9AcAz7b7vhZkbvQ5+1H35RfDQYxpRRwLMPc3TvodbnzTAqDaT4VPPEYHjGSIBor0XWxOmq58ME6wJ7EmoEVAlqIY5k9SKZ69nUKU5qRh00byPcJIZou5Oaym+NUP2jmfVS4i77z5IbQBGJQFvYc9nz82AvbYVcook0VX06cBc6G2aSyN8IZLrBoWoaKQqCCVOP4u+KVcPiQR0hVhHdN77ojOShupUbWnmYaRWlNVboCCaM3eti47GLbsurnn+AYw8xmOYS9OIJe0Cmpuh5B6pBhDkoVBF7I2Mk+HV46Ub0dgiYvvXsfWgJ8lUNAMvJACX82ZsLvorG1J6hIisG09viTeHtW/FkTp4RVETIAHfYZAWpV5RiJuX2ZiIpvmwAUWkIxYEIv/CPOeI2OdSt60Q/7WRhTQu6T6vfT9EdbGual32J66GZklIkNs35+uQuObiaY9jtj+qiQhj+ghf1ybB0huV X-Forefront-Antispam-Report: CIP:149.199.62.198; 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Signed-off-by: Shubhrajyoti Datta --- drivers/clk/clk-xlnx-clock-wizard.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index d403a74..7f09522 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -472,8 +472,10 @@ static int clk_wzrd_probe(struct platform_device *pdev) u32 reg, reg_f, mult; unsigned long rate; const char *clk_name; + void __iomem *ctrl_reg; struct clk_wzrd *clk_wzrd; int outputs; + unsigned long flags = 0; struct device_node *np = pdev->dev.of_node; clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); @@ -543,16 +545,17 @@ static int clk_wzrd_probe(struct platform_device *pdev) } outputs = of_property_count_strings(np, "clock-output-names"); - /* register div */ - reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & - WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT; + if (outputs == 1) + flags = CLK_SET_RATE_PARENT; clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); if (!clk_name) { ret = -ENOMEM; goto err_rm_int_clk; } - clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor + ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0); + /* register div */ + clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider (&pdev->dev, clk_name, __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | @@ -577,7 +580,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) if (!i) clk_wzrd->clkout[i] = clk_wzrd_register_divf (&pdev->dev, clkout_name, - clk_name, 0, + clk_name, flags, clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), WZRD_CLKOUT_DIVIDE_SHIFT, WZRD_CLKOUT_DIVIDE_WIDTH,