From patchwork Wed Mar 28 02:22:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 132505 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp198801ljb; Tue, 27 Mar 2018 19:24:36 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+96qYvbE1EEw724Tz3Go4Hi2kEwFBbVJJyO/tlW6dipoThm7avXv2sSleuROpg+nvlGzpO X-Received: by 10.55.33.144 with SMTP id f16mr2794764qki.158.1522203876668; Tue, 27 Mar 2018 19:24:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522203876; cv=none; d=google.com; s=arc-20160816; b=KLb9IgREircRbokBEk6bp+XXaO4FEWS2m1BKLRDHsOcmkOgd0bf9u7cE8hcWGR0wbi PSnmgqIuYq078/ADh4z1upr9nfbhVPYbXVmT0DYyvXygVt64UXzwgg6Ii0r+XbGmC7cq 8qU7MFyzBGCUcZLmMYfR/sLeTclrQ4Ju00S62U24ngaPwnbCJ11VQQD1VWVA+B05+Grq 4J0J2XncJqFF92JRy+wFcVPS1ruzIeyTeX74256tk0BwCRzy1ulSkyPbXh+GnDOkaZNi jE2+YxP5SilrR9Mzhdyz5lHcNoeBCoR3HIv0FQEt5yZGEyvRZFZnvdRsSM+KPG3KmyrC qf0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aYOvnXxHtqwog0x7GNQJk6qyEkCYwa2jmMvekB1xTz8=; b=qnFnsuEd2ZnJW3QPmceQ9frYDzgAqgW765Ob1duZqtYOzkwz5EoNJlWlciTBB1T24/ 2/NpY8qGC0OUBOFmLEi7P455bUiQiatfdEmmaybq7B2HIq41z+sH6Kg3U1E8eZXBKkxq L3QsQ6Y+4QbsbsVsL3NewgadRrel+IHRwTGpjqsojuxR40n3cnYHunWzLLDr0JfA6dPv 9Oth1sFWILvqiMa0Y6DcA8bjp8g6Zk/3/aidzMc4tx34cDHt7Q+VlIWffoluTTr3YxWT M4v6I+Nt1sCuHgc1ylhwttsc+YYG4JqwzOsTwHO/45Sb/bayPrImOMvtLALn0uX4cVz8 7z+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZMzc1Cw6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g20si1216262qto.44.2018.03.27.19.24.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 27 Mar 2018 19:24:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZMzc1Cw6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f10lQ-0005pw-6p for patch@linaro.org; Tue, 27 Mar 2018 22:24:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f10ji-0004RE-BJ for qemu-devel@nongnu.org; Tue, 27 Mar 2018 22:22:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f10jh-0002ko-EP for qemu-devel@nongnu.org; Tue, 27 Mar 2018 22:22:50 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:43801) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f10jh-0002kb-89 for qemu-devel@nongnu.org; Tue, 27 Mar 2018 22:22:49 -0400 Received: by mail-pf0-x243.google.com with SMTP id j2so400430pff.10 for ; Tue, 27 Mar 2018 19:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aYOvnXxHtqwog0x7GNQJk6qyEkCYwa2jmMvekB1xTz8=; b=ZMzc1Cw6TACy6/kxkcmN5M4YmjXJqbempXjsIVVw8st2RdYdT+LnNCRa1OnzwtHI7j DFbI/A/ryBk2IGR3LB3C0ELEr7v7hKnOW1h/aVCpbyg1X4wfpFTRtxgK2QYNymtcSS8J ekUZTczL7gIzkuEw/5lJU1ClMN8nSvC66UblQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aYOvnXxHtqwog0x7GNQJk6qyEkCYwa2jmMvekB1xTz8=; b=BtNQ4VFv93FdfqaD3WXMpn1H0swiDlUjf97ihkRc0AgoysTQWw2Rd0WQfFzZozQoMf rwtHhlELrdD4vPDIZ4HmFUDEp30gBTDMMuDs/JUF+A0wwE5X5NtbIx5Olvdev/eSlJej BWEUaEqJsxIqGJfQGe2ySbnb0T/GXy3Jdw4lx1cghvg64xIpCgXz7dAnIQDxXOrG0d96 92ue65dgVhxrC1hJIHnqb2sHFMErxJ8BS+uYtPBSWcJwpsR81U8RMByKRZDAuyG0Bqy6 sU58c2H9Y31EbNoMFUQWmx4d2+1hl+ouJ8XSzXJfxnPP/4frhbj0frbvCchSg02nXqwD VWuQ== X-Gm-Message-State: AElRT7HlrHYfjRT3ptWRGhEcLcStNeALyAxbF9L2w1Xbh72H/fHy0sqd 3tt/N/HDSKA70oPIzhMISvvLs0WuzOU= X-Received: by 10.101.74.69 with SMTP id a5mr1241234pgu.32.1522203767804; Tue, 27 Mar 2018 19:22:47 -0700 (PDT) Received: from cloudburst.twiddle.net ([121.215.28.70]) by smtp.gmail.com with ESMTPSA id 67sm5717731pfp.122.2018.03.27.19.22.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Mar 2018 19:22:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Mar 2018 10:22:32 +0800 Message-Id: <20180328022233.13400-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180328022233.13400-1-richard.henderson@linaro.org> References: <20180328022233.13400-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 1/2] target/riscv: Split out mstatus_fs from tb_flags during translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, mjc@sifive.com, palmer@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will want to track changes to mstatus_fs through the TB. As there is nothing else in tb_flags at the moment, remove the variable from DisasContext. Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.14.3 Reviewed-by: Michael Clark diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 41e06ac0f9..d201dd3e90 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -269,8 +269,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, target_ulong cpu_riscv_get_fflags(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_FP_ENABLE MSTATUS_FS +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -278,7 +278,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; + *flags = TB_FLAGS_MSTATUS_FS; #else *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 808eab7f50..a30724aa90 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -43,7 +43,7 @@ typedef struct DisasContext { target_ulong pc; target_ulong next_pc; uint32_t opcode; - uint32_t flags; + uint32_t mstatus_fs; uint32_t mem_idx; int singlestep_enabled; int bstate; @@ -665,7 +665,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -695,7 +695,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -986,7 +986,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0 = NULL; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { goto do_illegal; } @@ -1862,8 +1862,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) ctx.tb = tb; ctx.bstate = BS_NONE; - ctx.flags = tb->flags; ctx.mem_idx = tb->flags & TB_FLAGS_MMU_MASK; + ctx.mstatus_fs = tb->flags & TB_FLAGS_MSTATUS_FS; ctx.frm = -1; /* unknown rounding mode */ num_insns = 0; From patchwork Wed Mar 28 02:22:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 132506 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp199652ljb; Tue, 27 Mar 2018 19:25:50 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/y+q3Uw/i9K7DBM9rY9n0hX1CMSCruNTKbeHYA86s8qlRhptEWojQ91yza72hPPXr+3IJ6 X-Received: by 10.55.52.7 with SMTP id b7mr2539970qka.332.1522203950320; Tue, 27 Mar 2018 19:25:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522203950; cv=none; d=google.com; s=arc-20160816; b=Bj6cDbiyEqjUN5dYHk0vm6KifzPokVfiYTyGVcM9JVPBZ0xxiHBagwRpoDahqgTZhc r9bVIH5HYyzTMIPjN4/lhZLpPcCunOZkXr33W0vTS97EhMUZM0Mjsp+cDnK098tBusef T0ody+3z/ZmAKRiWXW5wOn83FkohRksYztVqNXUMmO1T0blYnbGVlYIOkVgss03Bd1sN ReqW4tH2k/RxkgmlhbtuB0BwBWHmFBVAzbssBbayrVjm9M4aWIXVFi7aZ2kQJ5gYCxsf DvjbdTzl++0xiRZJwLAWT0dO68to67aT1jsrhK6qZZz+Cgv2d1H1KN+aD/4UsLAhPlFG QBSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=NVN+MnRFAzC9cwjCwkjcgdhIUMbKFmhULCTOgUBeiF0=; b=fNAC6+nTSNGxwmcq0E3Arma1vnUP2ru0edPPaoTPkN+WveRCHETyOYAfd0JDQbLIhS MTzzzEomajPN0UcDF8LC/lgKT8bMuxgrNCtWVsumqAj95ZBzfCTmtQWvyrdQW9vjz3hb AxNs0bTCzv+VJAPhJG/dGfG4oPgS1qTXrA52+4ANufUBBgVdIN81J5nGgL/+W09Xu529 2V74pq8vFLipIXNKQFxHNFz8DMy9VqbNrxLb2odhfudm096w3OVisRI1mcniZ5D67OXU I5JV8ttcKmSV/UfywIaGhantM4xmbM9uXE8Ey1+OOu8Zprj9UNUwtHo1YWhjmQTT8UEV Qd0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MvAof+SO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 2/2] target/riscv: Mark MSTATUS_FS dirty X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@groups.riscv.org, mjc@sifive.com, palmer@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Writes to the FP register file mark the register file as dirty. Signed-off-by: Richard Henderson --- target/riscv/op_helper.c | 25 +++++++++++++++++-------- target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 56 insertions(+), 9 deletions(-) -- 2.14.3 Reviewed-by: Michael Clark Tested-by: Michael Clark diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e34715df4e..74eeef0be8 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -72,11 +72,20 @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception) do_raise_exception_err(env, exception, 0); } -static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra) +static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra, bool write) { #ifndef CONFIG_USER_ONLY - if (!(env->mstatus & MSTATUS_FS)) { + switch (get_field(env->mstatus, MSTATUS_FS)) { + case 0: /* disabled */ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, ra); + g_assert_not_reached(); + case 1: /* initial */ + case 2: /* clean */ + if (write) { + /* Mark fp status as dirty. */ + env->mstatus = MSTATUS_FS; + } + break; } #endif } @@ -96,15 +105,15 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, switch (csrno) { case CSR_FFLAGS: - validate_mstatus_fs(env, GETPC()); + validate_mstatus_fs(env, GETPC(), true); cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT)); break; case CSR_FRM: - validate_mstatus_fs(env, GETPC()); + validate_mstatus_fs(env, GETPC(), true); env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT); break; case CSR_FCSR: - validate_mstatus_fs(env, GETPC()); + validate_mstatus_fs(env, GETPC(), true); env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT; cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT); break; @@ -379,13 +388,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) switch (csrno) { case CSR_FFLAGS: - validate_mstatus_fs(env, GETPC()); + validate_mstatus_fs(env, GETPC(), false); return cpu_riscv_get_fflags(env); case CSR_FRM: - validate_mstatus_fs(env, GETPC()); + validate_mstatus_fs(env, GETPC(), false); return env->frm; case CSR_FCSR: - validate_mstatus_fs(env, GETPC()); + validate_mstatus_fs(env, GETPC(), false); return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a30724aa90..08fc42a679 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -660,6 +660,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(dat); } +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_fs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_fs_dirty(DisasContext *ctx) +{ + TCGv tmp; + if (ctx->mstatus_fs == MSTATUS_FS) { + return; + } + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_fs = MSTATUS_FS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); +} +#else +static inline void mark_fs_dirty(DisasContext *ctx) { } +#endif + static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -688,6 +713,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, break; } tcg_temp_free(t0); + + mark_fs_dirty(ctx); } static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, @@ -985,6 +1012,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, int rs2, int rm) { TCGv t0 = NULL; + bool fp_output = true; if (ctx->mstatus_fs == 0) { goto do_illegal; @@ -1047,6 +1075,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_S: @@ -1076,6 +1105,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_S_W: @@ -1126,6 +1156,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FMV_S_X: @@ -1218,6 +1249,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_D: @@ -1247,6 +1279,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_D_W: @@ -1294,6 +1327,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, default: goto do_illegal; } + fp_output = false; break; case OPC_RISC_FMV_D_X: @@ -1310,7 +1344,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); } gen_exception_illegal(ctx); - break; + return; + } + + if (fp_output) { + mark_fs_dirty(ctx); } }