From patchwork Wed Feb 17 11:39:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 384576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8ACCC433E6 for ; Wed, 17 Feb 2021 11:43:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C28C364E45 for ; Wed, 17 Feb 2021 11:43:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231856AbhBQLnJ (ORCPT ); Wed, 17 Feb 2021 06:43:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232111AbhBQLkw (ORCPT ); Wed, 17 Feb 2021 06:40:52 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06455C061756; Wed, 17 Feb 2021 03:40:06 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id v1so17035137wrd.6; Wed, 17 Feb 2021 03:40:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Ub3gKGJwLJRaryXIKn0038/d6bzjLaWe3sRPb09LY0=; b=DT5YyN1MOvKp2WuAgEYIlR4ajbLPAmzH8CueHGYC6nk8Xn8oz+MgtOH9LJI/Ptgo+a iv0wBtsjV/NINYVMTY0I2UZ6KaFbgb/kkpWwg50vfmNUbG0VXUAxpIDqwmGsf7uTT9MU dzzxwcaYJ8qRByQsqALtL9jP1ZidNrraUtKtDWaGZrBF0nh5Yg/efaebvZX8FH+3KlS4 j1myj9gs82TAASf+YCECDYCpDjJhGsW9pu/TG9Uavm3dFEf1li6DNkjcGMiJPxYC/MEO fllzQFRsvy/3DjMnkvBgAaT876WxFRjk196510alcNpJV59Z690xDGW6id7tb72US0Oh FqFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Ub3gKGJwLJRaryXIKn0038/d6bzjLaWe3sRPb09LY0=; b=HhMutll4R9YiHaHWVV/4jKHAQjJahdOkL+O0lvIAgerNqKWnlyMnML1JFPPIu4Qk/J OIUmRRW0qlUQYVqXn7I02f73c0QsHPDDj0dvSME63tSxntbL6+FZKgXH69C0ONpzUTF4 6vFSHwBBFBY6KceGJQPU0yDUrp2dsRB1FYFzpZNBwpxQv8bV04t7vhOReT2x0EOoEDDc /MB5FuXrhbKghSdXAztywOpm9JkNsUZg6kmEBFbtUqyHfEtrmmIBiNE851Jg7T6TmGiU wTLGy1tOFaLlv6cV7WrcOAlDQ7EBCquDQrTZb9Vt1+TWAF888tGmUsZwhEykZqk0891k eGTw== X-Gm-Message-State: AOAM530wXBftYs4/Xs53q7m3zKpNvf1wRIUYSI3MAMJQlKa2sLHGiXUK L2+Bvojt+53KZFf8ubjBOkI= X-Google-Smtp-Source: ABdhPJzduoPzl6qqnC0sKdwQMRl++JTO9gIqK1bXITzDft6XpAaJ5pRosTgHGQ+BZ2EeLgp5iZol+A== X-Received: by 2002:adf:edc8:: with SMTP id v8mr28901840wro.330.1613562004775; Wed, 17 Feb 2021 03:40:04 -0800 (PST) Received: from localhost.localdomain (67.red-83-54-30.dynamicip.rima-tde.net. [83.54.30.67]) by smtp.gmail.com with ESMTPSA id q140sm3600813wme.0.2021.02.17.03.40.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2021 03:40:04 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, neil@brown.name, Rob Herring Subject: [PATCH v7 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Date: Wed, 17 Feb 2021 12:39:55 +0100 Message-Id: <20210217114000.19571-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217114000.19571-1-sergio.paracuellos@gmail.com> References: <20210217114000.19571-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index 000000000000..1422badcf9de --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Sergio Paracuellos + */ + +#ifndef _DT_BINDINGS_CLK_MT7621_H +#define _DT_BINDINGS_CLK_MT7621_H + +#define MT7621_CLK_XTAL 0 +#define MT7621_CLK_CPU 1 +#define MT7621_CLK_BUS 2 +#define MT7621_CLK_50M 3 +#define MT7621_CLK_125M 4 +#define MT7621_CLK_150M 5 +#define MT7621_CLK_250M 6 +#define MT7621_CLK_270M 7 + +#define MT7621_CLK_HSDMA 8 +#define MT7621_CLK_FE 9 +#define MT7621_CLK_SP_DIVTX 10 +#define MT7621_CLK_TIMER 11 +#define MT7621_CLK_PCM 12 +#define MT7621_CLK_PIO 13 +#define MT7621_CLK_GDMA 14 +#define MT7621_CLK_NAND 15 +#define MT7621_CLK_I2C 16 +#define MT7621_CLK_I2S 17 +#define MT7621_CLK_SPI 18 +#define MT7621_CLK_UART1 19 +#define MT7621_CLK_UART2 20 +#define MT7621_CLK_UART3 21 +#define MT7621_CLK_ETH 22 +#define MT7621_CLK_PCIE0 23 +#define MT7621_CLK_PCIE1 24 +#define MT7621_CLK_PCIE2 25 +#define MT7621_CLK_CRYPTO 26 +#define MT7621_CLK_SHXC 27 + +#define MT7621_CLK_MAX 28 + +#endif /* _DT_BINDINGS_CLK_MT7621_H */ From patchwork Wed Feb 17 11:39:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 384575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A27FC433E0 for ; Wed, 17 Feb 2021 11:43:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3106564E33 for ; Wed, 17 Feb 2021 11:43:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231419AbhBQLnO (ORCPT ); Wed, 17 Feb 2021 06:43:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231969AbhBQLkw (ORCPT ); Wed, 17 Feb 2021 06:40:52 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09658C0613D6; Wed, 17 Feb 2021 03:40:07 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id t15so16976271wrx.13; Wed, 17 Feb 2021 03:40:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P2+9ZW2sRGm5fV3POd9uic+HKJNg6UuQ8+N4DBVvEOI=; b=Z4nUm3t3RKH1M16liPd8pxxnbr9w+hzq8lFpbtGdBH9BwqTH7blN+xQvoZlbePzgmi ewEZBWuw0PHDTWJtCjmLG8/JmSBRdUDSuxgrjIo5/GWjXKq4ySFO/Mg4rpdjV2P9DE4A sjcD3jpxrlBrzAv2OxsTYn+wrg6bU4SxcXbExtkrFi1sJ4QL+XHGsLk3+JyjJIjarj3a JZiWsK5O8lq1iro+XKcs3CWfa/7ZWX4kgCp5YA2v9u69UxTVSJ8JFs+Rg9oJYlPQjWX6 OaQbioKYd5Vsw18TTXmgCwuBvYlWVA43hGBYftpxU3H/+xH0XiJNVJu1JO78itlOQ9Kz C5pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P2+9ZW2sRGm5fV3POd9uic+HKJNg6UuQ8+N4DBVvEOI=; b=nvSS5A7spzSXOsfgwGxmUCPDP9l1YN2F/O/WGLvP+RXmy3OX9jj6id4MSYQ/rjB21f l/TvmO+Ol7SO+9iU1HSGQKe2f3ctGTQeS6jihDy4Lo75MVrAHqMt4P24o6NVSIRMajDy 8FcxQtGYQF//tneNXGwyDEhmxySYkF4i0L4VTpy6tyoKljM6MBmUBPbu7Y4erN0EdeUR JExVTOBg/4C3fsxNrcuqu9w7W6jMXGH3x5Fq3d2t9/PWLspWYDwftxrOu5qkEmsV754v /dH56AbXujHjKTXHv2Deu+6M+0FKrX1KJtnk/vzeCvWbHjmSEhWR5nfYwsomlhFSrZP7 tFJw== X-Gm-Message-State: AOAM530sF633whVlKj1dstG8pB560l/Mdoshenf1v8holFO+jgv16M4s /T9JrYlWpO9NpPwpjiw1ZBc= X-Google-Smtp-Source: ABdhPJwguJLYBfn5zzQLtUWS1q02A4AdbZTRw5rmi4BN0o6C5hA/QYnlKo+zo+ZN5X4KHAxfax+Zaw== X-Received: by 2002:a5d:6602:: with SMTP id n2mr28359513wru.150.1613562005813; Wed, 17 Feb 2021 03:40:05 -0800 (PST) Received: from localhost.localdomain (67.red-83-54-30.dynamicip.rima-tde.net. [83.54.30.67]) by smtp.gmail.com with ESMTPSA id q140sm3600813wme.0.2021.02.17.03.40.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2021 03:40:05 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, neil@brown.name Subject: [PATCH v7 2/6] dt: bindings: add mt7621-clk device tree binding documentation Date: Wed, 17 Feb 2021 12:39:56 +0100 Message-Id: <20210217114000.19571-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217114000.19571-1-sergio.paracuellos@gmail.com> References: <20210217114000.19571-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml new file mode 100644 index 000000000000..842a0f2c9d40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: . + +properties: + compatible: + const: mediatek,mt7621-clk + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + ralink,sysctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control system registers + + ralink,memctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control memory registers + + clock-output-names: + maxItems: 8 + +required: + - compatible + - '#clock-cells' + - ralink,sysctl + - ralink,memctl + +additionalProperties: false + +examples: + - | + #include + + pll { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; From patchwork Wed Feb 17 11:39:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 384032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06F99C433E0 for ; Wed, 17 Feb 2021 11:43:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C839B64E24 for ; Wed, 17 Feb 2021 11:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232198AbhBQLnR (ORCPT ); Wed, 17 Feb 2021 06:43:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232214AbhBQLkw (ORCPT ); Wed, 17 Feb 2021 06:40:52 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31E30C061786; Wed, 17 Feb 2021 03:40:08 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id n4so14057279wrx.1; Wed, 17 Feb 2021 03:40:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D7ONLAu08Mv3X6XwfE0xnfnap6TUVRns7veDeVdvOZU=; b=k+VCuy6wc6oKwtGsRMV8K1QqiAHW1LxlYAJQR46E3B4lboc2HSU8EEFvaR0Vjp0Y5v ywsYqHDztGS4cc0dR4k3+C5veHfqDQdJq/DK+V74p89P2hfhMxOMBE1RWx4rI0edIzLh miW27pTrmFSJqtk9hey4gDgqvMkFHVwObufLvurIXwDiRUhP+yDXcSmbeN8DVI3KP8b7 YrU8ZSW5wncMbOQxrvMesvYnVQ+Ke+JhYAeU8lfjL51oKpfkSNDwnV/6u0zNSNZ7PK5U H6NAxthoX+70rqkg70pubIm57EmIPVYMmaaPeaLLPAuAmU3xxH+/A43K4Hmq3ROD8Raj +d6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7ONLAu08Mv3X6XwfE0xnfnap6TUVRns7veDeVdvOZU=; b=LtMsFeStnBgKvzRg8XNL2uFGfNoib1/3kQPgYmGlIsi4xhHGDkfK2U0QhKFFhTqvio QTSNqvBcWc5WnTQy8ISsWYbRuU3lOOI6JFVy6dpcjPJgbI3lb6LA7d6OID6Ar/dBTJg0 ubY0kYf47t+1yZRcR4J4TX3ko2y/o51LtCxr4mksZnzCuqdshQWZmIwEX701Xqcbn6Rh T+AmX0HbsLFoor4fR3oz5APrM4Gyb9Rj8LMqEnxtZ/y+sn3PvZ6rG472i71axtsuFW1P X/MIeFNt6riwpH7Zmq2HFtneAtzGd1MH3ixgRkX81xBg1XEdYOLxzDXtjbU6qcySsMf4 XOLA== X-Gm-Message-State: AOAM533waDg8YgU1yG+aLPIjnh0/LaPpxvL7HUi+WdIOiFqdW2rNoGfx GjNKEiDSojy47p7FXBT4nF4= X-Google-Smtp-Source: ABdhPJyfdKQpec+0mh/SI8uM/aK3kI/GmxLx4p6Ff/fucCDjJK2pw6DC7mi4wJy2O7HWpykvTBcQJg== X-Received: by 2002:adf:9031:: with SMTP id h46mr29031565wrh.19.1613562006885; Wed, 17 Feb 2021 03:40:06 -0800 (PST) Received: from localhost.localdomain (67.red-83-54-30.dynamicip.rima-tde.net. [83.54.30.67]) by smtp.gmail.com with ESMTPSA id q140sm3600813wme.0.2021.02.17.03.40.05 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2021 03:40:06 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, neil@brown.name Subject: [PATCH v7 3/6] clk: ralink: add clock driver for mt7621 SoC Date: Wed, 17 Feb 2021 12:39:57 +0100 Message-Id: <20210217114000.19571-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217114000.19571-1-sergio.paracuellos@gmail.com> References: <20210217114000.19571-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. Looking into driver code, and some openWRT patched there are another frequencies which are used in some drivers (uart, sd...). According to all of this information the clock plan for this SoC is set as follows: - Main top clock "xtal" from where all the rest of the world is derived. - CPU clock "cpu" derived from "xtal" frequencies and a bunch of register reads and predividers. - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz. - Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz. We also have a buch of gate clocks with their parents: * "hsdma": "150m" * "fe": "250m" * "sp_divtx": "270m" * "timer": "50m" * "pcm": "270m" * "pio": "50m" * "gdma": "bus" * "nand": "125m" * "i2c": "50m" * "i2s": "270m" * "spi": "bus" * "uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m" * "shxc": "50m" With this information the clk driver will provide clock and gates functionality from a a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Signed-off-by: Sergio Paracuellos Reported-by: kernel test robot --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ralink/Kconfig | 14 + drivers/clk/ralink/Makefile | 2 + drivers/clk/ralink/clk-mt7621.c | 532 ++++++++++++++++++++++++++++++++ 5 files changed, 550 insertions(+) create mode 100644 drivers/clk/ralink/Kconfig create mode 100644 drivers/clk/ralink/Makefile create mode 100644 drivers/clk/ralink/clk-mt7621.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 7c5dc348c16f..70b23da997bf 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" +source "drivers/clk/ralink/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5325847469e9..1b35ad852721 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ +obj-y += ralink/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig new file mode 100644 index 000000000000..9f39c282fdc5 --- /dev/null +++ b/drivers/clk/ralink/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# MediaTek Mt7621 Clock Driver +# +menu "Clock driver for Mediatek mt7621 SoC" + depends on SOC_MT7621 || COMPILE_TEST + +config CLK_MT7621 + bool "Clock driver for MediaTek MT7621" + depends on SOC_MT7621 || COMPILE_TEST + default SOC_MT7621 + help + This driver supports MediaTek MT7621 basic clocks. +endmenu diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile new file mode 100644 index 000000000000..cf6f9216379d --- /dev/null +++ b/drivers/clk/ralink/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c new file mode 100644 index 000000000000..55b415e74cd1 --- /dev/null +++ b/drivers/clk/ralink/clk-mt7621.c @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek MT7621 Clock Driver + * Author: Sergio Paracuellos + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Configuration registers */ +#define SYSC_REG_SYSTEM_CONFIG0 0x10 +#define SYSC_REG_SYSTEM_CONFIG1 0x14 +#define SYSC_REG_CLKCFG0 0x2c +#define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_CUR_CLK_STS 0x44 + +#define MEMC_REG_CPU_PLL 0x648 +#define XTAL_MODE_SEL_MASK 0x7 +#define XTAL_MODE_SEL_SHIFT 6 + +#define CPU_CLK_SEL_MASK 0x3 +#define CPU_CLK_SEL_SHIFT 30 + +#define CUR_CPU_FDIV_MASK 0x1f +#define CUR_CPU_FDIV_SHIFT 8 +#define CUR_CPU_FFRAC_MASK 0x1f +#define CUR_CPU_FFRAC_SHIFT 0 + +#define CPU_PLL_PREDIV_MASK 0x3 +#define CPU_PLL_PREDIV_SHIFT 12 +#define CPU_PLL_FBDIV_MASK 0x7f +#define CPU_PLL_FBDIV_SHIFT 4 + +struct mt7621_clk_priv { + struct regmap *sysc; + struct regmap *memc; +}; + +struct mt7621_clk { + struct clk_hw hw; + struct mt7621_clk_priv *priv; +}; + +struct mt7621_fixed_clk { + u8 idx; + const char *name; + const char *parent_name; + unsigned long rate; + struct clk_hw *hw; +}; + +struct mt7621_gate { + u8 idx; + const char *name; + const char *parent_name; + struct mt7621_clk_priv *priv; + u32 bit_idx; + struct clk_hw hw; +}; + +#define GATE(_id, _name, _pname, _shift) \ + { \ + .idx = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .bit_idx = _shift \ + } + +static struct mt7621_gate mt7621_gates[] = { + GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)), + GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)), + GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)), + GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)), + GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)), + GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)), + GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)), + GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)), + GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)), + GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)), + GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)), + GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)), + GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)), + GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)), + GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)), + GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)), + GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)), + GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)), + GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)), + GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30)) +}; + +static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw) +{ + return container_of(hw, struct mt7621_gate, hw); +} + +static int mt7621_gate_enable(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *sysc = clk_gate->priv->sysc; + + return regmap_update_bits(sysc, SYSC_REG_CLKCFG1, + clk_gate->bit_idx, clk_gate->bit_idx); +} + +static void mt7621_gate_disable(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *sysc = clk_gate->priv->sysc; + + regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); +} + +static int mt7621_gate_is_enabled(struct clk_hw *hw) +{ + struct mt7621_gate *clk_gate = to_mt7621_gate(hw); + struct regmap *sysc = clk_gate->priv->sysc; + u32 val; + + if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val)) + return 0; + + return val & BIT(clk_gate->bit_idx); +} + +static const struct clk_ops mt7621_gate_ops = { + .enable = mt7621_gate_enable, + .disable = mt7621_gate_disable, + .is_enabled = mt7621_gate_is_enabled, +}; + +static int mt7621_gate_ops_init(struct device *dev, + struct mt7621_gate *sclk) +{ + struct clk_init_data init = { + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .parent_names = &sclk->parent_name, + .ops = &mt7621_gate_ops, + .name = sclk->name, + }; + + sclk->hw.init = &init; + return devm_clk_hw_register(dev, &sclk->hw); +} + +static int mt7621_register_gates(struct device *dev, + struct clk_hw_onecell_data *clk_data, + struct mt7621_clk_priv *priv) +{ + struct clk_hw **hws = clk_data->hws; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) { + struct mt7621_gate *sclk = &mt7621_gates[i]; + + sclk->priv = priv; + ret = mt7621_gate_ops_init(dev, sclk); + if (ret) { + dev_err(dev, "Couldn't register clock %s\n", sclk->name); + goto err_clk_unreg; + } + + hws[sclk->idx] = &sclk->hw; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + struct mt7621_gate *sclk = &mt7621_gates[i]; + + clk_hw_unregister(&sclk->hw); + } + return ret; +} + +#define FIXED(_id, _name, _rate) \ + { \ + .idx = _id, \ + .name = _name, \ + .parent_name = "xtal", \ + .rate = _rate \ + } + +static struct mt7621_fixed_clk mt7621_fixed_clks[] = { + FIXED(MT7621_CLK_50M, "50m", 50000000), + FIXED(MT7621_CLK_125M, "125m", 125000000), + FIXED(MT7621_CLK_150M, "150m", 150000000), + FIXED(MT7621_CLK_250M, "250m", 250000000), + FIXED(MT7621_CLK_270M, "270m", 270000000), +}; + +static int mt7621_register_fixed_clocks(struct device *dev, + struct clk_hw_onecell_data *clk_data) +{ + struct clk_hw **hws = clk_data->hws; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) { + struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; + + sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name, + sclk->parent_name, 0, + sclk->rate); + if (IS_ERR(sclk->hw)) { + dev_err(dev, "Couldn't register clock %s\n", sclk->name); + ret = PTR_ERR(sclk->hw); + goto err_clk_unreg; + } + + hws[sclk->idx] = sclk->hw; + } + + return 0; + +err_clk_unreg: + while (--i >= 0) { + struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; + + clk_hw_unregister_fixed_rate(sclk->hw); + } + return ret; +} + +static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw) +{ + return container_of(hw, struct mt7621_clk, hw); +} + +static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mt7621_clk *clk = to_mt7621_clk(hw); + struct regmap *sysc = clk->priv->sysc; + u32 val; + + regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val); + val = (val >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; + + if (val <= 2) + return 20000000; + if (val <= 5) + return 40000000; + + return 25000000; +} + +static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw, + unsigned long xtal_clk) +{ + static const u32 prediv_tbl[] = { 0, 1, 2, 2 }; + struct mt7621_clk *clk = to_mt7621_clk(hw); + struct regmap *sysc = clk->priv->sysc; + struct regmap *memc = clk->priv->memc; + u32 clkcfg, clk_sel, curclk, ffiv, ffrac; + u32 pll, prediv, fbdiv; + unsigned long cpu_clk; + + regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg); + clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; + + regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk); + ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; + ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; + + switch (clk_sel) { + case 0: + cpu_clk = 500000000; + break; + case 1: + regmap_read(memc, MEMC_REG_CPU_PLL, &pll); + fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; + prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; + cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; + break; + default: + cpu_clk = xtal_clk; + } + + return cpu_clk / ffiv * ffrac; +} + +static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 4; +} + +#define CLK_BASE(_name, _parent, _recalc) { \ + .init = &(struct clk_init_data) { \ + .name = _name, \ + .ops = &(const struct clk_ops) { \ + .recalc_rate = _recalc, \ + }, \ + .parent_data = &(const struct clk_parent_data) { \ + .name = _parent, \ + .fw_name = _parent \ + }, \ + .num_parents = _parent ? 1 : 0 \ + }, \ +} + +static struct mt7621_clk mt7621_clks_base[] = { + { CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) }, + { CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) }, + { CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) }, +}; + +static struct clk_hw *mt7621_clk_early[MT7621_CLK_MAX]; + +static int mt7621_register_early_clocks(struct device_node *np, + struct clk_hw_onecell_data *clk_data, + struct mt7621_clk_priv *priv) +{ + struct clk_hw **hws = clk_data->hws; + int ret, i, j; + + for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { + struct mt7621_clk *sclk = &mt7621_clks_base[i]; + + sclk->priv = priv; + ret = of_clk_hw_register(np, &sclk->hw); + if (ret) { + pr_err("Couldn't register top clock %i\n", i); + goto err_clk_unreg; + } + + hws[i] = &sclk->hw; + mt7621_clk_early[i] = &sclk->hw; + } + + for (j = i; j < MT7621_CLK_MAX; j++) + mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER); + + return 0; + +err_clk_unreg: + while (--i >= 0) { + struct mt7621_clk *sclk = &mt7621_clks_base[i]; + + clk_hw_unregister(&sclk->hw); + } + return ret; +} + +static int mt7621_prepare_enable_clocks(struct clk_hw_onecell_data *clk_data) +{ + int ret, i; + + for (i = 0; i < MT7621_CLK_MAX; i++) { + ret = clk_prepare_enable(clk_data->hws[i]->clk); + if (ret) { + pr_err("failed to enable clk: %d\n", ret); + goto err_clk_disable; + } + } + + return 0; + +err_clk_disable: + while (--i >= 0) + clk_disable_unprepare(clk_data->hws[i]->clk); + return ret; +} + +static void __init mt7621_clk_init(struct device_node *node) +{ + struct mt7621_clk_priv *priv; + struct clk_hw_onecell_data *clk_data; + int ret, i, count; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return; + + priv->sysc = syscon_regmap_lookup_by_phandle(node, "ralink,sysctl"); + if (IS_ERR(priv->sysc)) { + pr_err("Could not get sysc syscon regmap\n"); + goto free_clk_priv; + } + + priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl"); + if (IS_ERR(priv->memc)) { + pr_err("Could not get memc syscon regmap\n"); + goto free_clk_priv; + } + + count = ARRAY_SIZE(mt7621_clks_base) + + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); + clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); + if (!clk_data) + goto free_clk_priv; + + ret = mt7621_register_early_clocks(node, clk_data, priv); + if (ret) { + pr_err("Couldn't register top clocks\n"); + goto free_clk_data; + } + + clk_data->num = count; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) { + pr_err("Couldn't add clk hw provider\n"); + goto unreg_clk_top; + } + + return; + +unreg_clk_top: + for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) { + struct mt7621_clk *sclk = &mt7621_clks_base[i]; + + clk_hw_unregister(&sclk->hw); + } + +free_clk_data: + kfree(clk_data); + +free_clk_priv: + kfree(priv); +} +CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-clk", mt7621_clk_init); + +static int mt7621_clk_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + struct device *dev = &pdev->dev; + struct mt7621_clk_priv *priv; + int ret, i, count; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->sysc = syscon_regmap_lookup_by_phandle(np, "ralink,sysctl"); + if (IS_ERR(priv->sysc)) { + dev_err(dev, "Could not get sysc syscon regmap\n"); + goto free_clk_priv; + } + + priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl"); + if (IS_ERR(priv->memc)) { + dev_err(dev, "Could not get memc syscon regmap\n"); + goto free_clk_priv; + } + + count = ARRAY_SIZE(mt7621_clks_base) + + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); + clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); + if (!clk_data) + goto free_clk_priv; + + for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) + clk_data->hws[i] = mt7621_clk_early[i]; + + ret = mt7621_register_fixed_clocks(dev, clk_data); + if (ret) { + dev_err(dev, "Couldn't register fixed clocks\n"); + goto free_clk_data; + } + + ret = mt7621_register_gates(dev, clk_data, priv); + if (ret) { + dev_err(dev, "Couldn't register fixed clock gates\n"); + goto unreg_clk_fixed; + } + + clk_data->num = count; + + ret = mt7621_prepare_enable_clocks(clk_data); + if (ret) { + dev_err(dev, "Couldn't register fixed clock gates\n"); + goto unreg_clk_gates; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) { + dev_err(dev, "Couldn't add clk hw provider\n"); + goto disable_clks; + } + + return 0; + +disable_clks: + for (i = 0; i < MT7621_CLK_MAX; i++) + clk_disable_unprepare(clk_data->hws[i]->clk); + +unreg_clk_gates: + for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) { + struct mt7621_gate *sclk = &mt7621_gates[i]; + + clk_hw_unregister(&sclk->hw); + } + +unreg_clk_fixed: + for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) { + struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; + + clk_hw_unregister_fixed_rate(sclk->hw); + } + +free_clk_data: + kfree(clk_data); + +free_clk_priv: + kfree(priv); + + return ret; +} + +static const struct of_device_id mt7621_clk_of_match[] = { + { .compatible = "mediatek,mt7621-clk" }, + {}, +}; + +static struct platform_driver mt7621_clk_driver = { + .probe = mt7621_clk_probe, + .driver = { + .name = "mt7621-clk", + .of_match_table = mt7621_clk_of_match, + }, +}; +builtin_platform_driver(mt7621_clk_driver); From patchwork Wed Feb 17 11:39:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 384573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CABA9C433DB for ; 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[83.54.30.67]) by smtp.gmail.com with ESMTPSA id q140sm3600813wme.0.2021.02.17.03.40.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2021 03:40:07 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, neil@brown.name Subject: [PATCH v7 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Date: Wed, 17 Feb 2021 12:39:58 +0100 Message-Id: <20210217114000.19571-5-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217114000.19571-1-sergio.paracuellos@gmail.com> References: <20210217114000.19571-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/gbpc1.dts | 11 ---- drivers/staging/mt7621-dts/mt7621.dtsi | 79 +++++++++++++------------- 2 files changed, 38 insertions(+), 52 deletions(-) diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts index a7c0d3115d72..7716d0efe524 100644 --- a/drivers/staging/mt7621-dts/gbpc1.dts +++ b/drivers/staging/mt7621-dts/gbpc1.dts @@ -100,17 +100,6 @@ partition@50000 { }; }; -&sysclock { - compatible = "fixed-clock"; - /* This is normally 1/4 of cpuclock */ - clock-frequency = <225000000>; -}; - -&cpuclock { - compatible = "fixed-clock"; - clock-frequency = <900000000>; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 16fc94f65486..11d1670d4339 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -1,5 +1,6 @@ #include #include +#include / { #address-cells = <1>; @@ -27,27 +28,6 @@ aliases { serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* This is normally 1/4 of cpuclock */ - clock-frequency = <220000000>; - }; - - mmc_clock: mmc_clock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; mmc_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; @@ -76,10 +56,20 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; + compatible = "mtk,mt7621-sysc", "syscon"; reg = <0x0 0x100>; }; + pll: pll { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; + wdt: wdt@100 { compatible = "mtk,mt7621-wdt"; reg = <0x100 0x100>; @@ -101,8 +91,8 @@ i2c: i2c@900 { compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysclock>; - + clocks = <&pll MT7621_CLK_I2C>; + clock-names = "i2c"; resets = <&rstctrl 16>; reset-names = "i2c"; @@ -119,8 +109,8 @@ i2s: i2s@a00 { compatible = "mediatek,mt7621-i2s"; reg = <0xa00 0x100>; - clocks = <&sysclock>; - + clocks = <&pll MT7621_CLK_I2S>; + clock-names = "i2s"; resets = <&rstctrl 17>; reset-names = "i2s"; @@ -138,7 +128,7 @@ i2s: i2s@a00 { }; memc: memc@5000 { - compatible = "mtk,mt7621-memc"; + compatible = "mtk,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; }; @@ -156,8 +146,8 @@ uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; - clock-frequency = <50000000>; + clocks = <&pll MT7621_CLK_UART1>; + clock-names = "uart1"; interrupt-parent = <&gic>; interrupts = ; @@ -173,7 +163,8 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_SPI>; + clock-names = "spi"; resets = <&rstctrl 18>; reset-names = "spi"; @@ -189,6 +180,8 @@ gdma: gdma@2800 { compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; + clocks = <&pll MT7621_CLK_GDMA>; + clock-names = "gdma"; resets = <&rstctrl 14>; reset-names = "dma"; @@ -206,6 +199,8 @@ hsdma: hsdma@7000 { compatible = "mediatek,mt7621-hsdma"; reg = <0x7000 0x1000>; + clocks = <&pll MT7621_CLK_HSDMA>; + clock-names = "hsdma"; resets = <&rstctrl 5>; reset-names = "hsdma"; @@ -311,11 +306,6 @@ rstctrl: rstctrl { #reset-cells = <1>; }; - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - sdhci: sdhci@1E130000 { status = "disabled"; @@ -334,7 +324,8 @@ sdhci: sdhci@1E130000 { pinctrl-0 = <&sdhci_pins>; pinctrl-1 = <&sdhci_pins>; - clocks = <&mmc_clock &mmc_clock>; + clocks = <&pll MT7621_CLK_SHXC>, + <&pll MT7621_CLK_50M>; clock-names = "source", "hclk"; interrupt-parent = <&gic>; @@ -349,7 +340,7 @@ xhci: xhci@1E1C0000 { 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_XTAL>; clock-names = "sys_ck"; interrupt-parent = <&gic>; @@ -368,7 +359,7 @@ gic: interrupt-controller@1fbc0000 { timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; @@ -381,6 +372,9 @@ nand: nand@1e003000 { 0x1e003800 0x800>; #address-cells = <1>; #size-cells = <1>; + + clocks = <&pll MT7621_CLK_NAND>; + clock-names = "nand"; }; ethsys: syscon@1e000000 { @@ -394,8 +388,9 @@ ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysclock>; - clock-names = "ethif"; + clocks = <&pll MT7621_CLK_FE>, + <&pll MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; #address-cells = <1>; #size-cells = <0>; @@ -521,7 +516,9 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clocks = <&pll MT7621_CLK_PCIE0>, + <&pll MT7621_CLK_PCIE1>, + <&pll MT7621_CLK_PCIE2>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2"; From patchwork Wed Feb 17 11:39:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 384574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D48D3C433DB for ; Wed, 17 Feb 2021 11:43:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0A6964E24 for ; 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[83.54.30.67]) by smtp.gmail.com with ESMTPSA id q140sm3600813wme.0.2021.02.17.03.40.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2021 03:40:08 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, neil@brown.name Subject: [PATCH v7 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Date: Wed, 17 Feb 2021 12:39:59 +0100 Message-Id: <20210217114000.19571-6-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217114000.19571-1-sergio.paracuellos@gmail.com> References: <20210217114000.19571-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 6 +++--- drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index ca0ac607b0f3..5d74fc1c96ac 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void) void __init ralink_of_remap(void) { - rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); - rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); + rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); + rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); if (!rt_sysc_membase || !rt_memc_membase) panic("Failed to remap core resources"); @@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) { name = "MT7621"; - soc_info->compatible = "mtk,mt7621-soc"; + soc_info->compatible = "mediatek,mt7621-soc"; } else { panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1); } diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 11d1670d4339..55784dd48dc5 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -56,7 +56,7 @@ palmbus: palmbus@1E000000 { #size-cells = <1>; sysc: sysc@0 { - compatible = "mtk,mt7621-sysc", "syscon"; + compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; }; @@ -71,7 +71,7 @@ pll: pll { }; wdt: wdt@100 { - compatible = "mtk,mt7621-wdt"; + compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; }; @@ -128,17 +128,17 @@ i2s: i2s@a00 { }; memc: memc@5000 { - compatible = "mtk,mt7621-memc", "syscon"; + compatible = "mediatek,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; }; cpc: cpc@1fbf0000 { - compatible = "mtk,mt7621-cpc"; + compatible = "mediatek,mt7621-cpc"; reg = <0x1fbf0000 0x8000>; }; mc: mc@1fbf8000 { - compatible = "mtk,mt7621-mc"; + compatible = "mediatek,mt7621-mc"; reg = <0x1fbf8000 0x8000>; }; @@ -366,7 +366,7 @@ timer { nand: nand@1e003000 { status = "disabled"; - compatible = "mtk,mt7621-nand"; + compatible = "mediatek,mt7621-nand"; bank-width = <2>; reg = <0x1e003000 0x800 0x1e003800 0x800>; From patchwork Wed Feb 17 11:40:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 384031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B13A5C4332B for ; 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[83.54.30.67]) by smtp.gmail.com with ESMTPSA id q140sm3600813wme.0.2021.02.17.03.40.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2021 03:40:09 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, neil@brown.name Subject: [PATCH v7 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Date: Wed, 17 Feb 2021 12:40:00 +0100 Message-Id: <20210217114000.19571-7-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217114000.19571-1-sergio.paracuellos@gmail.com> References: <20210217114000.19571-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L: linux-wireless@vger.kernel.org S: Maintained F: drivers/net/wireless/mediatek/mt7601u/ +MEDIATEK MT7621 CLOCK DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml +F: drivers/clk/ralink/clk-mt7621.c + MEDIATEK MT7621/28/88 I2C DRIVER M: Stefan Roese L: linux-i2c@vger.kernel.org