From patchwork Tue Mar 27 13:11:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 132479 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp5063913ljb; Tue, 27 Mar 2018 06:11:24 -0700 (PDT) X-Google-Smtp-Source: AIpwx49a2oUBgxVfAMAW4ZFWrJ96VGiTQLRGGOslbcRqe0l5jqMZ2xXllQ7OGZ01AwzsrQcj9glL X-Received: by 10.101.97.178 with SMTP id i18mr9452626pgv.439.1522156284327; Tue, 27 Mar 2018 06:11:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522156284; cv=none; d=google.com; s=arc-20160816; b=UHiy1Ucjq40WBCZ8O/NPlFNG8AEbsM+jGUYiAzHxeT2lZNrIDmwxJkmj6/aVbr01At xKQRxnaO+4kJtnhpHYje5mbgWfqyebS28HqkXEK5HG4bJwZAwR9wqmgTZAUe6HIKasup SM6vTvRrJK1T9Z6QAdLMgUoFvz+aIPu6QliZDtj/iag2vQkwRBujAEGeXO+A5HIlIIGe NwhWdhgBL3SH90XeAm9cDYsuQJlW1mnAOQbcrY2es89kEFd9tJM8bssbVoqFI3UMtDUL raKrNKDpw3JQqxAOr0jegbA6GUTa4YZuGH/CUoLwT2VeiISIvpO9w9h6xY2gdnlsDyGT +4XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=5aVLc7eoUsE8M9LF0Sm34xpfzGxS1PUQziOZ2nTpFQc=; b=jpTw1/9qKlNRwFoX8TLYmhqAQjYSn5meCbfYP2Err9dzq71KE5Njj/PXYZbwTkfKF+ +jTpcf/578tDjcTGTxkRsplT3wg8Ke3HO6m/cRszsNkWkVVUHV1B4VxGVYJz1nprsh1l N5m9GkNQG3MpQWgXEP7XIz2WJZzQuGr4QvZ3ACD38z0X3x7mC1TdWXo2w0MlJZr31zdr U/cHjXiZChZIgb+AVgAjVs+AlUOJDihAMRER4q5tHJTcYtTA1wX9xC78PnfoJvuHD7ss 1CL8FyEgAuYLWl5UGjG+1F57cKpzGkr/VDQlp4k7wmXhtgIq5N9W3miQ/0RLo1XCuK5X i73g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z188si961731pfz.172.2018.03.27.06.11.24; Tue, 27 Mar 2018 06:11:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752620AbeC0NLV (ORCPT + 28 others); Tue, 27 Mar 2018 09:11:21 -0400 Received: from foss.arm.com ([217.140.101.70]:54806 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752060AbeC0NLS (ORCPT ); Tue, 27 Mar 2018 09:11:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 767921435; Tue, 27 Mar 2018 06:11:18 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 474E73F24A; Tue, 27 Mar 2018 06:11:18 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 0F3571AE53E7; Tue, 27 Mar 2018 14:11:29 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: okaya@codeaurora.org, Will Deacon , Benjamin Herrenschmidt , Arnd Bergmann , Jason Gunthorpe , "Paul E. McKenney" , Peter Zijlstra , Ingo Molnar , Jonathan Corbet Subject: [PATCH] docs/memory-barriers.txt: Fix broken DMA vs MMIO ordering example Date: Tue, 27 Mar 2018 14:11:27 +0100 Message-Id: <1522156287-15169-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The section of memory-barriers.txt that describes the dma_Xmb() barriers has an incorrect example claiming that a wmb() is required after writing to coherent memory in order for those writes to be visible to a device before a subsequent MMIO access using writel() can reach the device. In fact, this ordering guarantee is provided (at significant cost on some architectures such as arm and power) by writel, so the wmb() is not necessary. writel_relaxed exists for cases where this ordering is not required. Fix the example and update the text to make this clearer. Cc: Benjamin Herrenschmidt Cc: Arnd Bergmann Cc: Jason Gunthorpe Cc: "Paul E. McKenney" Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Jonathan Corbet Reported-by: Sinan Kaya Signed-off-by: Will Deacon --- Documentation/memory-barriers.txt | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.1.4 diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index a863009849a3..3247547d1c36 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1909,9 +1909,6 @@ There are some more advanced barrier functions: /* assign ownership */ desc->status = DEVICE_OWN; - /* force memory to sync before notifying device via MMIO */ - wmb(); - /* notify device of new descriptors */ writel(DESC_NOTIFY, doorbell); } @@ -1919,11 +1916,15 @@ There are some more advanced barrier functions: The dma_rmb() allows us guarantee the device has released ownership before we read the data from the descriptor, and the dma_wmb() allows us to guarantee the data is written to the descriptor before the device - can see it now has ownership. The wmb() is needed to guarantee that the - cache coherent memory writes have completed before attempting a write to - the cache incoherent MMIO region. - - See Documentation/DMA-API.txt for more information on consistent memory. + can see it now has ownership. Note that, when using writel(), a prior + wmb() is not needed to guarantee that the cache coherent memory writes + have completed before writing to the MMIO region. The cheaper + writel_relaxed() does not provide this guarantee and must not be used + here. + + See the subsection "Kernel I/O barrier effects" for more information on + relaxed I/O accessors and the Documentation/DMA-API.txt file for more + information on consistent memory. MMIO WRITE BARRIER