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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:20:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Date: Wed, 17 Feb 2021 12:19:26 -0800 Message-Id: <20210217202036.1724901-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the provided cpu_ldst.h interfaces. This fixes the build vs the unconverted uses of g2h(), adds missed memory trace events, and correctly recognizes when a SIGSEGV belongs to the guest via set_helper_retaddr(). Fixes: 3e8f1628e864 Signed-off-by: Richard Henderson --- tcg/tci.c | 73 +++++++++++++++++++++---------------------------------- 1 file changed, 28 insertions(+), 45 deletions(-) -- 2.25.1 Tested-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index fb3c97aaf1..1c667537fe 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -346,51 +346,34 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) return result; } -#ifdef CONFIG_SOFTMMU -# define qemu_ld_ub \ - helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leuw \ - helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leul \ - helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leq \ - helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beuw \ - helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beul \ - helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beq \ - helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_st_b(X) \ - helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lew(X) \ - helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lel(X) \ - helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_leq(X) \ - helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bew(X) \ - helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bel(X) \ - helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_beq(X) \ - helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -#else -# define qemu_ld_ub ldub_p(g2h(taddr)) -# define qemu_ld_leuw lduw_le_p(g2h(taddr)) -# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr)) -# define qemu_ld_leq ldq_le_p(g2h(taddr)) -# define qemu_ld_beuw lduw_be_p(g2h(taddr)) -# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr)) -# define qemu_ld_beq ldq_be_p(g2h(taddr)) -# define qemu_st_b(X) stb_p(g2h(taddr), X) -# define qemu_st_lew(X) stw_le_p(g2h(taddr), X) -# define qemu_st_lel(X) stl_le_p(g2h(taddr), X) -# define qemu_st_leq(X) stq_le_p(g2h(taddr), X) -# define qemu_st_bew(X) stw_be_p(g2h(taddr), X) -# define qemu_st_bel(X) stl_be_p(g2h(taddr), X) -# define qemu_st_beq(X) stq_be_p(g2h(taddr), X) -#endif +#define qemu_ld_ub \ + cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leuw \ + cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leul \ + cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leq \ + cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beuw \ + cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beul \ + cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beq \ + cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_b(X) \ + cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_lew(X) \ + cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_lel(X) \ + cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_leq(X) \ + cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_bew(X) \ + cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_bel(X) \ + cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_beq(X) \ + cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) #if TCG_TARGET_REG_BITS == 64 # define CASE_32_64(x) \ From patchwork Wed Feb 17 20:19:27 2021 Content-Type: text/plain; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:20:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Date: Wed, 17 Feb 2021 12:19:27 -0800 Message-Id: <20210217202036.1724901-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow other places in tcg to restart with a smaller tb. Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197b..bbe3dcee03 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -346,6 +346,12 @@ static void set_jmp_reset_offset(TCGContext *s, int which) s->tb_jmp_reset_offset[which] = tcg_current_code_size(s); } +/* Signal overflow, starting over with fewer guest insns. */ +static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s) +{ + siglongjmp(s->jmp_trans, -2); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -1310,8 +1316,7 @@ static TCGTemp *tcg_temp_alloc(TCGContext *s) int n = s->nb_temps++; if (n >= TCG_MAX_TEMPS) { - /* Signal overflow, starting over with fewer guest insns. */ - siglongjmp(s->jmp_trans, -2); + tcg_raise_tb_overflow(s); } return memset(&s->temps[n], 0, sizeof(TCGTemp)); } From patchwork Wed Feb 17 20:19:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383854 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3111470jao; Wed, 17 Feb 2021 12:25:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwWTTyX1uTxDU1iAHjItyU5mPdnLsreqmJ94/sHCz5tJxyNMYLndHuiKHnXsPFSAskuNP3/ X-Received: by 2002:a25:5cd6:: with SMTP id q205mr1805123ybb.489.1613593533559; Wed, 17 Feb 2021 12:25:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613593533; cv=none; d=google.com; s=arc-20160816; b=gvyVHC+m+v3bPEE/K67mnE4VQNwFHDEzA44Me+4gKP0cwDwL1SyZ+u+AKmlCD1Kjzp uOQ2JqbM0KqkmbYib4mphzLVQ9cIRIMYXTZiz+hvBjtGEGqolzMpVYtDcp2dii7JqgNm zibwvYpKEhgglfZ1xAqX2zDsv2OTGHbVjkwZO4cKAY++sF5ko8pitnHe06yS/dKSh+b6 X+CPORLh+E1ct0tzfC1cJYQruSqV0WxSBj42qjYg8nLqlhEpWwlltDO+jM1HSQEYMzKd +ciyLfTr4QDDY9KYsIgDLQUYAgnOm9sNRcwkySoVZi53JbdyGpYp72uSnO1rILJVWzv3 z82g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xzKpOz1dnkvT+2F/uu8BRDtdRIBrUsrfNHwaFpPfXw4=; b=mnjHEdwHcnQC9dPt7j3M/bx5TCEB5SLhUjJpvLnciy0MZJP3/DDYuz1GPoBckOiNgb sHDgqMe6Hm0zgYbvyOdFf5tFkI/T9JzUoMhbrn0If9S5iAUKcQmydHhNZ5nALKAYZREu bfPclfBPGIBp9ebz2SBlpQyfaTWTOGGrl+v+JlFogJ3ha67W9Kp7n/QDeO21jkDO2Sp5 w9BHp+qRYZN4oKGisKxUUj9BO7NzTZe5KPgveXAnWAAN8fG1AsM6iYKh8csdJ2wi8R+x NsnfbrlrGetGx+aVVB2qUGZBpzc1+Gln0UnY1DXIl8B7QvNIB+zfGTZfQvC+LYmKZeNC Wvqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nCwovk5b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Date: Wed, 17 Feb 2021 12:19:28 -0800 Message-Id: <20210217202036.1724901-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson --- For TCI, this indicates a bug in handle_cpu_signal, in that we are taking PC from the host signal frame. Which is, nearly, unrelated to TCI at all. The TCI "pc" is tci_tb_ptr (fixed in the next patch to at least be thread-local). We update this only on calls, since we don't expect SEGV during the interpretation loop. Which works ok for softmmu, in which we pass down pc by hand to the helpers, but is not ok for user-only, where we simply perform the raw memory operation. I don't know how to fix this, exactly. Probably by storing to tci_tb_ptr before each qemu_ld/qemu_st operation, with barriers. Then Doing the Right Thing in handle_cpu_signal. And perhaps by clearing tci_tb_ptr whenever we're not expecting a SEGV on behalf of the guest (and thus anything left is a qemu host bug). --- v2: Retain full struct initialization --- tcg/tcg.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index bbe3dcee03..2991112829 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -513,11 +513,21 @@ static void tcg_region_trees_init(void) } } -static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p) { - void *p = tcg_splitwx_to_rw(cp); size_t region_idx; + /* + * Like tcg_splitwx_to_rw, with no assert. The pc may come from + * a signal handler over which the caller has no control. + */ + if (!in_code_gen_buffer(p)) { + p -= tcg_splitwx_diff; + if (!in_code_gen_buffer(p)) { + return NULL; + } + } + if (p < region.start_aligned) { region_idx = 0; } else { @@ -536,6 +546,7 @@ void tcg_tb_insert(TranslationBlock *tb) { struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr); + g_assert(rt != NULL); qemu_mutex_lock(&rt->lock); g_tree_insert(rt->tree, &tb->tc, tb); qemu_mutex_unlock(&rt->lock); @@ -545,6 +556,7 @@ void tcg_tb_remove(TranslationBlock *tb) { struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr); + g_assert(rt != NULL); qemu_mutex_lock(&rt->lock); g_tree_remove(rt->tree, &tb->tc); qemu_mutex_unlock(&rt->lock); @@ -561,6 +573,10 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) TranslationBlock *tb; struct tb_tc s = { .ptr = (void *)tc_ptr }; + if (rt == NULL) { + return NULL; + } + qemu_mutex_lock(&rt->lock); tb = g_tree_lookup(rt->tree, &s); qemu_mutex_unlock(&rt->lock); From patchwork Wed Feb 17 20:19:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383850 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3109696jao; Wed, 17 Feb 2021 12:22:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJzwYiOVbTJ0jNzXdmEFGGmQxf3jbWB2N2NoxUMaiZdYuoWYntp02ZwaFPEENUt5SNHL/jwQ X-Received: by 2002:a25:c7c6:: with SMTP id w189mr1582682ybe.323.1613593360303; Wed, 17 Feb 2021 12:22:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613593360; cv=none; d=google.com; s=arc-20160816; b=G/m21JcwYXeNXt1uvoIYljjMnstKdHsz3BzZW96dCIXav24T841cHSVtbI/TY3ePNd 1dVCw3qf+u8D+5dKYGyeAFLMAySbBgzhjZg17mGs+TjCTuDxej+x6t3/aRK+aGJ98al0 QkLqSNSiulWkdTTGdd6mQzwzzPLkNrQ/69V3oxw8q0Tv+mk9xZPq/n2A1jqSKGR7NFxc qQB80fzrlyNfqDnvN8X8OcLuaRXk7jK1JGCY4iMHUXDh8a8qHeN99xYCVgJxK/2gQxx4 JAYEmtpdXDEzD3FBPxT9j3nS+FTpdbMcti6uwkoWa5VpnvOfzLnp+ODRhnsZo4w4l2od jJkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VvjDH0d9yENa4ecfbUN1MGRyNECdD1MomwyxKEWSk7s=; b=KHqlVsYmC5tmKnxI9O6MJ9dzsntGGDQPTX/aefizy2HgCDlR/rt01RI6c63TvLB/xm tdnfwChV6TRymvDVsGtwscItDDUzWMhdI02Mw1DhsiyCAHEUVLuy8SL7RhJ8U86sA1Pa uu6LOEMjR8DUAfMowgVK7JA0u0k4sTyGDHipvRY9Zdnu88eZ0uqCqdvgXhu9b+iX6cMZ aWFLCnikGFppsJ0JKyLDsX9BxLYWHYMnKxoZvIm2E6TQw2/F4x/GaJmVtJlpTs7kQHBN vx1upkEQxLxG8AlkGyzbm/4jLva7Q5k3uC2gWm9lCme3EfPoekU3z3yXRttb3h5E+YRt KOoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I3lzKJEi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Date: Wed, 17 Feb 2021 12:19:29 -0800 Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 204 ++++++++++++++------------------------- 1 file changed, 73 insertions(+), 131 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index feac4659cc..c79f9c32d8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -380,6 +380,18 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +#if TCG_TARGET_REG_BITS == 64 +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ + case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { @@ -391,6 +403,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_exit_tb: tcg_out64(s, args[0]); break; + case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* Direct jump method. */ @@ -404,15 +417,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_br: tci_out_label(s, arg_label(args[0])); break; - case INDEX_op_setcond_i32: + + CASE_32_64(setcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; + #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ @@ -423,60 +439,54 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; -#elif TCG_TARGET_REG_BITS == 64 - case INDEX_op_setcond_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - break; #endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: + + CASE_32_64(ld8u) + CASE_32_64(ld8s) + CASE_32_64(ld16u) + CASE_32_64(ld16s) case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: + CASE_64(ld32u) + CASE_64(ld32s) + CASE_64(ld) + CASE_32_64(st8) + CASE_32_64(st16) case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: + CASE_64(st32) + CASE_64(st) stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] == (int32_t)args[2]); tcg_out32(s, args[2]); break; - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ - case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ - case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ - case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ - case INDEX_op_or_i32: - case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + + CASE_32_64(add) + CASE_32_64(sub) + CASE_32_64(mul) + CASE_32_64(and) + CASE_32_64(or) + CASE_32_64(xor) + CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */ + CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */ + CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ + CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ + CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ + CASE_32_64(shl) + CASE_32_64(shr) + CASE_32_64(sar) + CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); break; - case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ + + CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); @@ -486,79 +496,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out8(s, args[4]); break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ - case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ - case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ - case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ - case INDEX_op_or_i64: - case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; - case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <= UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <= UINT8_MAX); - tcg_out8(s, args[4]); - break; - case INDEX_op_brcond_i64: + CASE_32_64(brcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; - case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */ - case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */ - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ - case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ - case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ - case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ - case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ - case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ - case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ - case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: -#endif /* TCG_TARGET_REG_BITS == 64 */ - case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ - case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ - case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ - case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ - case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ - case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ - case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */ - case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ + + CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ + CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ + CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ + CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ + CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ + CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ + CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ + CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ + CASE_64(ext_i32) + CASE_64(extu_i32) + CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ + CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ + CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); break; - case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; + #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: @@ -584,31 +545,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[3]); break; #endif - case INDEX_op_brcond_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; + case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS == 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; case INDEX_op_qemu_st_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); @@ -617,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } tcg_out_i(s, *args++); break; + + case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS == 32) { @@ -628,8 +568,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } tcg_out_i(s, *args++); break; + case INDEX_op_mb: break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ From patchwork Wed Feb 17 20:19:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383855 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3112787jao; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Date: Wed, 17 Feb 2021 12:19:30 -0800 Message-Id: <20210217202036.1724901-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 1c667537fe..4ade0ccaf9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) } #endif -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint8_t)tci_read_reg(regs, index); -} - static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { return (uint16_t)tci_read_reg(regs, index); @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -/* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - uint8_t value = tci_read_reg8(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 = tci_read_r8(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) = t0; @@ -722,8 +709,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 = *tb_ptr++; - t1 = tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 @@ -916,8 +903,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 = *tb_ptr++; - t1 = tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 From patchwork Wed Feb 17 20:19:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383863 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3117567jao; Wed, 17 Feb 2021 12:36:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJyP08qIQwC/l4DE4Pd3CX/zJVVLVY69TFVwHlPnFR3KHZGllq4oQ8lXz/XED5uLyE1lo1Uq X-Received: by 2002:a25:1f8a:: with SMTP id f132mr1778082ybf.77.1613594165060; Wed, 17 Feb 2021 12:36:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594165; cv=none; d=google.com; s=arc-20160816; b=SAYIT+OkUoBXtcxryRQmBbo544BX5PY9Tc+FpXQR1PlJfB27c2IR2Bbh7ScUBdsgaM p0SYnpqRXdw70mfULgU/c8QPdaOFxGwsNJLsqlSxkANVzTECPdG7h14wA9OqVyjae9a7 Qhjm0hhN0RaR4deMZRhcwti20PggbAh2km8oMkVCse/oDNHjlB8oYlbq6UqjVgCs9pIg RG1YtX4K9mGhmD34qPWqxp9CcDoObLnMrztJpyQ7uRldaob6CGi19BmdarV2bjseWu8R /mFqpenRRPugXx2WR72QGeQTAxowf8B4nQ5pfRp3jROs5VfWizk3IKOeG8xA/2G8G+Gz DBfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=s0epI5FYzBmDpaBBAxqnrVAuCgvURTvdHnKLPkRQG1c=; b=nDPRAkifCkxAWjP56H7sMmeUUGTOKzAnh3dHdJVSBZpeVreueLq6oXKBHdGn5AhNTG pq8RKUQwunrWs7gL15e9DKNfiUriYnnyinhcnZ1t/icP3z+WtLqbiz6HIAe+QFzVUP06 sVm5iEUEjVwClI2FDU7dE3dchXPFAH+Q8bsahhpcC7BlDsExp1XvP+gtWbM3Fm0LamTq 2Qnp9EDR3NvpR1tkSHj+VYRiDhVdY1ZXw8RhYUubOln6ObzuLg6E7W+50PPpmdoe5tqx qpT4FpvJXLos3uzP24tiNnUaVoEsQfT3jX82YDMsTWBhGN9wxzaxy+2P6LJCE3ML8Jl/ yAXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cCumBb77; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Date: Wed, 17 Feb 2021 12:19:31 -0800 Message-Id: <20210217202036.1724901-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext8s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 4ade0ccaf9..7325c8bfd0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - int8_t value = tci_read_reg8s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -695,8 +678,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -910,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 From patchwork Wed Feb 17 20:19:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383858 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3114728jao; Wed, 17 Feb 2021 12:31:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJzskBkDR6ycC+nAX8D1yVpf5WmJOZAdgBAfmN4DV24xJfgfHnFMd2C8f1yF6xc1W4MR/uox X-Received: by 2002:a25:68cf:: with SMTP id d198mr1793651ybc.258.1613593887097; Wed, 17 Feb 2021 12:31:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613593887; cv=none; d=google.com; s=arc-20160816; b=H1dLo49EGhQZCPhMAJXXZM+3LOX2WRTSDb66Z7Ll5R+0XkwcrX+DR8AXeh1tF1ZFk5 xDa2iFJPmoi2ZTE2mqcqTZmk2wG24cnvtC0mNY15UbUSsw0rwumrojJh686//K8QcPGN jXcOP7MtJgXd1YK0hqRtkf1QVTAFwIEKRQXIATQFaPodKeuYCFZSXeErUaT6g/6MmNU5 6JijNlSHt41WNMeehbbJRwlWKmJD9Qapl3Wio82WD0guGSdsS+j1DisSFc7wBoXxpLuD pdROTE9pqD/R+X1S/644NN6PH8bhPO0t10ET8EOlYTVlk+AmxHJ6ageYMigUPI8OavIN zp/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EgfsM+xDw/5+yMWEqnFKIWyZYHRInwuGtrXJDDW2BOY=; b=m6R8o4dmcDH8/BR3A4AjaSf6KFlKC6Ib6bvvHBag7YUxhXeQqCgXYZ1apKkOhGOGif tvwHIlQwBNRjIwQVUDIFxcJsrd0q3bV/qcQvG62/ZlkuaEe2a1cRYbQiMgofgiFtUbt/ Mo4PcaFF1aY0m0nr7ZerX2d0Afw87iSZyogMB48BinebDBlO6T/kRh418T1r0kHveF5v j4coZK/h9qMf60yXEl50u9jLO91B57eAkfyWppJVbAcfaHu49DgTGL8RWqDPYhPVty0o 0KROLlljd+O7o/Stf73kPLXl+tBKXwhl0h60RALAb04+zlNb4YhAsas2wpDnJxZNZl2w vqIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bp59r9W5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:21:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Date: Wed, 17 Feb 2021 12:19:32 -0800 Message-Id: <20210217202036.1724901-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st16 opcodes, and with the call for bswap16 opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 7325c8bfd0..2440da1746 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -71,11 +71,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) } #endif -static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint16_t)tci_read_reg(regs, index); -} - static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { return (uint32_t)tci_read_reg(regs, index); @@ -157,15 +152,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -/* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint16_t value = tci_read_reg16(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ static int16_t tci_read_r16s(const tcg_target_ulong *regs, @@ -509,7 +495,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, *(uint8_t *)(t1 + t2) = t0; break; CASE_32_64(st16) - t0 = tci_read_r16(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) = t0; @@ -699,14 +685,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif @@ -907,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -930,7 +916,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif From patchwork Wed Feb 17 20:19:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383862 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3117548jao; Wed, 17 Feb 2021 12:36:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJztlKqIg17+cZRv2m4aD/oootURRRSycrHxzA2beySJbVhmcyJufh+y3pGU2KxOOOImdB0C X-Received: by 2002:a25:e008:: with SMTP id x8mr1804219ybg.90.1613594164342; Wed, 17 Feb 2021 12:36:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594164; cv=none; d=google.com; s=arc-20160816; b=bTEfQbsLz0JrxGNKG8BGImP20ThR9kqYx17MjFnRl6ND2ycpA9T3816wRxUkxSOCaT fyQMUVrCL5NyUb3qeoPsThx9QUfztRLH9n/mdh3r8pk+7ZjBlpMz71DNJrVB3Ke2Gdva e63ZVgocXGjdXRidf+W306CLgvv8gbMkvC/16nvpkT9rc6czpyX5gS6ZFapZUr7lwX6E 6p/N8OjcBHN5lDaAeDdJf/j/LCinSqpY7FAkUYIbbjt6TGWLwK3VC4/zLtbmkSFp0faK 6pQrHEF1AXr8YXt73zvpmyaqJMCLvOjW21LqHLYoJ+e1vQohYt+o1zjarHt+oBiNgJk/ viNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sLU2XmKG3JbG1D9u9PmlE0yiGugHvDS0F3Tdhc3De6g=; b=vtAIL1tQvC1svJ8w53xcyaKTs+ObTuuBAA7LNIl6C+E+oqz3giQQQPQ40SO+uT9a90 CQKH2jyPDGEg+2FpYdwvwE6G1VcBZjttj+/Y+n2znnnlViLNkoXhkrYUDy+wCZnc6rQk 0WxJ35h1EgHSo+DDGgVillO/3JGux1APU86V0zYBYN5CQJ6YmEPKUnVXRuuE6dMlzB0T 8wDv587FzUT5pCHPM312rlXNHV8LI8N/OkGYDxQ7DuYgjnKd2vlJkOHm/rFzwyZWH56S kaTpugQTYGIZGEmr+ktjLAcBv0IdFpBgFRrjPovjGrtna1ToArTt+troxzbuFjoXvkeM ndMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OyUw7VdG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Date: Wed, 17 Feb 2021 12:19:33 -0800 Message-Id: <20210217202036.1724901-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext16s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 2440da1746..8b91e6efc3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int16_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS == 64 static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { @@ -152,17 +145,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -/* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int16_t value = tci_read_reg16s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (32 bit) from bytecode. */ static uint32_t tci_read_r32(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -671,8 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 = *tb_ptr++; - t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 @@ -886,8 +868,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 = *tb_ptr++; - t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 From patchwork Wed Feb 17 20:19:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383867 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3119453jao; Wed, 17 Feb 2021 12:39:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJxR6GiT/Kgu1o4VKzfqtgQJzcnWX4JV8KGfD7pJLBIUG9EAvSfynWkrZ+W4Bs979wBfRsfX X-Received: by 2002:a25:8087:: with SMTP id n7mr1769647ybk.367.1613594362708; Wed, 17 Feb 2021 12:39:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594362; cv=none; d=google.com; s=arc-20160816; b=NCHhcbdvLt3lHg8WyfN28Z648By5ysNxsUZdRtcTFUvcj+it2SziNJjRUeVxUCfZgb 4w9o2f82uX9O4DXVWwsSViwJEKllqvaA4C/vbAwsXWcIdn1feBY6S3hT0U7bx2BXGOzd UrdVVcUc6meCKElXlpJn/Z9xsAdVEShEmj5mxfCttyiWNyvIj0BMXcdyv1XeowZG6bNf hULSeQEO8XE7GSSTMnPPxPG9GubuPClzEqs3pxMThy5P9EcsOlBZD0lhisgOX091nm76 WuBipV/QBDUu1PdeWMeXTZVKYapH1IYwwNBdhWEUxGDWkhE5Zpls2Isvp0+CYjTNY8/U kpZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1zh4Oi86+XA2CDAVF1jA84UCd8h/wBVxBroPuyJg4Sk=; b=X4+uduLtKiaaBWwl6V7tl4CXr58JBAx2M5gmpxiaLmVKRSJi/LjSsNkE9uZZe/ew7t 83Wb2C76MKQcZoQgwJPS769KSiQliMGtLJPkeJj03yLUuKUYyNc3mZiqZz3frcvvpZ2w l30YsuhWQ24rceuHfRnqnNe/MVt6NBgGXd2NIxtvKECmODOsR0u1kNguWe2qmv9pCj7/ zvlsOBzdcNTCDI0EuunvwBnFbbmD7fSFt1POwrCDqgp7fMrePXrc9zNVGBXqy84vnu19 NvvbZxBb+oC+DaOKNi3CrbbeHB72g0WCDmbAS15WkG8yTpjrO2QZ9aMzMlo4MTatv+ff dSYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ly2ufi3x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Date: Wed, 17 Feb 2021 12:19:34 -0800 Message-Id: <20210217202036.1724901-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext32u opcodes, and allow truncation to happen for other users. Signed-off-by: Richard Henderson --- tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------ 1 file changed, 54 insertions(+), 68 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 8b91e6efc3..a5aaa763f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -64,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) } #endif -static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint32_t)tci_read_reg(regs, index); -} - #if TCG_TARGET_REG_BITS == 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -145,22 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -/* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t value = tci_read_reg32(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low = tci_read_r32(regs, tb_ptr); - return tci_uint64(tci_read_r32(regs, tb_ptr), low); + uint32_t low = tci_read_r(regs, tb_ptr); + return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register (32 bit signed) from bytecode. */ @@ -404,8 +390,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; case INDEX_op_setcond_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -428,7 +414,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_mov_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -484,7 +470,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; case INDEX_op_st_i32: CASE_64(st32) - t0 = tci_read_r32(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) = t0; @@ -494,62 +480,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_add_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 / t2); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 % t2); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; case INDEX_op_and_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; @@ -557,41 +543,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_shl_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 31)); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 31)); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp32 = (((1 << tmp8) - 1) << tmp16); @@ -599,8 +585,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i32: - t0 = tci_read_r32(regs, &tb_ptr); - t1 = tci_read_r32(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -638,9 +624,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_mulu2_i32: t0 = *tb_ptr++; t1 = *tb_ptr++; - t2 = tci_read_r32(regs, &tb_ptr); - tmp64 = tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, t2 * tmp64); + t2 = tci_read_r(regs, &tb_ptr); + tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 @@ -681,21 +667,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -892,8 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_extu_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: @@ -905,7 +891,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif From patchwork Wed Feb 17 20:19:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383866 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3119451jao; Wed, 17 Feb 2021 12:39:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJw9wmXdzrEUrdjxyfyLcAgpGUDb4vDmXvNAZ68nyhIlPLxmihaSO1NQqhBIuI5KRRspK1FE X-Received: by 2002:a25:244c:: with SMTP id k73mr1726596ybk.368.1613594362617; Wed, 17 Feb 2021 12:39:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594362; cv=none; d=google.com; s=arc-20160816; b=XDUdOjbK/NrUZVri5BX6pjEoLcvbQspA6gwCHMbVHtLv47hMI/q9IsjLHQgEkHo/dk erNEjIwuoP0VhmcQz4+x84hjWQQQj/dCttANyZl0BlQTNZRVmAkAI2IFOG4LSDhde6DU IsN94oamdyI18K+FmYxkuTo7a/oOBqnlbJY2moRXxbj73hTrPizZlaG0q+c1oqUfS/re lGvBcBqJvFcTlSzmW48zOMVSeeQEWXDDvu5YY4+se6A5nZSqnfMD02cfIgjzny5YtEYh TXK/8OMkk2KiGzgpM76ctCkLXhSag3YqoQ/Wq/l4Dbnc2kFQf4rj66RNY055+PI/sYvJ PbYA== ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Date: Wed, 17 Feb 2021 12:19:35 -0800 Message-Id: <20210217202036.1724901-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext32s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index a5aaa763f8..cef12f263d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_REG_BITS == 64 -static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int32_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS == 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 -/* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int32_t value = tci_read_reg32s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -870,8 +854,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: From patchwork Wed Feb 17 20:19:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383853 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3111438jao; Wed, 17 Feb 2021 12:25:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJzt7akSqDsByXu94rgydwXSyvLKP6WvSwcu5Y9O6lWFXYgGwIHnbLLWlCfONuUAbtNtdLzb X-Received: by 2002:a25:2c49:: with SMTP id s70mr1773880ybs.125.1613593530476; Wed, 17 Feb 2021 12:25:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613593530; cv=none; d=google.com; s=arc-20160816; b=Zps+1ZoW+MaQJl9geZzf3Pg1DGljQKRp9C1JYXIiSlRLLaPU8g5KU963YGWDifYkGk RFKsy1SxZOLGQWnkOYNv84bFPF9qY8g0PmWw/dQEUOULQI9G7MuwxJn8YpdrOBjGvM70 HJl/RIsBYQAKsbK2MMKO+2zEO/J5ECZdJMQMrCGgbEy3i5yDIAjpVZ0N74LNDNe0Yylr keQx3CY0pCXE4YyxbXWNi+e1hr7qMEpu2A8IJLQHv9fgoZvAjCYFyF7jpba2BzO+8XGu ZEaFOWX2qm860nAuKjt0dOrHpBsDbZEHrpK8ywLXHiVuSkFHBU2AqndOUPM5ioA5dVkM g7Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/cgl87lXykdJMny21/UJVDiccpgPXiqD0uRpK0C4eyY=; b=i1+14D2X0HRcN3RbehGZMWlh3w8QJo8NWGnDYCoWa6m0mGQqZ96Et8dkYeGpssD4Jp UHNgOd2UKnKgzNwXTXzCg/InOUy2C+Fk/u73knY0g8GRXI6tK6rFuFtPVFcEcW56rF+i 0k+uY0I1HcH74W1iKuNpXOO8Z/Mf3kvdVFttc7xFdhsWS6z3hXGK4C1XBCVLyVOLfgrR HoVTjgwIbmZBHXs92wW6g/By24ffDDI4fcUM4SWaoQgB0TtFv7ORSr/EBOz2p49MBJDD kod47vzVJ15LaxFTTbNSNTKqLX/UzXQfOXwPLdZTiRi5HDV3Arnp1A0y+cfLN97qWdbJ ejvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EaySR6Ue; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Date: Wed, 17 Feb 2021 12:19:36 -0800 Message-Id: <20210217202036.1724901-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Signed-off-by: Richard Henderson --- tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 51 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index cef12f263d..9efe69d05f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_REG_BITS == 64 -static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) -{ - return tci_read_reg(regs, index); -} -#endif - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint64_t value = tci_read_reg64(regs, **tb_ptr); - *tb_ptr += 1; - return value; + return tci_read_r(regs, tb_ptr); } #endif @@ -390,8 +381,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -672,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: @@ -696,7 +687,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 = tci_read_r64(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) = t0; @@ -706,62 +697,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_add_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; @@ -769,41 +760,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_shl_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp64 = (((1ULL << tmp8) - 1) << tmp16); @@ -811,8 +802,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i64: - t0 = tci_read_r64(regs, &tb_ptr); - t1 = tci_read_r64(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -882,21 +873,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif From patchwork Wed Feb 17 20:19:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383871 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3121564jao; Wed, 17 Feb 2021 12:43:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJx5CH7T3bQxD39bZ2Q4SwCuHMeKwhqaXLReatu2Y28+mnXGg02PDrMsbfOQiHJt+ArUCvEk X-Received: by 2002:a25:dfc5:: with SMTP id w188mr1611763ybg.502.1613594595036; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Date: Wed, 17 Feb 2021 12:19:37 -0800 Message-Id: <20210217202036.1724901-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes add, sub, mul, and, or, xor. Signed-off-by: Richard Henderson --- tcg/tci.c | 83 +++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 58 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 9efe69d05f..d0bf810781 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -451,26 +451,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, *(uint32_t *)(t1 + t2) = t0; break; - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ - case INDEX_op_add_i32: + CASE_32_64(add) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; + CASE_32_64(and) + t0 = *tb_ptr++; + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 & t2); + break; + CASE_32_64(or) + t0 = *tb_ptr++; + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 | t2); + break; + CASE_32_64(xor) + t0 = *tb_ptr++; + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 ^ t2); + break; + + /* Arithmetic operations (32 bit). */ + case INDEX_op_div_i32: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); @@ -495,24 +516,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; - case INDEX_op_and_i32: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i32: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i32: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; /* Shift/rotate operations (32 bit). */ @@ -695,24 +698,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (64 bit). */ - case INDEX_op_add_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); @@ -737,24 +722,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; /* Shift/rotate operations (64 bit). */ From patchwork Wed Feb 17 20:19:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383875 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3123319jao; Wed, 17 Feb 2021 12:46:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJxyRycSfrKKMAUdCuwjv38F1okd/Wt64tFGpM14Z88H4Wz3EQqJMCMSLgpRYy0riYF4dD3C X-Received: by 2002:a5b:7c1:: with SMTP id t1mr1680491ybq.480.1613594786461; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/71] tcg/tci: Merge extension operations Date: Wed, 17 Feb 2021 12:19:38 -0800 Message-Id: <20210217202036.1724901-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes ext8s, ext8u, ext16s, ext16u. Signed-off-by: Richard Henderson --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index d0bf810781..73f639d23a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif From patchwork Wed Feb 17 20:19:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383856 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3112807jao; Wed, 17 Feb 2021 12:27:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5qmf6tMPSdm06H9j5eCF0/P1D7pCT6ppqJHtBA5ylplM5AEBPtqIINB7ITP92LRaFQ/Ho X-Received: by 2002:a25:32c4:: with SMTP id y187mr1893044yby.163.1613593667279; Wed, 17 Feb 2021 12:27:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613593667; cv=none; d=google.com; s=arc-20160816; b=ZP1uoWYWf0amdozto5Py8OtFi/YygnTYiXOZDtvEgZ/qBw7OdyA1HWun47q6PbByOc Sl5mudOnCeUG1LlniFX7IgXRUqzCwtalO1fe3auQJhD9mvFUaeYXBUKRfwPRvPuMj5td 5kCuxGi6sUV/p7VXcQbLVFQAro6rLUYavRkSFVZdyI9VkB0fywqfaipegozRh3hAGOnc ijmBdw73BcQf1qJutBZkHJhPBxW5uiSEljKcT0is43LWqor/1/MliXOm7uSdbsDXiFyR Ve1a+jRSP3QjP0dkbdVLgcrA2hnKHTQpujKh6+XvBoeRB68IFGIl0OC0e4/qaNfUdgnj kf/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xccDHlZG+A/og+PXFW/xFbu9lxlDn8hKgHX6EMXyYhQ=; b=qlGzDHarWyDrsVipMkAQOfnxLcxbJFtpVl97Bef2cVJk9Zvilw5IGfG8QG9468tnOb 3CNGOYfWfi65GTStJKmzkvSOW9M0BMEdyfrBRUXphbJjDMQPGnuQr1ZQeG4kmcKyJTt0 kRq4rzC8Mw6H3lJOYufWl8QyOxI1k5NbJMIoMQmte7CkygjZvCQJY0ARZFjDYq0epxo9 mnmDA7VAvhWVuLlk0TgzW8rJWmOaPMr6Aik/5+r49FbvvgF1TZBjQR9LGhvjpXZ1572G pF6tPBKwjWetP4YQIB0DxRksALPR1n8Vi7jzl8VfNiFV/xCCSZjhYh/Ju0zRUXIDpU8d LnuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YtqmEbw+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Date: Wed, 17 Feb 2021 12:19:39 -0800 Message-Id: <20210217202036.1724901-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These operations are always available under different names: INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove no code with the ifdef. Signed-off-by: Richard Henderson --- tcg/tci.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 73f639d23a..a5ee37eb4e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -779,17 +779,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; } break; -#if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: -#endif case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; -#if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: -#endif case INDEX_op_extu_i32_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); From patchwork Wed Feb 17 20:19:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383870 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3121562jao; Wed, 17 Feb 2021 12:43:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJyrbXRQwqd3h0Sl+IV8pBpdxdR0d4lgZ8n9aegl7lL0KA69PmNmxGuRNGBZHNyLUMMFDF6u X-Received: by 2002:a25:903:: with SMTP id 3mr1654654ybj.275.1613594594878; Wed, 17 Feb 2021 12:43:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594594; cv=none; d=google.com; s=arc-20160816; b=REkBeMLxjXdkdVfXfwZSgQluMZ9AbZpgAOgXMHvWjBYvCAiDIXr6HUr2/+Ytc+pj6O WozC+3J+lMqkCQ0lihTXutwufZDu6BZwRUEVq8ABCoekEAwNA5+NLKNVFUoKPLQzgant tqoaLFf4C4bDDASYj3tmCnaATMRLQixp/o2Enzww7tlpBgNSffJX9KpRdtNTjNkPxFbD az51fEFRYQIsnyozZ11Pp8cMXLFXOB4Bi3JQmydlQX/bOGRYZLHDqSDKW0AXHAwvc4zl PDFnsEueM4dZJHuifPnIT6Fl+PgSKx6BbbquhkrwJZSxgtnv6Ht6awBzl80CpwGjILRR pR6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OneSdNbhFRwD/gEDSE1iypW9deQBMDbQopH2CXvtbwE=; b=jPPzXa+ibOIQJCmQcWOFFi44Y1MwjuEYJBGBwxsMSF150PcoA2/Tvx8M1HIwZBRbUh DdiLmExUIlkMTHFvksIQN2W/rdXGzWkL+epFyGg41INF7vVb+ZJu5diF8vSMWj6w6H3E ud0557rbt9MypBdDZy3g1a01WLzO3771CV3qZx4kOrGlytIzBFATCg5Hy8TxvE+y21QA Onj18lcVY7FyTvfIJTrH5RiDkTkCceFjjzisrPmKGuwnuqfSho0umkoD958Wjrifowkp sdCcsT7+9c4+X00ugCanCxcYLbt08nUeldavEX5yUxshCTlW0yYE5ExEepo3bbOx8IBq u7qQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="w1z/tEvS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/71] tcg/tci: Merge bswap operations Date: Wed, 17 Feb 2021 12:19:40 -0800 Message-Id: <20210217202036.1724901-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes bswap16 and bswap32. Signed-off-by: Richard Henderson --- tcg/tci.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index a5ee37eb4e..288a70287e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -635,15 +635,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, (uint16_t)t1); break; #endif -#if TCG_TARGET_HAS_bswap16_i32 - case INDEX_op_bswap16_i32: +#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 + CASE_32_64(bswap16) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif -#if TCG_TARGET_HAS_bswap32_i32 - case INDEX_op_bswap32_i32: +#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 + CASE_32_64(bswap32) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); @@ -791,20 +791,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; -#if TCG_TARGET_HAS_bswap16_i64 - case INDEX_op_bswap16_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); - break; -#endif -#if TCG_TARGET_HAS_bswap32_i64 - case INDEX_op_bswap32_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); - break; -#endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; From patchwork Wed Feb 17 20:19:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383859 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3114987jao; Wed, 17 Feb 2021 12:31:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJz23fIEN4npIIm+6sl0aCYj7J8Oo0YO6H+j51jdvwoKF8P8ZodB19gDVhkI8Dxgm8T4yvb5 X-Received: by 2002:a25:412:: with SMTP id 18mr1850193ybe.366.1613593913046; Wed, 17 Feb 2021 12:31:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613593913; cv=none; d=google.com; s=arc-20160816; b=MuIc18QFHmaxAyZJ2zqbMw5fTOnUnNjb9kR9O9sanr79npcGrW6rmAEh5Am6mLiLQm R6+VD8W7PvOf4atAXYGiwoETft3z7V15M9tiUbM869uxuQt9mKfv4D0p3fDKiNZi5NzU icCDIm4hH+lqB+DipCHH+ExNxaeEP3/FVAriKsjppotVGgLOJ9NTaahEBU26VRWfrKe+ kBDpZ29+weSSrvciLHfOKjfPqCVbCcpqHzbclpSIXDns9VuCt25oP0KKsJVT2FhKnUhX orcdXcda+AyfM5btgEKO89O/d0jw+kV9TFEBpGQ10w5efRWppud84Ei7e6JvlijLkt3E 1Ucw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nlAJBrBE2gOeL/pHL/++6ehY/SIfIXhi3tsdcdL4xk0=; b=IKRBMwhn+ru0gd2R8NQTcA19F9pfZunbnKaNTuLACgIPx0p2NtFn+Lk4n9zwjczHj4 Ix1LmP4g47WNS65WaUA214nQEHZmGYG7aRUJ0ZJOgmtfdRouegwg4cCx+fsggzW+hn0U 8IIk3liPSti/Dw8L07AGXQGyiUNS6DKZWq1NyhxEfqTUKq4jHmDfamCknwBfaaLuPglU Xwt4F3oh3Z80KuBfjEESc/ca+HMU9ntEosFgpBpiRK4gjgPGxpx/1eS0HYTUn7Jwy0N2 6+WCKqvNF31XT55b+h1JTRDtwmAEt5u5TekuXIA7gbcKsX4tD2IpCJZdq6V0s3Tm55yO NfKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cmbFUgyf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations Date: Wed, 17 Feb 2021 12:19:41 -0800 Message-Id: <20210217202036.1724901-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/tci.c b/tcg/tci.c index 288a70287e..6a0bdf028b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -387,7 +387,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif - case INDEX_op_mov_i32: + CASE_32_64(mov) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); @@ -649,26 +649,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, bswap32(t1)); break; #endif -#if TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: +#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 + CASE_32_64(not) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif -#if TCG_TARGET_HAS_neg_i32 - case INDEX_op_neg_i32: +#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 + CASE_32_64(neg) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_mov_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); - break; case INDEX_op_tci_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); @@ -798,20 +793,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, bswap64(t1)); break; #endif -#if TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); - break; -#endif -#if TCG_TARGET_HAS_neg_i64 - case INDEX_op_neg_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); - break; -#endif #endif /* TCG_TARGET_REG_BITS == 64 */ /* QEMU specific operations. */ From patchwork Wed Feb 17 20:19:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383879 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3125520jao; Wed, 17 Feb 2021 12:50:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJxHvzEkcJBhuuSXK2M9HkW4LV2UcLjyHnxSEMd+at9NoacjhnuLDEaph/CkapWEaURsjn57 X-Received: by 2002:a25:dfc5:: with SMTP id w188mr1647730ybg.502.1613595046907; Wed, 17 Feb 2021 12:50:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595046; cv=none; d=google.com; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval Date: Wed, 17 Feb 2021 12:19:42 -0800 Message-Id: <20210217202036.1724901-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the next patches, we want to use tci_read_r to return the raw register number. So rename the existing function, which returns the register value, to tci_read_rval. Signed-off-by: Richard Henderson --- tcg/tci.c | 192 +++++++++++++++++++++++++++--------------------------- 1 file changed, 96 insertions(+), 96 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 6a0bdf028b..6d6a5510da 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr) /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) +tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value = tci_read_reg(regs, **tb_ptr); *tb_ptr += 1; @@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low = tci_read_r(regs, tb_ptr); - return tci_uint64(tci_read_r(regs, tb_ptr), low); + uint32_t low = tci_read_rval(regs, tb_ptr); + return tci_uint64(tci_read_rval(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - return tci_read_r(regs, tb_ptr); + return tci_read_rval(regs, tb_ptr); } #endif @@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, static target_ulong tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - target_ulong taddr = tci_read_r(regs, tb_ptr); + target_ulong taddr = tci_read_rval(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr += (uint64_t)tci_read_r(regs, tb_ptr) << 32; + taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32; #endif return taddr; } @@ -365,8 +365,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; case INDEX_op_setcond_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); condition = *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -381,15 +381,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); condition = *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif CASE_32_64(mov) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -402,51 +402,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, CASE_32_64(ld8u) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); break; CASE_32_64(ld8s) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); break; CASE_32_64(ld16u) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); break; CASE_32_64(ld16s) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); break; case INDEX_op_ld_i32: CASE_64(ld32u) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 = tci_read_r(regs, &tb_ptr); - t1 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) = t0; break; CASE_32_64(st16) - t0 = tci_read_r(regs, &tb_ptr); - t1 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) = t0; break; case INDEX_op_st_i32: CASE_64(st32) - t0 = tci_read_r(regs, &tb_ptr); - t1 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) = t0; break; @@ -455,38 +455,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, CASE_32_64(add) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; CASE_32_64(sub) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; CASE_32_64(mul) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; CASE_32_64(and) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; CASE_32_64(or) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; CASE_32_64(xor) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; @@ -494,26 +494,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_div_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; @@ -521,41 +521,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_shl_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp32 = (((1 << tmp8) - 1) << tmp16); @@ -563,8 +563,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i32: - t0 = tci_read_r(regs, &tb_ptr); - t1 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -602,64 +602,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_mulu2_i32: t0 = *tb_ptr++; t1 = *tb_ptr++; - t2 = tci_read_r(regs, &tb_ptr); - tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); + tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -674,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_ld32s_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 = tci_read_r(regs, &tb_ptr); - t1 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) = t0; break; @@ -695,26 +695,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_div_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; @@ -722,41 +722,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_shl_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); + t2 = tci_read_rval(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp64 = (((1ULL << tmp8) - 1) << tmp16); @@ -764,8 +764,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i64: - t0 = tci_read_r(regs, &tb_ptr); - t1 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -777,19 +777,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1); break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_rval(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif @@ -896,7 +896,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } break; case INDEX_op_qemu_st_i32: - t0 = tci_read_r(regs, &tb_ptr); + t0 = tci_read_rval(regs, &tb_ptr); taddr = tci_read_ulong(regs, &tb_ptr); oi = tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { From patchwork Wed Feb 17 20:19:43 2021 Content-Type: text/plain; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs Date: Wed, 17 Feb 2021 12:19:43 -0800 Message-Id: <20210217202036.1724901-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin splitting out functions that do pure argument decode, without actually loading values from the register set. This means that decoding need not concern itself between input and output registers. We can assert that the register number is in range during decode, so that it is safe to simply dereference from regs[] later. Signed-off-by: Richard Henderson --- tcg/tci.c | 111 ++++++++++++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 44 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 6d6a5510da..5acf5c38c3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -83,6 +83,20 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) } #endif +/* Read constant byte from bytecode. */ +static uint8_t tci_read_b(const uint8_t **tb_ptr) +{ + return *(tb_ptr[0]++); +} + +/* Read register number from bytecode. */ +static TCGReg tci_read_r(const uint8_t **tb_ptr) +{ + uint8_t regno = tci_read_b(tb_ptr); + tci_assert(regno < TCG_TARGET_NB_REGS); + return regno; +} + /* Read constant (native size) from bytecode. */ static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { @@ -161,6 +175,23 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) return label; } +/* + * Load sets of arguments all at once. The naming convention is: + * tci_args_ + * where arguments is a sequence of + * + * r = register + * s = signed ldst offset + */ + +static void tci_args_rrs(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, int32_t *i2) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *i2 = tci_read_s32(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result = false; @@ -311,6 +342,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint8_t op_size = tb_ptr[1]; const uint8_t *old_code_ptr = tb_ptr; #endif + TCGReg r0, r1; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -325,6 +357,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint64_t v64; #endif TCGMemOpIdx oi; + int32_t ofs; + void *ptr; /* Skip opcode and size entry. */ tb_ptr += 2; @@ -401,54 +435,46 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (32 bit). */ CASE_32_64(ld8u) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(uint8_t *)ptr; break; CASE_32_64(ld8s) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(int8_t *)ptr; break; CASE_32_64(ld16u) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(uint16_t *)ptr; break; CASE_32_64(ld16s) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(uint32_t *)ptr; break; CASE_32_64(st8) - t0 = tci_read_rval(regs, &tb_ptr); - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - *(uint8_t *)(t1 + t2) = t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + *(uint8_t *)ptr = regs[r0]; break; CASE_32_64(st16) - t0 = tci_read_rval(regs, &tb_ptr); - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - *(uint16_t *)(t1 + t2) = t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + *(uint16_t *)ptr = regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - t0 = tci_read_rval(regs, &tb_ptr); - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - *(uint32_t *)(t1 + t2) = t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + *(uint32_t *)ptr = regs[r0]; break; /* Arithmetic operations (mixed 32/64 bit). */ @@ -673,22 +699,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Load/store operations (64 bit). */ case INDEX_op_ld32s_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(int32_t *)ptr; break; case INDEX_op_ld_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + regs[r0] = *(uint64_t *)ptr; break; case INDEX_op_st_i64: - t0 = tci_read_rval(regs, &tb_ptr); - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_s32(&tb_ptr); - *(uint64_t *)(t1 + t2) = t0; + tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + ptr = (void *)(regs[r1] + ofs); + *(uint64_t *)ptr = regs[r0]; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/71] tcg/tci: Split out tci_args_rr Date: Wed, 17 Feb 2021 12:19:44 -0800 Message-Id: <20210217202036.1724901-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 5acf5c38c3..e5aba3a9fa 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * s = signed ldst offset */ +static void tci_args_rr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -422,9 +429,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif CASE_32_64(mov) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = regs[r1]; break; case INDEX_op_tci_movi_i32: t0 = *tb_ptr++; @@ -635,58 +641,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS == 64 @@ -799,21 +797,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap64(t1)); + tci_args_rr(&tb_ptr, &r0, &r1); + regs[r0] = bswap64(regs[r1]); break; #endif #endif /* TCG_TARGET_REG_BITS == 64 */ From patchwork Wed Feb 17 20:19:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383883 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3127162jao; Wed, 17 Feb 2021 12:53:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJy8/8U/YN/pZaP0XIunTX4zrL7pKk28+005Idc2aNdbsf6Apl5X/hSRYy8U9kfuTrnPzYNt X-Received: by 2002:a25:b09e:: with SMTP id f30mr1973680ybj.199.1613595223732; Wed, 17 Feb 2021 12:53:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595223; cv=none; d=google.com; s=arc-20160816; b=jlDaw+LA9jUvdqJcnYCvOJSxfW61AjZgzGD1QQbdngaMP2MZwfsjFPbQd9C5hrYHY6 8gK0ZlFlwO4JfHL1DVVmeUgcdaT99RgYKZhxxNTmyTqX3A1t0pkmL3oWih3pzzOWakbE mNSQoGN3b8hw+EruJ7zckUcWD+RJJ8R/BndURBmONFbMAi/6/ucuWYXHkQ1JzAKBLo+V h7iyvSmuAEJQjLU4CZTltqFuJI5QB9jUogG13WgBx4ylo9LTsBAgNCCLr5ZX34GQEuW/ kRpUFv+nnJHezV80QezJCK8g0RpzpkqMldfzMcsD6yKk/EnDTTmV+h8sT0gyVf6FN9fa wk0Q== ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr Date: Wed, 17 Feb 2021 12:19:45 -0800 Message-Id: <20210217202036.1724901-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 154 ++++++++++++++++++++---------------------------------- 1 file changed, 57 insertions(+), 97 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index e5aba3a9fa..1c879a2536 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 = tci_read_r(tb_ptr); } +static void tci_args_rrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); +} + static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { @@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint8_t op_size = tb_ptr[1]; const uint8_t *old_code_ptr = tb_ptr; #endif - TCGReg r0, r1; + TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; @@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (mixed 32/64 bit). */ CASE_32_64(add) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] + regs[r2]; break; CASE_32_64(sub) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] - regs[r2]; break; CASE_32_64(mul) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] * regs[r2]; break; CASE_32_64(and) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] & regs[r2]; break; CASE_32_64(or) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] | regs[r2]; break; CASE_32_64(xor) - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] ^ regs[r2]; break; /* Arithmetic operations (32 bit). */ case INDEX_op_div_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; /* Shift/rotate operations (32 bit). */ case INDEX_op_shl_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror32(t1, t2 & 31)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (64 bit). */ case INDEX_op_div_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; /* Shift/rotate operations (64 bit). */ case INDEX_op_shl_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, rol64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tci_write_reg(regs, t0, ror64(t1, t2 & 63)); + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + regs[r0] = ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 From patchwork Wed Feb 17 20:19:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383873 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3123293jao; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc Date: Wed, 17 Feb 2021 12:19:46 -0800 Message-Id: <20210217202036.1724901-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 1c879a2536..bdd2127ec8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -207,6 +207,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 = tci_read_s32(tb_ptr); } +static void tci_args_rrrc(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *c3 = tci_read_b(tb_ptr); +} + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result = false; @@ -413,11 +422,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tb_ptr = (uint8_t *)label; continue; case INDEX_op_setcond_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - condition = *tb_ptr++; - tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] = tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: @@ -429,11 +435,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - condition = *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + regs[r0] = tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) From patchwork Wed Feb 17 20:19:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383877 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3125024jao; Wed, 17 Feb 2021 12:49:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJz/+s+hWKluo87653t0IkQUViMwlUt4pdYbZBjqFLHDhApoyt1IEi9oz02IXTxxtbvDHBEQ X-Received: by 2002:a25:da0e:: with SMTP id n14mr1967306ybf.356.1613594986149; Wed, 17 Feb 2021 12:49:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594986; cv=none; d=google.com; s=arc-20160816; b=LhKc+A74c1yAMgo8uHJ+AmNSbWRAHT3KmLFFLMW0ciHEC0FFYLCCDXrIYKxpqKYcm0 AamYNXlm30lh8/xO4+Rbm0f4tFTqdvLLQyHvoWVfKky75k4vUIQlwAHIsmSIPNcMQ/5y LauzkqLYWm5LNZksBSVfr3JrjuGLHSYHW5qNXg0v4rrBnNpyMlwK5Pu3HUbeCC24H+ch D5jsfFGTzLRPrV6m0DkKA/Hocgxb6zWA9epTsKV96DZ4z/myqBFSZ0VY1UL61iX87uZS HfH79t9UKYl868aDZ6NSlxKQP+BOyieqib8mlWrljgDh5Ycqwsr1PzIhxW6/1EsNZBRM W5uQ== ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/71] tcg/tci: Split out tci_args_l Date: Wed, 17 Feb 2021 12:19:47 -0800 Message-Id: <20210217202036.1724901-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index bdd2127ec8..6e9d482885 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -184,6 +184,11 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * s = signed ldst offset */ +static void tci_args_l(const uint8_t **tb_ptr, void **l0) +{ + *l0 = (void *)tci_read_label(tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -417,9 +422,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif break; case INDEX_op_br: - label = tci_read_label(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr == old_code_ptr + op_size); - tb_ptr = (uint8_t *)label; + tb_ptr = ptr; continue; case INDEX_op_setcond_i32: tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); From patchwork Wed Feb 17 20:19:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383864 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3118557jao; Wed, 17 Feb 2021 12:37:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJxBI6IqeiGVe0Tm1EoQ07xJXkKGqnCy7jgu6KynHJzPGYA/zGGFQIIVLju2jXeVF82nPC3c X-Received: by 2002:a25:4906:: with SMTP id w6mr1828922yba.324.1613594267607; Wed, 17 Feb 2021 12:37:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594267; cv=none; d=google.com; s=arc-20160816; b=gQxylBvMe5nkRkhulWOiEpVDhNGrrs7khnP4NDD056p7s/SbCdfN2PoRcc1fNwhNzq Xe53cPJmLLFXQFtxrx8wJOdG0DY1ImZlcaFH3e/8JKH1Xjzf+8VwILKOWg3oHR99MimN 4dq94JnDkGFyrDw0qEiBJKEn8wWv31OdoEB4RBXiDlH8TY8sWP0bhcsGPVLzmpMyJQeO QrthaBJ+M0WPN3jTAblAId3svm+fOvNHPmmVwL1Sjp0hsaXzla0B9gPObfgeLSs6qOEY HcTcsq78S5hgoXFpmV0nIEyk8a6IHC40Rl1qp8A7599Tac3rPbvwxz8BisaPT2e4b1NB vbSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RxHyIf5IQ/iHhFCB4XIpWAKun69n1MIgbHeQ1l++JBg=; b=G8kGz1HTkQ6B8/05Hy48gnOgK5porcM0hvXf7IT2PBHHmOWM9cO+uqG7MkvF3c5OY1 R4wohG342Mb8ti+TWVanmijlj69aBWnNodWqtK0UKI6OBN5nTDnYrNkO7t5r3yTCM3hJ 0l73ELEZMaTo1QEr7kPMswpP4z8rqoP2BPCGuP8km0R2TLZffMECNGQc0Kkm0U6sqYMC SwdwiQflIBDnGYjR7L2zEdiiZewq3qbv4xxMbtCLeNr0qWA8v3oKBeO82m+IEa9Ctynm u8/C01p3er6ujqi3ItGlwGuPq3ykrF2AYxDxiP5uUQGKmBxPydr1qbN6bGrG3u+/UsiY +QZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="zgL9YjY/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc Date: Wed, 17 Feb 2021 12:19:48 -0800 Message-Id: <20210217202036.1724901-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 6e9d482885..558d03fd1b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -221,6 +221,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 = tci_read_b(tb_ptr); } +#if TCG_TARGET_REG_BITS == 32 +static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *r3 = tci_read_r(tb_ptr); + *r4 = tci_read_r(tb_ptr); + *c5 = tci_read_b(tb_ptr); +} +#endif + static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { bool result = false; @@ -383,7 +396,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 - uint64_t v64; + TCGReg r3, r4; + uint64_t v64, T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -432,11 +446,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: - t0 = *tb_ptr++; - tmp64 = tci_read_r64(regs, &tb_ptr); - v64 = tci_read_r64(regs, &tb_ptr); - condition = *tb_ptr++; - tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition)); + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + T1 = tci_uint64(regs[r2], regs[r1]); + T2 = tci_uint64(regs[r4], regs[r3]); + regs[r0] = tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: From patchwork Wed Feb 17 20:19:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383881 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3127092jao; Wed, 17 Feb 2021 12:53:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJxxxtseA/VudrT87eU5ZAaPrcKubRqPAEOpFba99wewpnOj9UHSPa/mbHPuV/Yl4n99y8bW X-Received: by 2002:a25:442:: with SMTP id 63mr1909908ybe.131.1613595218402; Wed, 17 Feb 2021 12:53:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595218; cv=none; d=google.com; s=arc-20160816; b=DbMhPEVXllyC7n7uIaaYsi9VjtQt1eMvshQkePoklOhewyisjwVWlo8jQ7uwOtA7JC tpj1edtF1dv9A0XVGd1sYepX5SPBPQQlxQkevLb/gVSSX3URlFt3QE9OB+PTacLDDjmz eZ0S7RwIwGnvPJdC76KMqqujAQQN2EPIzgeQt+vngv856q+duBB20NdyUshi2G8/NuT5 qx2rMz0pXFP4WYarG25PMWVkLxiXVuh39Hb3MBK5TCpao2XhHIkWfPTiHeb2gTERO62d n3houar5ugm2bBM+dIpB5X0z4zxOboMwZ12G4OKqpiAEnYrlvHJLpRDoe9oFAKEMIX9i xiag== ARC-Message-Signature: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Date: Wed, 17 Feb 2021 12:19:49 -0800 Message-Id: <20210217202036.1724901-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 52 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 558d03fd1b..c8df45ce28 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -212,6 +212,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr, *i2 = tci_read_s32(tb_ptr); } +static void tci_args_rrcl(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *c2 = tci_read_b(tb_ptr); + *l3 = (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -222,6 +231,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } #if TCG_TARGET_REG_BITS == 32 +static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *r3 = tci_read_r(tb_ptr); + *c4 = tci_read_b(tb_ptr); + *l5 = (void *)tci_read_label(tb_ptr); +} + static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) { @@ -388,7 +408,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tcg_target_ulong t0; tcg_target_ulong t1; tcg_target_ulong t2; - tcg_target_ulong label; TCGCond condition; target_ulong taddr; uint8_t tmp8; @@ -397,7 +416,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 TCGReg r3, r4; - uint64_t v64, T1, T2; + uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; @@ -594,13 +613,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i32: - t0 = tci_read_rval(regs, &tb_ptr); - t1 = tci_read_rval(regs, &tb_ptr); - condition = *tb_ptr++; - label = tci_read_label(&tb_ptr); - if (tci_compare32(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare32(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr == old_code_ptr + op_size); - tb_ptr = (uint8_t *)label; + tb_ptr = ptr; continue; } break; @@ -620,13 +636,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 = tci_read_r64(regs, &tb_ptr); - v64 = tci_read_r64(regs, &tb_ptr); - condition = *tb_ptr++; - label = tci_read_label(&tb_ptr); - if (tci_compare64(tmp64, v64, condition)) { + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); + T1 = tci_uint64(regs[r1], regs[r0]); + T2 = tci_uint64(regs[r3], regs[r2]); + if (tci_compare64(T1, T2, condition)) { tci_assert(tb_ptr == old_code_ptr + op_size); - tb_ptr = (uint8_t *)label; + tb_ptr = ptr; continue; } break; @@ -766,13 +781,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i64: - t0 = tci_read_rval(regs, &tb_ptr); - t1 = tci_read_rval(regs, &tb_ptr); - condition = *tb_ptr++; - label = tci_read_label(&tb_ptr); - if (tci_compare64(t0, t1, condition)) { + tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); + if (tci_compare64(regs[r0], regs[r1], condition)) { tci_assert(tb_ptr == old_code_ptr + op_size); - tb_ptr = (uint8_t *)label; + tb_ptr = ptr; continue; } break; From patchwork Wed Feb 17 20:19:50 2021 Content-Type: text/plain; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI Date: Wed, 17 Feb 2021 12:19:50 -0800 Message-Id: <20210217202036.1724901-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index c8df45ce28..cfbe039fa6 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -121,16 +121,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_REG_BITS == 64 -/* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(const uint8_t **tb_ptr) -{ - uint64_t value = *(const uint64_t *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} -#endif - /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -180,6 +170,8 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * tci_args_ * where arguments is a sequence of * + * i = immediate (uint32_t) + * I = immediate (tcg_target_ulong) * r = register * s = signed ldst offset */ @@ -196,6 +188,22 @@ static void tci_args_rr(const uint8_t **tb_ptr, *r1 = tci_read_r(tb_ptr); } +static void tci_args_ri(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 = tci_read_r(tb_ptr); + *i1 = tci_read_i32(tb_ptr); +} + +#if TCG_TARGET_REG_BITS == 64 +static void tci_args_rI(const uint8_t **tb_ptr, + TCGReg *r0, tcg_target_ulong *i1) +{ + *r0 = tci_read_r(tb_ptr); + *i1 = tci_read_i(tb_ptr); +} +#endif + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -481,9 +489,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = regs[r1]; break; case INDEX_op_tci_movi_i32: - t0 = *tb_ptr++; - t1 = tci_read_i32(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_ri(&tb_ptr, &r0, &t1); + regs[r0] = t1; break; /* Load/store operations (32 bit). */ @@ -703,9 +710,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif #if TCG_TARGET_REG_BITS == 64 case INDEX_op_tci_movi_i64: - t0 = *tb_ptr++; - t1 = tci_read_i64(&tb_ptr); - tci_write_reg(regs, t0, t1); + tci_args_rI(&tb_ptr, &r0, &t1); + regs[r0] = t1; break; /* Load/store operations (64 bit). */ From patchwork Wed Feb 17 20:19:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383874 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3123297jao; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls. Date: Wed, 17 Feb 2021 12:19:51 -0800 Message-Id: <20210217202036.1724901-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index cfbe039fa6..066e27b492 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -435,30 +435,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, switch (opc) { case INDEX_op_call: - t0 = tci_read_i(&tb_ptr); + tci_args_l(&tb_ptr, &ptr); tci_tb_ptr = (uintptr_t)tb_ptr; #if TCG_TARGET_REG_BITS == 32 - tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); + tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11)); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); + tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R4), + tci_read_reg(regs, TCG_REG_R5)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; From patchwork Wed Feb 17 20:19:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383869 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3121128jao; Wed, 17 Feb 2021 12:42:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiQZzkyeiNDQkjUBBD4HWxxfm563LifDSRTxT0BBZIpe8SIHfkTK7NSwrkkU5DQB1EY4d1 X-Received: by 2002:a25:3623:: with SMTP id d35mr1867500yba.180.1613594540389; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb Date: Wed, 17 Feb 2021 12:19:52 -0800 Message-Id: <20210217202036.1724901-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label != NULL has to be removed because that is a valid value for exit_tb. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- tcg/tci/tcg-target.c.inc | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 066e27b492..6fbbc48ecf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { - tcg_target_ulong label = tci_read_i(tb_ptr); - tci_assert(label != 0); - return label; + return tci_read_i(tb_ptr); } /* @@ -400,7 +398,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); - uintptr_t ret = 0; regs[TCG_AREG0] = (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] = sp_value; @@ -815,9 +812,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* QEMU specific operations. */ case INDEX_op_exit_tb: - ret = *(uint64_t *)tb_ptr; - goto exit; - break; + tci_args_l(&tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: /* Jump address is aligned */ tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4); @@ -975,6 +972,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } tci_assert(tb_ptr == old_code_ptr + op_size); } -exit: - return ret; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c79f9c32d8..ff8040510f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: - tcg_out64(s, args[0]); + tcg_out_i(s, args[0]); break; case INDEX_op_goto_tb: From patchwork Wed Feb 17 20:19:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383878 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3125509jao; Wed, 17 Feb 2021 12:50:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJyO+51cvT9SnSbClM/lLg14MAAPDmGwCc1sDwpmuX0P79g1+OD+tsqjQTAg2TYxaXB4HmRC X-Received: by 2002:a25:4f41:: with SMTP id d62mr1844911ybb.354.1613595045888; Wed, 17 Feb 2021 12:50:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595045; cv=none; d=google.com; s=arc-20160816; b=QJCml6Q2zm2wniafxJZgb3zdQK887tn293ALYvHuNcNJ6ZjydqGZf77STqQWZBCuE7 Z3NIMu7fHWWNS6jlzAcP3iHN1L0AlGB49Dz450C1AZsKvCkwOUTWxuNRwuguDfxeTUvI lRGLw5UkIYFvZipeswS1oYUKs+XtdLBac0zX4H4jPnBabfE3CDmR12zDZ2SNiD2slA6G O+UCIXQXAC7WNFL6AzNGJCLLtb2L7PwTr7R5zfixq6AreoSU7+BNH42B1vJRKRYWFrtZ lXmVQWnE1pbS78K72RE+AwhQ26sH6o1Us7KBBhAangrDnqOfXwNU3AxUFXkqlULUr22o EIRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tDBHUplRWlhhF0tIGzcFewPFwl6oh2HCB/aPTX+DVBc=; b=Vx8C2JJRM8xz4urHsPGMbqmgqYwTjnHxPmFgdmCJjlTpbSMyEws5kZjy1BS/65ApBY Jj+iEVAbUR4sylm70qIHSHHMDr7Xax1lmdKIH2X/Axt90BVnpMZOtnVsK1NVj4SlJRWB /4wpwI08gcF630JhEfMNQW55wupdCxPz2OMs1YCg+s3MYGOZJlyoSDMysDjuUZV+jISA VEakj8/yyZrnZr22CCtSQRrFFEMsXtJp5ErjrTsKn5SrzWrCR9vVMqtkZenUAgjrLT8W 6NNOMfXKfGkXLksjzT7p9qcQZt7plL91N8s/NOub+mjs7NwO08nx2rvvkpYZDniQxCBL qXJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w4mhJFiz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb Date: Wed, 17 Feb 2021 12:19:53 -0800 Message-Id: <20210217202036.1724901-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 11 +++-------- tcg/tci.c | 8 +++----- tcg/tci/tcg-target.c.inc | 13 +++---------- 3 files changed, 9 insertions(+), 23 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9c0021a26f..9285c930a2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -87,7 +87,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 @@ -174,12 +174,7 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) -{ - /* patch the branch destination */ - qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); - /* no need to flush icache explicitly */ -} +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #endif /* TCG_TARGET_H */ diff --git a/tcg/tci.c b/tcg/tci.c index 6fbbc48ecf..3fe0831b33 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -816,13 +816,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, return (uintptr_t)ptr; case INDEX_op_goto_tb: - /* Jump address is aligned */ - tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4); - t0 = qatomic_read((int32_t *)tb_ptr); - tb_ptr += sizeof(int32_t); + tci_args_l(&tb_ptr, &ptr); tci_assert(tb_ptr == old_code_ptr + op_size); - tb_ptr += (int32_t)t0; + tb_ptr = *(void **)ptr; continue; + case INDEX_op_qemu_ld_i32: t0 = *tb_ptr++; taddr = tci_read_ulong(regs, &tb_ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ff8040510f..2c64b4f617 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -405,16 +405,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump method. */ - /* Align for atomic patching and thread safety */ - s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4); - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* Indirect jump method. */ - TODO(); - } + tcg_debug_assert(s->tb_jmp_insn_offset == 0); + /* indirect jump method. */ + tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); set_jmp_reset_offset(s, args[0]); break; From patchwork Wed Feb 17 20:19:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383887 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3129047jao; Wed, 17 Feb 2021 12:57:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJyvG71y8utEdDcQ0EFMX0IulzON1ELC3uFzkO4RTcOJeugyQFo8JGPdMH7b/0dIWIPn7rf6 X-Received: by 2002:a25:7dc4:: with SMTP id y187mr1966291ybc.477.1613595440856; Wed, 17 Feb 2021 12:57:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595440; cv=none; d=google.com; s=arc-20160816; b=oMVkOjFvJ5e+X4JwFzGs51ByjKpmEoeA1xPHYZ83ztBX5eJE2vDLL72KRVNlER3bql I7Mc1DVjPE5EN+eVeTIR50+mC+zrnIP/zVBo+dWjHE4jmi2K1lK7N4goRAvL23ldITki QFTfCeciZPkN8s/Bg2AnBvF8wL4zTsLsHy8Hel7Mn6nk0r0/HVJWoEYpDuFWsB5QzMH7 gW03VSPwyMYlHyzZQOhyEUBRl1FA68jcHinY/5lCXCiWObh60w6zTP8sjquC3scmEfLB R7q9GZXubHubeK1ggmYAkBJAsd7iEs0DPWXwM6p33iK81LcL3Aa7ohyH3DGiQ5zphJmh PgXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E7uiPbIkaltXGyGrTOejJhAFYjDYkkPY5RpXmb9ap/U=; b=BXnqWLkZKwwCl7+oGirAOlTUQQlsEp8CBZMUlah9igBbwchkS+ngE9AliEvfbeCbGE 7L+0so3VrhzhRe24ii5PjcfkGHo2MM3gZWHfijKchMF5h8ekT+SmBF1/TQVh8ZMnGYo3 TuiC44HRDgXlinbH7ImHROaga3V2iXnxC8mPYEXUwwiZoDSxxrd0+MNRsD7tL4bA7LLi XRd2W/qMwPoiyHX9nr/gy/r55l4u3RnsJxB9hlfBb7caSdVw4Pv2LxRtfG3LibVnYBzJ ZCgnDDmJ1Pvay80xTJyPOUWMOik1QaOTjsYqtCClaw40aoximoooAGn92F/FGaZ1oXZy hGoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FNVb6l0Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr Date: Wed, 17 Feb 2021 12:19:54 -0800 Message-Id: <20210217202036.1724901-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 3fe0831b33..8b38687d9a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -258,6 +258,17 @@ static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, *r4 = tci_read_r(tb_ptr); *c5 = tci_read_b(tb_ptr); } + +static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *r3 = tci_read_r(tb_ptr); + *r4 = tci_read_r(tb_ptr); + *r5 = tci_read_r(tb_ptr); +} #endif static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) @@ -420,7 +431,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 - TCGReg r3, r4; + TCGReg r3, r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -626,18 +637,16 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: - t0 = *tb_ptr++; - t1 = *tb_ptr++; - tmp64 = tci_read_r64(regs, &tb_ptr); - tmp64 += tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 = tci_uint64(regs[r3], regs[r2]); + T2 = tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - t0 = *tb_ptr++; - t1 = *tb_ptr++; - tmp64 = tci_read_r64(regs, &tb_ptr); - tmp64 -= tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, tmp64); + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + T1 = tci_uint64(regs[r3], regs[r2]); + T2 = tci_uint64(regs[r5], regs[r4]); + tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_brcond2_i32: tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); From patchwork Wed Feb 17 20:19:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383868 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3120555jao; Wed, 17 Feb 2021 12:41:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJwJTsrwdJhBX7vIpw79L7vouKVE0ju6GVuGs7Uhmc/r+xo319YRrm3VcZ8ifpwGtAwepXxl X-Received: by 2002:a25:8b8b:: with SMTP id j11mr1921764ybl.305.1613594476836; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr Date: Wed, 17 Feb 2021 12:19:55 -0800 Message-Id: <20210217202036.1724901-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 8b38687d9a..10f58e4f25 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -237,6 +237,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, } #if TCG_TARGET_REG_BITS == 32 +static void tci_args_rrrr(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *r3 = tci_read_r(tb_ptr); +} + static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { @@ -659,11 +668,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } break; case INDEX_op_mulu2_i32: - t0 = *tb_ptr++; - t1 = *tb_ptr++; - t2 = tci_read_rval(regs, &tb_ptr); - tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 From patchwork Wed Feb 17 20:19:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383885 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3128374jao; Wed, 17 Feb 2021 12:56:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJy8H82bMPcS81KXUIZ9E1mj0DqTpMVSbXRhNdZ35HVgA2JmagdUP5O2xrh/TLWYon6MNhKU X-Received: by 2002:a25:3853:: with SMTP id f80mr1853875yba.514.1613595367422; Wed, 17 Feb 2021 12:56:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595367; cv=none; d=google.com; s=arc-20160816; b=0gWQQhrkbzX61X4z3aSMq5E2QQ44CBNKsYophBEsIjz4EjRzXkQ4BYR+ni30taxdl5 t3iYI8TU2dM4dJgtF+/BY3bgWj3DmgU3hspjcf+9R/cnhNc7GWuX3HGc3aVRylysYbt6 ioQwvuwv3126N6+O+Kh9HCXtzMTpfXKIJhzAAorMZJEoESIo8/oN7daYW9A8TVbLyvuR dy3L/jpTqEMac+iGnFmDDrK9uf2pcSYENgdGXTg8Wak6+xafpmeidW3F26sw5Rkhde+C OUrQ8BtSXIDCplMu/+Y4wXbrUxSIJo/Dx/QnJl5dwH2BzqilkjVgbLnnQUB7vSJHEVz6 UD9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e1N26oOEBH/mKZCKJR62A/M2uXOOm6+5WQ72+nFodnM=; b=oR9DNRcCAd3ou7IJIS60rrLeLF7ED/1PyO8SHwoOEX1DRcNBMXKsfSX4MeMT63vPPV winuym784dVMcf42ZWYgW2Rkm1ntBz87deCKA9X7Bi0htMA39pSprXpmrv+KrsMMUSeP TS4h6PmfnkNJ7PFy2aEQoTjER08JHtreZ+G91KvnHf9OZ5Ip2TqEJkSDSk7qM6lC68XQ ldGAmeWxleL1qb6zx99mHqAeJaUPyoK+d8Ef7pJZELftBU6wM2Hvfpdux+CyI0qcbQu9 oQxlzS2TkKXNr0Y5T25Xk+Ltbq4tTPgi2vUe/w27Am9FR6YvMxnseHXZhLUA8V0ptjZJ Ev+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J7Af9yOH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/71] tcg/tci: Clean up deposit operations Date: Wed, 17 Feb 2021 12:19:56 -0800 Message-Id: <20210217202036.1724901-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 - tcg/tci.c | 33 ++++++++++++++++----------------- tcg/tci/tcg-target.c.inc | 24 ++++++++++++++---------- 3 files changed, 30 insertions(+), 28 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index f51b7bcb13..316730f32c 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -13,7 +13,6 @@ C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) C_O1_I1(r, r) -C_O1_I2(r, 0, r) C_O1_I2(r, r, r) C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) diff --git a/tcg/tci.c b/tcg/tci.c index 10f58e4f25..3ce2b72316 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * tci_args_ * where arguments is a sequence of * + * b = immediate (bit position) * i = immediate (uint32_t) * I = immediate (tcg_target_ulong) * r = register @@ -236,6 +237,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 = tci_read_b(tb_ptr); } +static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, uint8_t *i3, uint8_t *i4) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *i3 = tci_read_b(tb_ptr); + *i4 = tci_read_b(tb_ptr); +} + #if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -432,11 +443,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; - tcg_target_ulong t2; TCGCond condition; target_ulong taddr; - uint8_t tmp8; - uint16_t tmp16; + uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 @@ -627,13 +636,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tmp16 = *tb_ptr++; - tmp8 = *tb_ptr++; - tmp32 = (((1 << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: @@ -789,13 +793,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tmp16 = *tb_ptr++; - tmp8 = *tb_ptr++; - tmp64 = (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 2c64b4f617..640407b4a8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -126,11 +126,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotr_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - return C_O1_I2(r, r, r); - case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - return C_O1_I2(r, 0, r); + return C_O1_I2(r, r, r); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: @@ -480,13 +478,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <= UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <= UINT8_MAX); - tcg_out8(s, args[4]); + { + TCGArg pos = args[3], len = args[4]; + TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <= max); + + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out8(s, pos); + tcg_out8(s, len); + } break; CASE_32_64(brcond) From patchwork Wed Feb 17 20:19:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383889 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3130154jao; Wed, 17 Feb 2021 12:59:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJzGdm7O1ogx18m0/RtPI+P9uhanmk5bKxMJEFkUU8MaVCEGVxoE7M2+Yhf/vOytv8fS3Ezs X-Received: by 2002:a5b:30f:: with SMTP id j15mr1870006ybp.431.1613595583449; Wed, 17 Feb 2021 12:59:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595583; cv=none; d=google.com; s=arc-20160816; b=w/4GSv/CPwX3VEl283r0RUibbqb1ib7ubByKzQ7oZZGrA0+ssoEISe3qmh/m3LVVbC TpYiJhbKhN6oNRgbLFeHcR33bw9guglYKu2hxUOmDfHbGBVEMnlfCtFmKDlzLRSZEMz6 IKXcGvJi3bD6ykCC/0UbAHG0tedbgwTeSKy3oYdvlqzdTWw4wocjEJ+NAgL7+GhuT71Y rlPNZOZ3SxjUqxTvImZjPSrA6blSigMwyeKPk85Urv+adTdRrizsBfzTgK0NSeKOiqwd jGgVm6jTrIIIe0eSsxL7iOyLfyte/AOSjIT87iJy359fytvWjUrS+FtyYWrTFdzwzrqA JvwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NtYy7CVHSUTsrLhd0g6enXEgT6j0TcJMSjVB1gNIEaI=; b=qKj2E1FsGMfkZiSmlYKNt6+8Yep1EC2LhIosEH+KLZUFT/jjWNSH2CNyUT1NjNDkiV viBTw8NDBB0CpsqAyu56NS2RD3caTTdNcp1WdRAeVByDIFLpANMy5hh9esCCxcjMrVYp h6OHXFXxms3xsJwysCQirX+t0lAgSUtCjikwie0zTPfdobt3mCPMzTCxC20d+USbjog8 splFuUdQ6DbKtCOjKwSwYi0v/AAQA9ZlnrT9bikI9x5QyBHOWHBdIFrrO6ZB239Wab4g yIJi3k84vkZl4wcs/MtvdWCadjnp1edwCzyk2kqwUijSghOFZciY6YYKUnRw8YyfEBY/ 5GVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gR7aFSjH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Date: Wed, 17 Feb 2021 12:19:57 -0800 Message-Id: <20210217202036.1724901-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Signed-off-by: Richard Henderson --- tcg/tci.c | 8 ++++---- tcg/tci/tcg-target.c.inc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 3ce2b72316..583059f319 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -838,7 +838,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_ld_i32: t0 = *tb_ptr++; taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i(&tb_ptr); + oi = tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 = qemu_ld_ub; @@ -875,7 +875,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t1 = *tb_ptr++; } taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i(&tb_ptr); + oi = tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 = qemu_ld_ub; @@ -924,7 +924,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_st_i32: t0 = tci_read_rval(regs, &tb_ptr); taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i(&tb_ptr); + oi = tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(t0); @@ -948,7 +948,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_st_i64: tmp64 = tci_read_r64(regs, &tb_ptr); taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i(&tb_ptr); + oi = tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 640407b4a8..6c187a25cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -550,7 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; case INDEX_op_qemu_ld_i64: @@ -563,7 +563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } - tcg_out_i(s, *args++); + tcg_out32(s, *args++); break; case INDEX_op_mb: From patchwork Wed Feb 17 20:19:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383894 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3133874jao; Wed, 17 Feb 2021 13:05:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJyXVG4vBJPXUe6U7EDe0GtUjxpZZLOQUuFPptY9FDcDlLJ/OLVSgWbHcFs5f9JtasQmaEF4 X-Received: by 2002:a25:4b02:: with SMTP id y2mr1940092yba.353.1613595905394; Wed, 17 Feb 2021 13:05:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595905; cv=none; d=google.com; s=arc-20160816; b=rU230MJSh52An7/DY7M0mPvAKs6Cl8U22Dmg5CPhqXmGoZSX1/zsdWiGuayW8Jbsz6 NWuPaF9rI5ZCSyj3DXazEjLzICU3+ZAqZFPaY0s84gTte5L6w1u1Dns/pCCDDKE9ZtuO fie8eQADbf+yfOj2JW5231pA+oMBfuJ/XJqoTon5pVVA6XsdgMwU3BW2e+e3m7LXA7SO 7m7dDZk9MTZLY+efDbKODPaQRDk3vR0SrFf99BsoELnTx0CyPahOQLKDAlE8rWmZPOcs 9uGBqfvb8h6bfJ4mhpA97bW+u+lPS0hM/6KCCtA7XVC308a3cP/BbjzrdmiDyzAN+rlf kkvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BGjOxn7oBYKM0brcxUQhOzUdPq+WpZr2L0yE6bqXqs8=; b=fJ8mmP0Fm+KvCkTA+KSuwJE5MBKmKe2LX+1qRbzsF9KkA1uGre/N7GGXNw+9RLwpIb 12LZSp5ag/FeNnExdaWbW7obkINwwyFXrIydczUK5c+IImQFyi2AekURuUJKdgxsz0dj OoZ2jX62GPi+lkv/Grivr/kVzLct8sLpd9d/stAkcxjHDxTg604uJp/6xJ5CVRUnSbMi 0mQ17RKLy07GQEhB/kPqsyu3/Imll8y4cao7mI2PDGKeTHZOrKsqGhPQ8a6QcEDT/7qW mrUfpQVv+7wJhl2r/+gGZD1VGSx9FGY20e32yvqrPyRLaMBH90K4wwvi50iD+XreO+Yw dbMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DkwnQBxw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Date: Wed, 17 Feb 2021 12:19:58 -0800 Message-Id: <20210217202036.1724901-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 81 insertions(+), 66 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 583059f319..f6cc5a3ab0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) regs[index] = value; } -#if TCG_TARGET_REG_BITS == 32 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#endif -#if TCG_TARGET_REG_BITS == 32 /* Create a 64 bit value from two 32 bit values. */ static uint64_t tci_uint64(uint32_t high, uint32_t low) { return ((uint64_t)high << 32) + low; } -#endif /* Read constant byte from bytecode. */ static uint8_t tci_read_b(const uint8_t **tb_ptr) @@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr) return value; } -/* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong -tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - tcg_target_ulong value = tci_read_reg(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - -#if TCG_TARGET_REG_BITS == 32 -/* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t low = tci_read_rval(regs, tb_ptr); - return tci_uint64(tci_read_rval(regs, tb_ptr), low); -} -#elif TCG_TARGET_REG_BITS == 64 -/* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - return tci_read_rval(regs, tb_ptr); -} -#endif - -/* Read indexed register(s) with target address from bytecode. */ -static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - target_ulong taddr = tci_read_rval(regs, tb_ptr); -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32; -#endif - return taddr; -} - static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { return tci_read_i(tb_ptr); @@ -171,6 +130,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * b = immediate (bit position) * i = immediate (uint32_t) * I = immediate (tcg_target_ulong) + * m = immediate (TCGMemOpIdx) * r = register * s = signed ldst offset */ @@ -203,6 +163,14 @@ static void tci_args_rI(const uint8_t **tb_ptr, } #endif +static void tci_args_rrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *m2 = tci_read_i32(tb_ptr); +} + static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { @@ -237,6 +205,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 = tci_read_b(tb_ptr); } +static void tci_args_rrrm(const uint8_t **tb_ptr, + TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *m3 = tci_read_i32(tb_ptr); +} + static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { @@ -247,6 +224,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, *i4 = tci_read_b(tb_ptr); } +static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *r3 = tci_read_r(tb_ptr); + *m4 = tci_read_i32(tb_ptr); +} + #if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -440,8 +427,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint8_t op_size = tb_ptr[1]; const uint8_t *old_code_ptr = tb_ptr; #endif - TCGReg r0, r1, r2; - tcg_target_ulong t0; + TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -449,7 +435,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 - TCGReg r3, r4, r5; + TCGReg r4, r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; @@ -836,9 +822,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; case INDEX_op_qemu_ld_i32: - t0 = *tb_ptr++; - taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr = regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr = tci_uint64(regs[r2], regs[r1]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp32 = qemu_ld_ub; @@ -867,15 +857,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp32); + regs[r0] = tmp32; break; + case INDEX_op_qemu_ld_i64: - t0 = *tb_ptr++; - if (TCG_TARGET_REG_BITS == 32) { - t1 = *tb_ptr++; + if (TCG_TARGET_REG_BITS == 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr = regs[r1]; + } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr = regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr = tci_uint64(regs[r3], regs[r2]); } - taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i32(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: tmp64 = qemu_ld_ub; @@ -916,39 +911,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, default: g_assert_not_reached(); } - tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS == 32) { - tci_write_reg(regs, t1, tmp64 >> 32); + tci_write_reg64(regs, r1, r0, tmp64); + } else { + regs[r0] = tmp64; } break; + case INDEX_op_qemu_st_i32: - t0 = tci_read_rval(regs, &tb_ptr); - taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i32(&tb_ptr); + if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr = regs[r1]; + } else { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr = tci_uint64(regs[r2], regs[r1]); + } + tmp32 = regs[r0]; switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: - qemu_st_b(t0); + qemu_st_b(tmp32); break; case MO_LEUW: - qemu_st_lew(t0); + qemu_st_lew(tmp32); break; case MO_LEUL: - qemu_st_lel(t0); + qemu_st_lel(tmp32); break; case MO_BEUW: - qemu_st_bew(t0); + qemu_st_bew(tmp32); break; case MO_BEUL: - qemu_st_bel(t0); + qemu_st_bel(tmp32); break; default: g_assert_not_reached(); } break; + case INDEX_op_qemu_st_i64: - tmp64 = tci_read_r64(regs, &tb_ptr); - taddr = tci_read_ulong(regs, &tb_ptr); - oi = tci_read_i32(&tb_ptr); + if (TCG_TARGET_REG_BITS == 64) { + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + taddr = regs[r1]; + tmp64 = regs[r0]; + } else { + if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + taddr = regs[r2]; + } else { + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + taddr = tci_uint64(regs[r3], regs[r2]); + } + tmp64 = tci_uint64(regs[r1], regs[r0]); + } switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: qemu_st_b(tmp64); @@ -975,6 +989,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, g_assert_not_reached(); } break; + case INDEX_op_mb: /* Ensure ordering for all kinds */ smp_mb(); From patchwork Wed Feb 17 20:19:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383891 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3131408jao; Wed, 17 Feb 2021 13:01:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJzmOmPT2YC6vvi+QVU+dc04fLV+jd3/r+4qcp9hmCk4pYMdRXowmcaDHPX3ofxjhoM8Anjt X-Received: by 2002:a25:dad7:: with SMTP id n206mr1749769ybf.249.1613595692363; Wed, 17 Feb 2021 13:01:32 -0800 (PST) ARC-Seal: i=1; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_* Date: Wed, 17 Feb 2021 12:19:59 -0800 Message-Id: <20210217202036.1724901-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Signed-off-by: Richard Henderson --- tcg/tci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 73 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index f6cc5a3ab0..6b63beea28 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -24,7 +24,7 @@ #if defined(CONFIG_DEBUG_TCG) # define tci_assert(cond) assert(cond) #else -# define tci_assert(cond) ((void)0) +# define tci_assert(cond) ((void)(cond)) #endif #include "qemu-common.h" @@ -135,146 +135,217 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * s = signed ldst offset */ +static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +{ + const uint8_t *old_code_ptr = start - 2; + uint8_t op_size = old_code_ptr[1]; + tci_assert(*tb_ptr == old_code_ptr + op_size); +} + static void tci_args_l(const uint8_t **tb_ptr, void **l0) { + const uint8_t *start = *tb_ptr; + *l0 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_ri(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *i1 = tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } #if TCG_TARGET_REG_BITS == 64 static void tci_args_rI(const uint8_t **tb_ptr, TCGReg *r0, tcg_target_ulong *i1) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *i1 = tci_read_i(tb_ptr); + + check_size(start, tb_ptr); } #endif static void tci_args_rrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *m2 = tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrs(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, int32_t *i2) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *i2 = tci_read_s32(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *c2 = tci_read_b(tb_ptr); *l3 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *c3 = tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *m3 = tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *i3 = tci_read_b(tb_ptr); *i4 = tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *r3 = tci_read_r(tb_ptr); *m4 = tci_read_i32(tb_ptr); + + check_size(start, tb_ptr); } #if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *r3 = tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *r3 = tci_read_r(tb_ptr); *c4 = tci_read_b(tb_ptr); *l5 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *r3 = tci_read_r(tb_ptr); *r4 = tci_read_r(tb_ptr); *c5 = tci_read_b(tb_ptr); + + check_size(start, tb_ptr); } static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { + const uint8_t *start = *tb_ptr; + *r0 = tci_read_r(tb_ptr); *r1 = tci_read_r(tb_ptr); *r2 = tci_read_r(tb_ptr); *r3 = tci_read_r(tb_ptr); *r4 = tci_read_r(tb_ptr); *r5 = tci_read_r(tb_ptr); + + check_size(start, tb_ptr); } #endif @@ -423,10 +494,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, for (;;) { TCGOpcode opc = tb_ptr[0]; -#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) - uint8_t op_size = tb_ptr[1]; - const uint8_t *old_code_ptr = tb_ptr; -#endif TCGReg r0, r1, r2, r3; tcg_target_ulong t1; TCGCond condition; @@ -476,7 +543,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = ptr; continue; case INDEX_op_setcond_i32: @@ -629,9 +695,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_brcond_i32: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare32(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = ptr; - continue; } break; #if TCG_TARGET_REG_BITS == 32 @@ -652,7 +716,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, T1 = tci_uint64(regs[r1], regs[r0]); T2 = tci_uint64(regs[r3], regs[r2]); if (tci_compare64(T1, T2, condition)) { - tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = ptr; continue; } @@ -786,9 +849,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); if (tci_compare64(regs[r0], regs[r1], condition)) { - tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = ptr; - continue; } break; case INDEX_op_ext32s_i64: @@ -817,9 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); - tci_assert(tb_ptr == old_code_ptr + op_size); tb_ptr = *(void **)ptr; - continue; + break; case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { @@ -997,6 +1057,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, default: g_assert_not_reached(); } - tci_assert(tb_ptr == old_code_ptr + op_size); } } From patchwork Wed Feb 17 20:20:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383872 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3122080jao; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 35/71] tcg/tci: Remove tci_disas Date: Wed, 17 Feb 2021 12:20:00 -0800 Message-Id: <20210217202036.1724901-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FUZZY_BITCOIN=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 -- tcg/tci/tcg-target.c.inc | 10 ---------- 2 files changed, 12 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9285c930a2..52af6d8bc5 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -163,8 +163,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 16 -void tci_disas(uint8_t opc); - #define HAVE_TCG_QEMU_TB_EXEC /* We could notice __i386__ or __s390x__ and reduce the barriers depending diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c187a25cc..7fb3b04eaf 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -253,16 +253,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return true; } -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) -/* Show current bytecode. Used by tcg interpreter. */ -void tci_disas(uint8_t opc) -{ - const TCGOpDef *def = &tcg_op_defs[opc]; - fprintf(stderr, "TCG %s %u, %u, %u\n", - def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); -} -#endif - /* Write value (native size). */ static void tcg_out_i(TCGContext *s, tcg_target_ulong v) { From patchwork Wed Feb 17 20:20:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383876 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3124347jao; Wed, 17 Feb 2021 12:48:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJwCivzcJ6j7T32Z4kn87IrBw9QfM4BG6L7yk4jqc6udVvfLYy7q+PUSp5wTB2UNOEQ+zY6B X-Received: by 2002:a25:50cd:: with SMTP id e196mr1936451ybb.51.1613594906694; Wed, 17 Feb 2021 12:48:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613594906; cv=none; d=google.com; s=arc-20160816; b=HiPpMLvHDh4ETgOz0OoFpWty6w5vDACQRO3O3TerB1nQ+yGW+QutcirqmTstmOS7Vk TU7ajb7RMGy/q978zEKQJWoH+Ji/wXhlP+b/O0wxc/Jqwunmu4S8JzZTpiffSbDpx2Px qZwOMEuu94AlR2a+Ww2lLxkw4hHJO/FmYgZrAY2v6RtAR4/0FY/OtPe9Gao0MG0jIhIe ttxTHqgXAyNcIZurjUKDu7D/Y1qimaHNa/cVqmebdOraFYUkrzV9MPMEzQlFM5Ux0l+R sWH+PzD8AzC1SG6v10iU9QnNWy9wh6qd6nzQVY8FGUmXC6fxaEh1wyNm06fpH1VMFZjd cs7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=myNnxOdd6aR6rNRnu4Iw7VN5PbwCEgYK5JJ5Ief1/yY=; b=M2RtG87u/hH8146QxkRE8LFjtvDOCTWylCD25XKaIZXyyqZjf/wLLdNxzb1dmjj/j0 A9iaRCaEX6fxSyNnasAOptb69uXCOjl6Dj5rb+CPk6Ls4Ft0ndHhN91ybQta+St8XA0W 7830UBQx7prQruUs93Bv9LMIcN1j2toTqi/Ap5WgGw64plCpiDLfAxzTQd0+mo5DRCv6 foZ2GRiSy4UYxyoZ0Aj3M43mXUOqehyT6TGS582ZU1AFx8QqAowVzpWxjSmbVy+1rL/9 7KBIUrYVIVj9CaP/HSh/Vo7sDR1YY+C0IJunDBaV6XH6MEK/ReL2cktbiOklZcxMpfq6 mGig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=knbUTgwt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 36/71] tcg/tci: Implement the disassembler properly Date: Wed, 17 Feb 2021 12:20:01 -0800 Message-Id: <20210217202036.1724901-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Signed-off-by: Richard Henderson --- meson.build | 2 +- include/tcg/tcg-opc.h | 2 - disas/tci.c | 61 --------- tcg/tci.c | 283 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+), 64 deletions(-) delete mode 100644 disas/tci.c -- 2.25.1 diff --git a/meson.build b/meson.build index a923f249d8..da225d68a7 100644 --- a/meson.build +++ b/meson.build @@ -1925,7 +1925,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.c', 'tcg/tci.c')) +specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c')) subdir('backends') subdir('disas') diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 900984c005..bbb0884af8 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interpreter. */ DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -#if TCG_TARGET_REG_BITS == 64 DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) #endif -#endif #undef TLADDR_ARGS #undef DATA64_ARGS diff --git a/disas/tci.c b/disas/tci.c deleted file mode 100644 index f1d6c6b469..0000000000 --- a/disas/tci.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Tiny Code Interpreter for QEMU - disassembler - * - * Copyright (c) 2011 Stefan Weil - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "disas/dis-asm.h" -#include "tcg/tcg.h" - -/* Disassemble TCI bytecode. */ -int print_insn_tci(bfd_vma addr, disassemble_info *info) -{ - int length; - uint8_t byte; - int status; - TCGOpcode op; - - status = info->read_memory_func(addr, &byte, 1, info); - if (status != 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op = byte; - - addr++; - status = info->read_memory_func(addr, &byte, 1, info); - if (status != 0) { - info->memory_error_func(status, addr, info); - return -1; - } - length = byte; - - if (op >= tcg_op_defs_max) { - info->fprintf_func(info->stream, "illegal opcode %d", op); - } else { - const TCGOpDef *def = &tcg_op_defs[op]; - int nb_oargs = def->nb_oargs; - int nb_iargs = def->nb_iargs; - int nb_cargs = def->nb_cargs; - /* TODO: Improve disassembler output. */ - info->fprintf_func(info->stream, "%s\to=%d i=%d c=%d", - def->name, nb_oargs, nb_iargs, nb_cargs); - } - - return length; -} diff --git a/tcg/tci.c b/tcg/tci.c index 6b63beea28..41d73edc3a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -1059,3 +1059,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } } } + +/* + * Disassembler that matches the interpreter + */ + +static const char *str_r(TCGReg r) +{ + static const char regs[TCG_TARGET_NB_REGS][4] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" + }; + + QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14); + QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15); + + assert((unsigned)r < TCG_TARGET_NB_REGS); + return regs[r]; +} + +static const char *str_c(TCGCond c) +{ + static const char cond[16][8] = { + [TCG_COND_NEVER] = "never", + [TCG_COND_ALWAYS] = "always", + [TCG_COND_EQ] = "eq", + [TCG_COND_NE] = "ne", + [TCG_COND_LT] = "lt", + [TCG_COND_GE] = "ge", + [TCG_COND_LE] = "le", + [TCG_COND_GT] = "gt", + [TCG_COND_LTU] = "ltu", + [TCG_COND_GEU] = "geu", + [TCG_COND_LEU] = "leu", + [TCG_COND_GTU] = "gtu", + }; + + assert((unsigned)c < ARRAY_SIZE(cond)); + assert(cond[c][0] != 0); + return cond[c]; +} + +/* Disassemble TCI bytecode. */ +int print_insn_tci(bfd_vma addr, disassemble_info *info) +{ + uint8_t buf[256]; + int length, status; + const TCGOpDef *def; + const char *op_name; + TCGOpcode op; + TCGReg r0, r1, r2, r3; +#if TCG_TARGET_REG_BITS == 32 + TCGReg r4, r5; +#endif + tcg_target_ulong i1; + int32_t s2; + TCGCond c; + TCGMemOpIdx oi; + uint8_t pos, len; + void *ptr; + const uint8_t *tb_ptr; + + status = info->read_memory_func(addr, buf, 2, info); + if (status != 0) { + info->memory_error_func(status, addr, info); + return -1; + } + op = buf[0]; + length = buf[1]; + + if (length < 2) { + info->fprintf_func(info->stream, "invalid length %d", length); + return 1; + } + + status = info->read_memory_func(addr + 2, buf + 2, length - 2, info); + if (status != 0) { + info->memory_error_func(status, addr + 2, info); + return -1; + } + + def = &tcg_op_defs[op]; + op_name = def->name; + tb_ptr = buf + 2; + + switch (op) { + case INDEX_op_br: + case INDEX_op_call: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + tci_args_l(&tb_ptr, &ptr); + info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), str_c(c), ptr); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); + break; + + case INDEX_op_tci_movi_i32: + tci_args_ri(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_tci_movi_i64: + tci_args_rI(&tb_ptr, &r0, &i1); + info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", + op_name, str_r(r0), i1); + break; +#endif + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i32: + case INDEX_op_st_i64: + tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + info->fprintf_func(info->stream, "%-12s %s,%s,%d", + op_name, str_r(r0), str_r(r1), s2); + break; + + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + tci_args_rr(&tb_ptr, &r0, &r1); + info->fprintf_func(info->stream, "%-12s %s,%s", + op_name, str_r(r0), str_r(r1)); + break; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + info->fprintf_func(info->stream, "%-12s %s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2)); + break; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); + break; + +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_setcond2_i32: + tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_c(c)); + break; + + case INDEX_op_brcond2_i32: + tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), str_c(c), ptr); + break; + + case INDEX_op_mulu2_i32: + tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3)); + break; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", + op_name, str_r(r0), str_r(r1), str_r(r2), + str_r(r3), str_r(r4), str_r(r5)); + break; +#endif + + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + len = DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + goto do_qemu_ldst; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + len = 1; + do_qemu_ldst: + len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); + switch (len) { + case 2: + tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%x", + op_name, str_r(r0), str_r(r1), oi); + break; + case 3: + tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), str_r(r2), oi); + break; + case 4: + tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3), oi); + break; + default: + g_assert_not_reached(); + } + break; + + default: + info->fprintf_func(info->stream, "illegal opcode %d", op); + break; + } + + return length; +} From patchwork Wed Feb 17 20:20:02 2021 Content-Type: text/plain; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 37/71] tcg: Build ffi data structures for helpers Date: Wed, 17 Feb 2021 12:20:02 -0800 Message-Id: <20210217202036.1724901-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly use libffi for tci, as that is the only portable way of calling arbitrary functions. Signed-off-by: Richard Henderson --- meson.build | 9 +- include/exec/helper-ffi.h | 115 +++++++++++++++++++++++++ include/exec/helper-tcg.h | 24 ++++-- target/hppa/helper.h | 2 + target/i386/ops_sse_header.h | 6 ++ target/m68k/helper.h | 1 + target/ppc/helper.h | 3 + tcg/tcg.c | 20 +++++ tests/docker/dockerfiles/fedora.docker | 1 + 9 files changed, 172 insertions(+), 9 deletions(-) create mode 100644 include/exec/helper-ffi.h -- 2.25.1 diff --git a/meson.build b/meson.build index da225d68a7..6d5d1b914b 100644 --- a/meson.build +++ b/meson.build @@ -1925,7 +1925,14 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg/tcg-op.c', 'tcg/tcg.c', )) -specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c')) + +if get_option('tcg_interpreter') + libffi = dependency('libffi', version: '>=3.0', + static: enable_static, method: 'pkg-config', + required: true) + specific_ss.add(libffi) + specific_ss.add(files('tcg/tci.c')) +endif subdir('backends') subdir('disas') diff --git a/include/exec/helper-ffi.h b/include/exec/helper-ffi.h new file mode 100644 index 0000000000..3af1065af3 --- /dev/null +++ b/include/exec/helper-ffi.h @@ -0,0 +1,115 @@ +/* + * Helper file for declaring TCG helper functions. + * This one defines data structures private to tcg.c. + */ + +#ifndef HELPER_FFI_H +#define HELPER_FFI_H 1 + +#include "exec/helper-head.h" + +#define dh_ffitype_i32 &ffi_type_uint32 +#define dh_ffitype_s32 &ffi_type_sint32 +#define dh_ffitype_int &ffi_type_sint +#define dh_ffitype_i64 &ffi_type_uint64 +#define dh_ffitype_s64 &ffi_type_sint64 +#define dh_ffitype_f16 &ffi_type_uint32 +#define dh_ffitype_f32 &ffi_type_uint32 +#define dh_ffitype_f64 &ffi_type_uint64 +#ifdef TARGET_LONG_BITS +# if TARGET_LONG_BITS == 32 +# define dh_ffitype_tl &ffi_type_uint32 +# else +# define dh_ffitype_tl &ffi_type_uint64 +# endif +#endif +#define dh_ffitype_ptr &ffi_type_pointer +#define dh_ffitype_cptr &ffi_type_pointer +#define dh_ffitype_void &ffi_type_void +#define dh_ffitype_noreturn &ffi_type_void +#define dh_ffitype_env &ffi_type_pointer +#define dh_ffitype(t) glue(dh_ffitype_, t) + +#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 0, \ + }; + +#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ + static ffi_type *glue(cif_args_,NAME)[1] = { dh_ffitype(t1) }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 1, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ + static ffi_type *glue(cif_args_,NAME)[2] = { \ + dh_ffitype(t1), dh_ffitype(t2) \ + }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 2, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ + static ffi_type *glue(cif_args_,NAME)[3] = { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3) \ + }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 3, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ + static ffi_type *glue(cif_args_,NAME)[4] = { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), dh_ffitype(t4) \ + }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 4, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ + static ffi_type *glue(cif_args_,NAME)[5] = { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5) \ + }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 5, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + static ffi_type *glue(cif_args_,NAME)[6] = { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6) \ + }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 6, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ + static ffi_type *glue(cif_args_,NAME)[7] = { \ + dh_ffitype(t1), dh_ffitype(t2), dh_ffitype(t3), \ + dh_ffitype(t4), dh_ffitype(t5), dh_ffitype(t6), dh_ffitype(t7) \ + }; \ + static ffi_cif glue(cif_,NAME) = { \ + .rtype = dh_ffitype(ret), .nargs = 7, \ + .arg_types = glue(cif_args_,NAME), \ + }; + +#include "helper.h" +#include "trace/generated-helpers.h" +#include "tcg-runtime.h" + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 + +#endif /* HELPER_FFI_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index 27870509a2..a71b848576 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -10,50 +10,57 @@ to get all the macros expanded first. */ #define str(s) #s +#ifdef CONFIG_TCG_INTERPRETER +# define DO_CIF(NAME) .cif = &cif_##NAME, +#else +# define DO_CIF(NAME) +#endif + #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) }, #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, #define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func = HELPER(NAME), .name = str(NAME), \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, #define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), DO_CIF(NAME) .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) | dh_sizemask(t7, 7) }, @@ -64,6 +71,7 @@ #include "plugin-helpers.h" #undef str +#undef DO_CIF #undef DEF_HELPER_FLAGS_0 #undef DEF_HELPER_FLAGS_1 #undef DEF_HELPER_FLAGS_2 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 2d483aab58..35c612f09d 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,9 +1,11 @@ #if TARGET_REGISTER_BITS == 64 # define dh_alias_tr i64 # define dh_is_64bit_tr 1 +# define dh_ffitype_tr dh_ffitype_i64 #else # define dh_alias_tr i32 # define dh_is_64bit_tr 0 +# define dh_ffitype_tr dh_ffitype_i32 #endif #define dh_ctype_tr target_ureg #define dh_is_signed_tr 0 diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h index 6c0c849347..cae50f77eb 100644 --- a/target/i386/ops_sse_header.h +++ b/target/i386/ops_sse_header.h @@ -27,13 +27,19 @@ #define dh_alias_Reg ptr #define dh_alias_ZMMReg ptr #define dh_alias_MMXReg ptr + #define dh_ctype_Reg Reg * #define dh_ctype_ZMMReg ZMMReg * #define dh_ctype_MMXReg MMXReg * + #define dh_is_signed_Reg dh_is_signed_ptr #define dh_is_signed_ZMMReg dh_is_signed_ptr #define dh_is_signed_MMXReg dh_is_signed_ptr +#define dh_ffitype_Reg dh_ffitype_ptr +#define dh_ffitype_ZMMReg dh_ffitype_ptr +#define dh_ffitype_MMXReg dh_ffitype_ptr + DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg) DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 77808497a9..672c99d5de 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) #define dh_alias_fp ptr #define dh_ctype_fp FPReg * #define dh_is_signed_fp dh_is_signed_ptr +#define dh_ffitype_fp dh_ffitype_ptr DEF_HELPER_3(exts32, void, env, fp, s32) DEF_HELPER_3(extf32, void, env, fp, f32) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..bbd4700064 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -108,10 +108,12 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * #define dh_is_signed_avr dh_is_signed_ptr +#define dh_ffitype_avr dh_ffitype_ptr #define dh_alias_vsr ptr #define dh_ctype_vsr ppc_vsr_t * #define dh_is_signed_vsr dh_is_signed_ptr +#define dh_ffitype_vsr dh_ffitype_ptr DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) @@ -696,6 +698,7 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl) #define dh_alias_fprp ptr #define dh_ctype_fprp ppc_fprp_t * #define dh_is_signed_fprp dh_is_signed_ptr +#define dh_ffitype_fprp dh_ffitype_ptr DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp) DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2991112829..6382112215 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -66,6 +66,10 @@ #include "exec/log.h" #include "sysemu/sysemu.h" +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); @@ -1082,6 +1086,9 @@ void tcg_pool_reset(TCGContext *s) typedef struct TCGHelperInfo { void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif const char *name; unsigned flags; unsigned sizemask; @@ -1089,6 +1096,10 @@ typedef struct TCGHelperInfo { #include "exec/helper-proto.h" +#ifdef CONFIG_TCG_INTERPRETER +#include "exec/helper-ffi.h" +#endif + static const TCGHelperInfo all_helpers[] = { #include "exec/helper-tcg.h" }; @@ -1136,6 +1147,15 @@ void tcg_context_init(TCGContext *s) (gpointer)&all_helpers[i]); } +#ifdef CONFIG_TCG_INTERPRETER + for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { + ffi_cif *cif = all_helpers[i].cif; + ffi_status ok = ffi_prep_cif(cif, FFI_DEFAULT_ABI, cif->nargs, + cif->rtype, cif->arg_types); + tcg_debug_assert(ok == FFI_OK); + } +#endif + tcg_target_init(s); process_op_defs(s); diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 0d7602abbe..45fc1a77bd 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -32,6 +32,7 @@ ENV PACKAGES \ libcurl-devel \ libepoxy-devel \ libfdt-devel \ + libffi-devel \ libiscsi-devel \ libjpeg-devel \ libpmem-devel \ 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 38/71] tcg/tci: Use ffi for calls Date: Wed, 17 Feb 2021 12:20:03 -0800 Message-Id: <20210217202036.1724901-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 72 ++++++++++++-------- tcg/tci.c | 138 +++++++++++++++++++++++---------------- tcg/tci/tcg-target.c.inc | 50 +++++++------- 5 files changed, 150 insertions(+), 113 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0f0695e90d..e5573a9877 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -53,6 +53,7 @@ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) #define CPU_TEMP_BUF_NLONGS 128 +#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) /* Default target word size to pointer size. */ #ifndef TCG_TARGET_REG_BITS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 52af6d8bc5..4df10e2e83 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,7 +161,7 @@ typedef enum { /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 -#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_STACK_ALIGN 8 #define HAVE_TCG_QEMU_TB_EXEC diff --git a/tcg/tcg.c b/tcg/tcg.c index 6382112215..92aec0d238 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -208,6 +208,18 @@ static size_t tree_size; static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; +typedef struct TCGHelperInfo { + void *func; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif + const char *name; + unsigned flags; + unsigned sizemask; +} TCGHelperInfo; + +static GHashTable *helper_table; + #if TCG_TARGET_INSN_UNIT_SIZE == 1 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) { @@ -1084,16 +1096,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current = NULL; } -typedef struct TCGHelperInfo { - void *func; -#ifdef CONFIG_TCG_INTERPRETER - ffi_cif *cif; -#endif - const char *name; - unsigned flags; - unsigned sizemask; -} TCGHelperInfo; - #include "exec/helper-proto.h" #ifdef CONFIG_TCG_INTERPRETER @@ -1103,7 +1105,6 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] = { #include "exec/helper-tcg.h" }; -static GHashTable *helper_table; static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; static void process_op_defs(TCGContext *s); @@ -2081,25 +2082,38 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args = 0; for (i = 0; i < nargs; i++) { - int is_64bit = sizemask & (1 << (i+1)*2); - if (TCG_TARGET_REG_BITS < 64 && is_64bit) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - /* some targets want aligned 64 bit args */ - if (real_args & 1) { - op->args[pi++] = TCG_CALL_DUMMY_ARG; - real_args++; - } + bool is_64bit = sizemask & (1 << (i+1)*2); + bool want_align = false; + +#if defined(CONFIG_TCG_INTERPRETER) + /* + * Align all arguments, so that they land in predictable places + * for passing off to ffi_call. + */ + want_align = true; +#elif defined(TCG_TARGET_CALL_ALIGN_ARGS) + /* Some targets want aligned 64 bit args */ + want_align = is_64bit; #endif - /* If stack grows up, then we will be placing successive - arguments at lower addresses, which means we need to - reverse the order compared to how we would normally - treat either big or little-endian. For those arguments - that will wind up in registers, this still works for - HPPA (the only current STACK_GROWSUP target) since the - argument registers are *also* allocated in decreasing - order. If another such target is added, this logic may - have to get more complicated to differentiate between - stack arguments and register arguments. */ + + if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { + op->args[pi++] = TCG_CALL_DUMMY_ARG; + real_args++; + } + + if (TCG_TARGET_REG_BITS < 64 && is_64bit) { + /* + * If stack grows up, then we will be placing successive + * arguments at lower addresses, which means we need to + * reverse the order compared to how we would normally + * treat either big or little-endian. For those arguments + * that will wind up in registers, this still works for + * HPPA (the only current STACK_GROWSUP target) since the + * argument registers are *also* allocated in decreasing + * order. If another such target is added, this logic may + * have to get more complicated to differentiate between + * stack arguments and register arguments. + */ #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP) op->args[pi++] = temp_arg(args[i] + 1); op->args[pi++] = temp_arg(args[i]); diff --git a/tcg/tci.c b/tcg/tci.c index 41d73edc3a..5718fc42a6 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,6 +18,13 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" +#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ +#include "exec/cpu_ldst.h" +#include "tcg/tcg-op.h" +#include "qemu/compiler.h" +#include + /* Enable TCI assertions only when debugging TCG (and without NDEBUG defined). * Without assertions, the interpreter runs much faster. */ @@ -27,36 +34,8 @@ # define tci_assert(cond) ((void)(cond)) #endif -#include "qemu-common.h" -#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" -#include "qemu/compiler.h" - -#if MAX_OPC_PARAM_IARGS != 6 -# error Fix needed, number of supported input arguments changed! -#endif -#if TCG_TARGET_REG_BITS == 32 -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#else -typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong, tcg_target_ulong); -#endif - __thread uintptr_t tci_tb_ptr; -static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - return regs[index]; -} - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -131,6 +110,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * i = immediate (uint32_t) * I = immediate (tcg_target_ulong) * m = immediate (TCGMemOpIdx) + * n = immediate (call return length) * r = register * s = signed ldst offset */ @@ -151,6 +131,16 @@ static void tci_args_l(const uint8_t **tb_ptr, void **l0) check_size(start, tb_ptr); } +static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +{ + const uint8_t *start = *tb_ptr; + + *n0 = tci_read_b(tb_ptr); + *l1 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -474,6 +464,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) # define CASE_64(x) #endif + /* Interpret pseudo code in tb. */ /* * Disable CFI checks. @@ -485,11 +476,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, { const uint8_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; - long tcg_temps[CPU_TEMP_BUF_NLONGS]; - uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); + uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) + / sizeof(uint64_t)]; + void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; regs[TCG_AREG0] = (tcg_target_ulong)env; - regs[TCG_REG_CALL_STACK] = sp_value; + regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; + call_slots[0] = NULL; tci_assert(tb_ptr); for (;;) { @@ -514,33 +507,60 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, switch (opc) { case INDEX_op_call: - tci_args_l(&tb_ptr, &ptr); + /* + * We are passed a pointer to the TCGHelperInfo, which contains + * the function pointer followed by the ffi_cif pointer. + */ + tci_args_nl(&tb_ptr, &len, &ptr); + + /* Helper functions may need to access the "return address" */ tci_tb_ptr = (uintptr_t)tb_ptr; -#if TCG_TARGET_REG_BITS == 32 - tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5), - tci_read_reg(regs, TCG_REG_R6), - tci_read_reg(regs, TCG_REG_R7), - tci_read_reg(regs, TCG_REG_R8), - tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10), - tci_read_reg(regs, TCG_REG_R11)); - tci_write_reg(regs, TCG_REG_R0, tmp64); - tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); -#else - tmp64 = ((helper_function)ptr)(tci_read_reg(regs, TCG_REG_R0), - tci_read_reg(regs, TCG_REG_R1), - tci_read_reg(regs, TCG_REG_R2), - tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R4), - tci_read_reg(regs, TCG_REG_R5)); - tci_write_reg(regs, TCG_REG_R0, tmp64); -#endif + + /* + * Set up the ffi_avalue array once, delayed until now + * because many TB's do not make any calls. In tcg_gen_callN, + * we arranged for every real argument to be "left-aligned" + * in each 64-bit slot. + */ + if (call_slots[0] == NULL) { + for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) { + call_slots[i] = &stack[i]; + } + } + + /* + * Call the helper function. Any result winds up + * "left-aligned" in the stack[0] slot. + */ + { + void **pptr = ptr; + ffi_call(pptr[1], pptr[0], stack, call_slots); + } + switch (len) { + case 0: /* void */ + break; + case 1: /* uint32_t */ + /* + * Note that libffi has an odd special case in that it will + * always widen an integral result to ffi_arg. + */ + if (sizeof(ffi_arg) == 4) { + regs[TCG_REG_R0] = *(uint32_t *)stack; + break; + } + /* fall through */ + case 2: /* uint64_t */ + if (TCG_TARGET_REG_BITS == 32) { + tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]); + } else { + regs[TCG_REG_R0] = stack[0]; + } + break; + default: + g_assert_not_reached(); + } break; + case INDEX_op_br: tci_args_l(&tb_ptr, &ptr); tb_ptr = ptr; @@ -1145,13 +1165,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) switch (op) { case INDEX_op_br: - case INDEX_op_call: case INDEX_op_exit_tb: case INDEX_op_goto_tb: tci_args_l(&tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; + case INDEX_op_call: + tci_args_nl(&tb_ptr, &len, &ptr); + info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr); + break; + case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7fb3b04eaf..8d75482546 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -192,23 +192,8 @@ static const int tcg_target_reg_alloc_order[] = { # error Fix needed, number of supported input arguments changed! #endif -static const int tcg_target_call_iarg_regs[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, -#if TCG_TARGET_REG_BITS == 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, -#endif -}; +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] = { }; static const int tcg_target_call_oarg_regs[] = { TCG_REG_R0, @@ -292,8 +277,9 @@ static void tci_out_label(TCGContext *s, TCGLabel *label) static void stack_bounds_check(TCGReg base, target_long offset) { if (base == TCG_REG_CALL_STACK) { - tcg_debug_assert(offset < 0); - tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long))); + tcg_debug_assert(offset >= 0); + tcg_debug_assert(offset < (TCG_STATIC_CALL_ARGS_SIZE + + TCG_STATIC_FRAME_SIZE)); } } @@ -360,11 +346,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr = s->code_ptr; + const TCGHelperInfo *info; + uint8_t which; + + info = g_hash_table_lookup(helper_table, (gpointer)arg); + if (info->cif->rtype == &ffi_type_void) { + which = 0; + } else if (info->cif->rtype->size == 4) { + which = 1; + } else { + tcg_debug_assert(info->cif->rtype->size == 8); + which = 2; + } tcg_out_op_t(s, INDEX_op_call); - tcg_out_i(s, (uintptr_t)arg); + tcg_out8(s, which); + tcg_out_i(s, (uintptr_t)info); + old_code_ptr[1] = s->code_ptr - old_code_ptr; } @@ -629,11 +629,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - /* We use negative offsets from "sp" so that we can distinguish - stores that might pretend to be call arguments. */ - tcg_set_frame(s, TCG_REG_CALL_STACK, - -CPU_TEMP_BUF_NLONGS * sizeof(long), - CPU_TEMP_BUF_NLONGS * sizeof(long)); + /* The call arguments come first, followed by the temp storage. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + TCG_STATIC_FRAME_SIZE); } /* Generate global QEMU prologue and epilogue code. */ From patchwork Wed Feb 17 20:20:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383902 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3137189jao; Wed, 17 Feb 2021 13:10:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJxYR8Odm44otI1d6OE3ZSfIl2CXiqBkfpAWQ3faxW45egw/rPdBKQvh2ENBk5hp+b/2Trqi X-Received: by 2002:a25:c381:: with SMTP id t123mr1935168ybf.299.1613596212559; Wed, 17 Feb 2021 13:10:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596212; cv=none; d=google.com; s=arc-20160816; b=PLmmR0D/0BHiD64IxcYh3OswHjEZl0dEQM12fXG02OkbGpTc0rAVW8ZsSMyCDOa1Wp wEAiGaCi+aLQ2YDKMHTmvSb90kMmITzy19/G1BTMBUyXRKkBT+KqNksWslUNmW6jfjwt 9rChT1Wrt9oc9XcRA0aifSLRofPB9UVXeNg3Jbsx8AS09sKjh8kj6AjhcJecmmW2biWv yeip8qEkjgjfMJduyh5fprLSd018wY1CSRlMqrd5bbUgsnE94fWH86Z4vzgOiaomGq4B /8OAR5n0fhlJ3T2OIrsZYi357MLNGbEhcBCCP5rZGQvpDkiEwuPWTuCzkwDYBR/Z0dkZ vTPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YQBNB7jLXwaZJSYBL0BvoU6n3wPE6zwxayv+Hpeg13U=; b=iSs57dyTCURSxFeXZx6I18cjYe3tFEqdWu9tcGsqNMYUgSS/N9DwcfZEiYtJ/EBnmE jHHoMT1JGXvYs42tBDy022eWgtNVl/bH2cnWs2yDAmk+6E8cCN4+KBic2B4VORr/LAis 2tBVWiuMifD+9KmR1hitdy1r0EvdbJ8vDibj8LdjiSL0XAb8fcelXP2fUkvygDb4Ag/f /mq2fc3cVB6TSL3WC2J+JUnG1O0KAJiQTtopfRXQHQK7dE78LOA9lIHv4jO3DMuUg3N4 kwEWTGKChzn8OuXArFhYi6sKkPP69pwBAOmt6pnpu1MkiAJ5hAxjEqJGp/sJQ84ceeHf /3yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CrIcLrHZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs Date: Wed, 17 Feb 2021 12:20:04 -0800 Message-Id: <20210217202036.1724901-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The current setting is much too pessimistic. Indicating only the one or two registers that are actually assigned after a call should avoid unnecessary movement between the register array and the stack array. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8d75482546..4dae09deda 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -623,8 +623,14 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; /* Registers available for 64 bit operations. */ tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; - /* TODO: Which registers should be set here? */ - tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; + /* + * The interpreter "registers" are in the local stack frame and + * cannot be clobbered by the called helper functions. However, + * the interpreter assumes a 64-bit return value and assigns to + * the return value registers. + */ + tcg_target_call_clobber_regs = + MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); From patchwork Wed Feb 17 20:20:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383899 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3136335jao; Wed, 17 Feb 2021 13:08:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJyOdkU44xpnkrvrcGekqXrfari76/HOxKwbEdxv32smCq23Szvj1v016qfH5OYmsUiMinTM X-Received: by 2002:a25:824c:: with SMTP id d12mr2027462ybn.137.1613596127617; Wed, 17 Feb 2021 13:08:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596127; cv=none; d=google.com; s=arc-20160816; b=dnv0JiQsn+TyuIrvTLeONoxLP+By+1uFRA6NQk24PnCHz+Jqn/TTTjPksbITeZlpNb vZwF7rLS7Tv6yQqaeFFMKJi4xgjkr/EZdq8Sn5ZWnh9lD5Swuvzv+HVkxRaQPkiNtJKD WhEinWpFsY/t5vMMBE3p1v1CxhUp3kMgROYf4h8oHxo/35eLHZScGnIk1WqiWoNujH2P dsO/fAYwhC0w0GT0kzI557de8r5DTtEozonaiighS3HSaOMLoJj5vUSu7r4nGO5TJ8yn vt/m8UBdjGMs4KLls0KYfz8foaVwJgZ2lu/jYU8UkNtQGQhPmGCKkfPHLY4hCxUI9jeN 1SNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LAWykP8xawhD0n2LEjnvxt6U+It9ZnMCGaTxxtC6jn0=; b=X7LH3mB75unofgKIpIE4eZVk12UUccZCLp5njT4jLoVcuBb/NrhZ5SNiFMXFiwjqbO Y1BDRkDOJGOy5LZPfwuDpJ0BFZjhpbvBWTq/dFBD8Yzic5mSjNbktocNaM7GziR2J8Zo CYnlMztamSXqGCM8q7ocMF4GnOwtrjYzhonDmQR4gLN5/f9R5fPeX5tJfOeMovQZdlpt 8bLM2tXB6EUa34zVYbAJeDqDVXb1DKOoM7LA5ke8h/ugqQCYK5BabQym+xBCFvHmvS97 FUuDEfCEMyqD+1hZoOORakgo73idlaiVn9d1JlKbyW978N69ySUuTOACHz/30vOoe3Nr Btkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="RF/wS19O"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Date: Wed, 17 Feb 2021 12:20:05 -0800 Message-Id: <20210217202036.1724901-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the only call-clobbered regs for TCI, these should receive the least priority. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4dae09deda..53edc50a3b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) } static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, TCG_REG_R4, @@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R1, + TCG_REG_R0, }; #if MAX_OPC_PARAM_IARGS != 6 From patchwork Wed Feb 17 20:20:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383882 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3127095jao; Wed, 17 Feb 2021 12:53:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJwDzQIMeE4TM2Ci6F12Sgh1+4NJkNAXY4uRR0FEhmPV4XSW//wldkNgnFrwjIha/t4C6VKH X-Received: by 2002:a25:2f43:: with SMTP id v64mr1893178ybv.302.1613595218584; Wed, 17 Feb 2021 12:53:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595218; cv=none; d=google.com; s=arc-20160816; b=xZK2yDnu6dCieCUUQoiOUJeRAiyjO1BtWkK8PWGI0qH3Pw5nHVg1EG042lgscv9Hn9 OA2AFofwvaHphXapeulS9RWoMdYLut+1GGTpKjS3VIHtO3iiPn5a8/mnJtADlmzkJTBG ik5cQ2WO6ZBGQwZ2ZSKWZSmLtSRu/YxHveqMWhr5DE+LM5gC4rIFtZukpO3FN9Cu4NMk zGrjMOBLnFOf6DyshQZvK07HUzPGTfm2/FUluGRVSI/TrBBoHEpsVHwF/o3JKsVJmiEf 9KvkTg9hfGpu1Maho4zSIztM5cbwCw7+LAd6xbdVDiLJ71S/JrBAs1zdoupPaCCDyl8q bQ3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=akuogNqTsRbdFKyineyOU7+0wNNNt+eZ2/k7lVk1LqY=; b=UIohnAmde2unUC0vwB0pYcoiqn8FM0Juxv+k+FIeZ7EO8iosC3Rg1ZfBd3ibSlBQj7 te8oWPoJpJkyaxvg99zHRTPHDNPsJQQIhBzkBepnbeHdr/o+6EqrczarE+ZOik7F7d7M 2/j2Yav4z/5g9KYjK8PnNuJMHqueoK1LI0v+v7h3Ppj9md6S0aIBuA17lUycw3j/FHU1 aVpLJcWZ1CkHYGp8yS2L3ZniZcRoNLuBM+iO1x5TUqVtGFtc6uMeWNDsXZ1i/OFetzg6 WAwMmun7/vhOv7PH3SonuvpSK6tVwsJ+3jnvoinFqtvkTRDkQ8rlUA355qa54HpsClN8 u9tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=raMcAiBm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 41/71] tcg/tci: Push opcode emit into each case Date: Wed, 17 Feb 2021 12:20:06 -0800 Message-Id: <20210217202036.1724901-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 53edc50a3b..050d514853 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,40 +385,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, { uint8_t *old_code_ptr = s->code_ptr; - tcg_out_op_t(s, opc); - switch (opc) { case INDEX_op_exit_tb: + tcg_out_op_t(s, opc); tcg_out_i(s, args[0]); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset == 0); /* indirect jump method. */ + tcg_out_op_t(s, opc); tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); + old_code_ptr[1] = s->code_ptr - old_code_ptr; set_jmp_reset_offset(s, args[0]); break; case INDEX_op_br: + tcg_out_op_t(s, opc); tci_out_label(s, arg_label(args[0])); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; CASE_32_64(setcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; #endif @@ -436,10 +444,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_debug_assert(args[2] == (int32_t)args[2]); tcg_out32(s, args[2]); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; CASE_32_64(add) @@ -462,12 +472,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ + tcg_out_op_t(s, opc); { TCGArg pos = args[3], len = args[4]; TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64; @@ -481,13 +494,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out8(s, pos); tcg_out8(s, len); } + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; CASE_32_64(brcond) + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -503,48 +519,59 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out_r(s, args[4]); tcg_out_r(s, args[5]); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_brcond2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out_r(s, args[3]); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; #endif case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); tcg_out_r(s, *args++); if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: + tcg_out_op_t(s, opc); tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS == 32) { tcg_out_r(s, *args++); @@ -554,9 +581,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, *args++); } tcg_out32(s, *args++); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_mb: + tcg_out_op_t(s, opc); + old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ @@ -565,7 +595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, default: tcg_abort(); } - old_code_ptr[1] = s->code_ptr - old_code_ptr; } static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, From patchwork Wed Feb 17 20:20:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383880 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3126341jao; Wed, 17 Feb 2021 12:52:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJz2Y+w9AfhxCHjDFcVeuVeyIMdNLhn7qNNWPv1mCe+O4OhrnbV0wGHhw7KrcH4b5qHpP6su X-Received: by 2002:a25:c7c6:: with SMTP id w189mr1735454ybe.323.1613595133543; Wed, 17 Feb 2021 12:52:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595133; cv=none; d=google.com; s=arc-20160816; b=BFVsk2SUdrVBusATKjH/G1rPLGx8RwJCK4fwxXpRkIGNu7fB32Fjboq8FKBVtv9G5g 0RBwl+2IDWXwysUGWReyWA+XqVncTakWas+UBhuCUReHTP98RzCt1GAKCIXkkSbMOt79 xUbjD06e888chHaqL5u9bgPVBeBnU5UxeHQAvlkcOAIeKuqg6TMtHhr3S8VyXraYUqKz Rjf0Y8EpJMkUFFG4/ZAFWg9/G8SN8dU4M9P2g5ykHwg+WDsDetToG8bdcT+/sij3MZI8 vwC9PRNPazTHVJGPZozGjbjndCJzkQ105n2W5ZjRlg3d+kVWqn0gfOm+NsL4JvrS69H9 dYug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r51gde6XQroUTuOp18Wacrk/m6aRKZagEOpI8SD7K0E=; b=G8Yc+6blneTCZYwTlpftxE/wp9jfzvy4u43Zwhy2yEEwIBde+ET3qe/0hCmcAoUjKy izS2wotXb+5e5IPnop89ERPhliy1hGj0luw4nvvszVQ1m6/ZdmbenPYMAvTYyUAX10F4 u5o5yhEgO8f0VvfHqixUbKiuCM/QTf2uslc4ZvV0HLkuf1YR7PPj3a4N7/KJkuVPhflX Q7I4ZTpw82s6mZf5EJWDq9lRKYPistxXqSnCUIATmYJiP5znvpfEOrnkUn/ByVi6gt5f tX8y/26P+fK6+Bw10CQrQz+Ur7bCAgUYEPtZKgjVol1Myg/OpVOwfG4KI3NKddOuV8Ft XkJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gMJKM5xx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 42/71] tcg/tci: Split out tcg_out_op_rrs Date: Wed, 17 Feb 2021 12:20:07 -0800 Message-Id: <20210217202036.1724901-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 84 +++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 050d514853..707f801099 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,32 +283,38 @@ static void stack_bounds_check(TCGReg base, target_long offset) } } -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, - intptr_t arg2) +static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, intptr_t i2) { uint8_t *old_code_ptr = s->code_ptr; - stack_bounds_check(arg1, arg2); - if (type == TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_ld_i32); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type == TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_ld_i64); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_debug_assert(arg2 == (int32_t)arg2); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_debug_assert(i2 == (int32_t)i2); + tcg_out32(s, i2); + old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, + intptr_t offset) +{ + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + break; +#if TCG_TARGET_REG_BITS == 64 + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + break; +#endif + default: + g_assert_not_reached(); + } +} + static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { uint8_t *old_code_ptr = s->code_ptr; @@ -444,12 +450,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_64(st32) CASE_64(st) stack_bounds_check(args[1], args[2]); - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_debug_assert(args[2] == (int32_t)args[2]); - tcg_out32(s, args[2]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); break; CASE_32_64(add) @@ -597,29 +598,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } } -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, - intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base, + intptr_t offset) { - uint8_t *old_code_ptr = s->code_ptr; - - stack_bounds_check(arg1, arg2); - if (type == TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_st_i32); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type == TCG_TYPE_I64); + stack_bounds_check(base, offset); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); + break; #if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_st_i64); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] = s->code_ptr - old_code_ptr; } static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, From patchwork Wed Feb 17 20:20:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383886 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3128997jao; Wed, 17 Feb 2021 12:57:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwq5uPGC98/teXw8q6xXbGckcdzp19eJ+FncjbXtWy0E3KXAGzVhfF8CGX79EvYnPqafToY X-Received: by 2002:a25:40d8:: with SMTP id n207mr1841381yba.3.1613595434877; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 43/71] tcg/tci: Split out tcg_out_op_l Date: Wed, 17 Feb 2021 12:20:08 -0800 Message-Id: <20210217202036.1724901-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 707f801099..1e3f2c4049 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -283,6 +283,16 @@ static void stack_bounds_check(TCGReg base, target_long offset) } } +static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tci_out_label(s, l0); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -408,9 +418,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_br: - tcg_out_op_t(s, opc); - tci_out_label(s, arg_label(args[0])); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_l(s, opc, arg_label(args[0])); break; CASE_32_64(setcond) From patchwork Wed Feb 17 20:20:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383884 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3127364jao; Wed, 17 Feb 2021 12:54:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJzXkDT1KpkdOd241DLKvQNfXW9hxlY0r5Q+xMfYbTUhEqLQuUy4/Us0VzQTvbY9sx+Pja1P X-Received: by 2002:a25:cb41:: with SMTP id b62mr1808581ybg.284.1613595245561; Wed, 17 Feb 2021 12:54:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595245; cv=none; d=google.com; s=arc-20160816; b=UIdgr4CcxjsbJQisMK2anNj7eAsFTN6YPfduIZtYnS4ZFHbdSnXTZ9NyIrjqQBNtUv zVoE0RsyOJrgbW61PpcIeDwQeuct1x5UcPkREU1rTfxoyEwPexuWSmtDYq15GY7QYgKc qiXveif/YSb61NfkHHVJBYbWzuTNJ8Rw3BKmaPJylwQa6Z3jlAj84fteVegwhCDCmtGK noJKV23j9Q5+1Fk08dSfh1BeJ5ZVVrCe14OaGI3As8naBuZO9Bv0uE/wbxc/2fbgyOwM aClC2hxPsEyTkAkXHFSQHzwLySsb1fYWRIoqr1/FtqEPqdyvgKVZUMHuOoFZ+ejLOHUh LMPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=06Y+cyMxl+dC1AQMaIsueXy7S/PiohsOvXqBqGkx3uw=; b=vDo72oFXuZhSRWFQmW0qPhapK2uEbYl3MFEdhPtIltWnXyLDgQDi1aw7YjYr6n8NIv 8trS6hEfmifnRUFReRqpD+7y8kUZClhaqZNK1PeWGCQJgMr7c0qoybEsnCQfOTsutgzU 6M9eW7F5+z1oEZdqwnP0IR+K4PBr3a40XTzj2Q1qdioP4Qg79SpPqpLI4j0BOiQ+/Ce0 L7/gLhF9fpOrR8sdmZ2CAFAEod5H8AxWS5fQHHtG7obFwDvJDIshGh2Vks6oDLC0Br9t WVZI/6iCXTP8c27ZCujo31RVOybz/p5Fh8RiaxM98EXi6U1YSWrWOfjCj7xm7QzeOZQ8 tONQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=H4TMAZoX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 44/71] tcg/tci: Split out tcg_out_op_p Date: Wed, 17 Feb 2021 12:20:09 -0800 Message-Id: <20210217202036.1724901-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1e3f2c4049..cb0cbbb8da 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -293,6 +293,16 @@ static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_i(s, (uintptr_t)p0); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -403,17 +413,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: - tcg_out_op_t(s, opc); - tcg_out_i(s, args[0]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, (void *)args[0]); break; case INDEX_op_goto_tb: tcg_debug_assert(s->tb_jmp_insn_offset == 0); /* indirect jump method. */ - tcg_out_op_t(s, opc); - tcg_out_i(s, (uintptr_t)(s->tb_jmp_target_addr + args[0])); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); set_jmp_reset_offset(s, args[0]); break; From patchwork Wed Feb 17 20:20:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383906 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3139310jao; Wed, 17 Feb 2021 13:13:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJxXxLm/ahgiCC2kxJ7NTEVqOzLTAtuiIF4UMXggFi2Rh3Qis7YCSMLjnLcZVIymZY0xTTN8 X-Received: by 2002:a25:cb8a:: with SMTP id b132mr2292588ybg.58.1613596421133; Wed, 17 Feb 2021 13:13:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596421; cv=none; d=google.com; s=arc-20160816; b=OuapV+q5dkRHdbeST7hklJuQ59S9lEb+0X/vsG4ImKPsiKw0CtykHap9rAfYQsl2Om 0/FLS5gpylPTJOeX5pvEHSFTExtsY+ygo9/HqYm0HJzF8r3iogurMHBftUe+PzfdZjxi AqV6To6hWw86/Pq5YC7yNIYEEckrfoWZavf98JlAz0Tw/1HUUq53UuLTkhkz9ryRg9cL L0wy7cmavl9AbAPVrnIBizvqZ1+B6cJrPiktQuu8krAXdkhQarpgVNbmS3UEP/m2X+y2 7gxBiX7z/0w7e5BiV8c7MLXPyDj0hwo2CcTmVq5qgyqxsopmHCT8hTu88fTRKeaRe+kq M1bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Kpfe6JZmwXM15Cw7O9Ulgnnkm0DVoqv1s4+DGCwKajc=; b=BrWrB74XBU7AYPeWoTfy8hQkkb+tgtbDIjU5dbtaacmNpNuJRgx7vEaU/Uuqu76arX /AGOejW3wJdNPUJ4BbhhQnToEX6dA5s3A1X6GOvprvYSexejXuYGFRUJcZ4+HmMIbpeR K1Z2iuoVnp+fj8rYBlAHc8l3/4vqShWzCLcutyM88DkaWAurPSfx585y7CRK6IQPJp3Z wlH14MWafZJrAqvQn1jt3YLpAcYcoh3ja2CRT8ak0n2TIqLXIZfW5Y216Z+f5MzQMqwk ulYLH63SVd6MZ3PisjRksJnVnJsA25WrqIYxwo0uzC5W03sbz7UI3aIcRXDBmztr4Ezm BbcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sw3uO+4P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr Date: Wed, 17 Feb 2021 12:20:10 -0800 Message-Id: <20210217202036.1724901-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, validate the type argument in tcg_out_mov. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cb0cbbb8da..272e3ca70b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,17 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -337,16 +348,18 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - uint8_t *old_code_ptr = s->code_ptr; - tcg_debug_assert(ret != arg); -#if TCG_TARGET_REG_BITS == 32 - tcg_out_op_t(s, INDEX_op_mov_i32); -#else - tcg_out_op_t(s, INDEX_op_mov_i64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg); + break; +#if TCG_TARGET_REG_BITS == 64 + case TCG_TYPE_I64: + tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg); + break; #endif - tcg_out_r(s, ret); - tcg_out_r(s, arg); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + default: + g_assert_not_reached(); + } return true; } @@ -534,10 +547,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rr(s, opc, args[0], args[1]); break; #if TCG_TARGET_REG_BITS == 32 From patchwork Wed Feb 17 20:20:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383903 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3138024jao; Wed, 17 Feb 2021 13:11:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJzmLn+lLWiHcxVpsbpdqE6GPx7F8Zjf8YXeHlj/ECNhdQcztzW5mZzTtDePdcXgTCzkHmVN X-Received: by 2002:a25:21d4:: with SMTP id h203mr1866018ybh.290.1613596291069; Wed, 17 Feb 2021 13:11:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596291; cv=none; d=google.com; s=arc-20160816; b=AU6roHYIiqdNyZKeyoSlF3VipCEo4wdEx1RMloIMFFnTDWYjaHUVALPZHI5hRgRtkU HufWrodk8MQiAdu4Yim2wOAL/8er5/Y4zf6smxjNGX9jriSIXULrSN5dOGnjwNTTCEwz B4W6tBRO2U+p4BF2IumCf1cRIqwADMq2InlRIhnxhfAeYhJ7lwuantu6Hy9rnEBtfhWP RX7NTk49Cn+n5z4gWLh7khvy4jOFa/UnYA4DYbBvopMp7u8g1dGh6+PsNxaz+A1yb63+ UEyfOaodFlewLANX9Xlaei5XjHbZh2nl3wakWrzVQsUrQiEN/ixq82hLtRQdZtPym67N B3+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RzFAVc3cWW3yr0pGO36GqM64ymG+VJfs9mt8bjfFgIQ=; b=JFMGZqtoSy8o0oq/FTjyw/f7o7q7o5J6GAHpiIuL0x4FnpMxltMv/ZVfNPJlLmhOaE g8/uKWmS4l0SJDO/Mt16LFPMtIW+9D0f33OCTkS0po9Lpl2JC4tJFYX294hhK13/jgJa u7+PfH4yGczRk+I9b1tMXWt0D2XgCnryWSivy+mBq3WmMP4z5mLc8WmvUQkwOpt1VUCU sSHvM5YUke+1mKbHuR2nl2m0W7eCqInhVCVRyxR8yLkW1Bp6PwpGdZWC/h95hA3b4C16 mN3QypnA4+4VCjVbs2EbXghJfvDznlNv+SVwzXThL7+UP1VA0zUc+QNyjQFCzDeqtjKr yZeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vhbggrpp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 46/71] tcg/tci: Split out tcg_out_op_rrr Date: Wed, 17 Feb 2021 12:20:11 -0800 Message-Id: <20210217202036.1724901-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 272e3ca70b..546424c2bd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { @@ -500,11 +513,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ From patchwork Wed Feb 17 20:20:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383888 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3129834jao; Wed, 17 Feb 2021 12:59:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJxBAdjhDmvJRQY/L/4MKssN137h7/VXlcJ0CtEWd7Aj2N4oCsMTdpq2ZkKv143HN/IGGq7B X-Received: by 2002:a25:d684:: with SMTP id n126mr1834335ybg.223.1613595544169; Wed, 17 Feb 2021 12:59:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595544; cv=none; d=google.com; s=arc-20160816; b=fAswONDlVmEu7DPwvvmEjOAszNSk71wQbMLYlHaujZKaYEu/CnRe1Xjx8t0twIO9Qd QKeOsaoCbjBI//v61aDWR6eZyGCy5vqXil6GKkSeRwBwPJ4YgVtxdl35w0OFvgV8ti06 Hha+h15AZqBgdK0vn1HxnifnzT0Iw4q606Hho+Khl1FrZSgM1nMISakS5jiXt9Wz+D2C FnO8AABDrj8TNT5x4V9Z8XJBsj5cjFVqmkIaiE1u0WYi56hHqMu3uiLExzO8JuCVpsVb 6uxE+OAHyz0AGGrxALHtmug1qN1m+VaiNT1ExI2EIo1/03HoUQNPnC11ushrRivrtcRo SiMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QUs6bZlAERttu34ccVgcqABRUHJrBFMHH0LXLYX1oZo=; b=fyatkYIcqDMvNaGBqAJtgNtAzyKCgeJ1F8eZSKJyXJnqjk16ago5PGb52RuAKzzkMQ h2iWkrxIClKlkN/Ll2k1hGi8Rrpch/sFiOMVPfqlcmSceXRy2FRpIASlEJC//0VVG9HB Dw3iqprKascbJ6U+MWDuex8BcuCkeMxWVv7LIqaPzLnD+ONmtCbVIoh4JCv0nvj8Zwfm FRRTUilk0uvKIM7M3dIhMDKahvMB7hGl+iXjbP+2GO21Y/mT2mUQkqbF+iDZ2y3l89lH s1A6QfYQA7cwk/vwnH0Rh/VE1mX1FowDRnB2NuH81992eTf6mhUfCcEjxdVyMODpMh3e IAYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AA1pobb5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 47/71] tcg/tci: Split out tcg_out_op_rrrc Date: Wed, 17 Feb 2021 12:20:12 -0800 Message-Id: <20210217202036.1724901-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 546424c2bd..5848779208 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, c3); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, intptr_t offset) { @@ -454,12 +468,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; CASE_32_64(setcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; #if TCG_TARGET_REG_BITS == 32 From patchwork Wed Feb 17 20:20:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383907 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3139915jao; Wed, 17 Feb 2021 13:14:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJzCVSOV4/hshhXbnG/qyBwbebknQHRmvQ8tC7cp3T3PFhS7XBUU1Q1sIM6mebpSB8nREDxE X-Received: by 2002:a25:d3c5:: with SMTP id e188mr2107979ybf.345.1613596488352; Wed, 17 Feb 2021 13:14:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596488; cv=none; d=google.com; s=arc-20160816; b=vl1CkaFAUgdMDIUJhLf51YVUTAYwWLKihf+4IFjNb8xBpIVqndgA0C6ihMLSZrXM0c EQVg403QoNNaw8yazwOiDmGGyigKXlWfc9GE82vzX59zobhPOJsHFt0nNLE69ncw4Cfw k+3Pw3U+4JYM26psetnfU4ibBzZ/kEW7iNOXpqbt65RvBRL3yR7bODKQTS5kxe6NizqE oKrbceXz0LVPoNcxPoxI5ONJFqIuIGfW1PGzJrjMR5H/0L8kp4732HiXG5O2BiUwiWi1 PAexBQn1WUJRlWtF8VXg2nDU4/dtkZY+t6t4wcvjCeDKj1D2zrMn6o4QfQI2kcje4PW9 AfWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A8+oxGont/+bDGkQ3AaEp3aS+SzJCnRbYSKjy2ImL7Q=; b=MoV7tkWO6rHxar0QKSjRD01H8h3n/ypnOzm12oLHraGvONQlBKqW9laCpckwHQ6kEP GmrsVUDQaVGcEYNKjYrzW5uJMTD+geQyXcrvbWC2H76Kd7tjxLIGKEMVlAYqJqr8Auat Qe/chr1kUpmAZ48PdHIplSR1wThjiFiKufFRO1dKEbGydBvsdrkKvt5vVjILzZzEL+TO 7ovZyoLMwvlc4d/B9EWywTv+XqsJoL5xnE7k8TWwBb1MvziKFaSn00F75ZA5PFaGEl47 5sOCIqfxO4zJHKxcfufpRYjWqheX6LsLHojPytPhDt+4oZfJ9PBpADkwg1ChZ7Lb9W3p 5nNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=q7cKT6Ox; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 48/71] tcg/tci: Split out tcg_out_op_rrrrrc Date: Wed, 17 Feb 2021 12:20:13 -0800 Message-Id: <20210217202036.1724901-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5848779208..8eda159dde 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,25 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +#if TCG_TARGET_REG_BITS == 32 +static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGCond c5) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out8(s, c5); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, intptr_t offset) { @@ -473,15 +492,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: - /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out8(s, args[5]); /* condition */ - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); break; #endif From patchwork Wed Feb 17 20:20:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383910 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3142088jao; Wed, 17 Feb 2021 13:18:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJzh+HhIYvj269ofN3fjZtL+Kor9zpynAZC7T1N6FL1QOatG0TIOWlcJYkgQPJIqqyeRHExC X-Received: by 2002:a25:7dc4:: with SMTP id y187mr2094776ybc.477.1613596681935; Wed, 17 Feb 2021 13:18:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596681; cv=none; d=google.com; s=arc-20160816; b=Eg5QomPXl/CmcO5ZDrh7cDFLa1EN39R9PJFa3SaRRV3lLbOo+hvZ3/aphaa3p73Cag ZPuYIA7fqnkT7OMFbavSYNvNcoeVdf57s/6gsgu4K7USprCKc+tFKR59Mgp+aGEzwfWW W87CMhK4GnwpARL5gsC8m3d51a4bHF74oQ7a88SjtjPZGjgkgJUdqU2FJFfjOwbR7Ir8 oqBmZo94XhnV1gdi/P4Ll1Ka316xW6Ldf+agr4/hsQf88pUkaJqicJzcd6tZ7Ah8nWg1 ImfaB2UxdON9X2kvAcHztacbzvlR637wTGEDbdvb8f5VobQiXL4d+79PQjlmDKpD0EO8 7M2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6fN3MzHzuWIrC3R6bdCZxAnV3xyNnPemffGo42IAOp8=; b=hE+nmHHTT1XrjTKlJoeB4wJXvgb5q7HUb+i7Xg6FVb834FrrPgQ+O0oTZHVpvcmEeP z/sB0k9ytwd4HNEmYsgDpBmTiRFH/4SS53gufVuwd12xZSbN1eZrU1ZIx4zJy5FYEnk6 vvx9dTjd/0+wx+0Hxwj7fmIv4Zi1vuDodksZzW5HWB/A0+LmUl4SJBSnYEPInzeY7UVy GtbPUw6oUl3CBAWDw4sK2iLlyGMYyb98/5wU4ZNggvF0gcvYS8EsBWL0yg808qLrW0w9 5aMEg9hIDQh5liBR8n2WIZsu7K7HxOi4PVD6NoTm2/DT5NbrhsYSu5UYMf7Ya3+jusvF s5uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZLdZVS51; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb Date: Wed, 17 Feb 2021 12:20:14 -0800 Message-Id: <20210217202036.1724901-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8eda159dde..6c743a8fbd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -355,6 +355,21 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out8(s, b3); + tcg_out8(s, b4); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -538,7 +553,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ - tcg_out_op_t(s, opc); { TCGArg pos = args[3], len = args[4]; TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64; @@ -546,13 +560,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_debug_assert(pos < max); tcg_debug_assert(pos + len <= max); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, pos); - tcg_out8(s, len); + tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], pos, len); } - old_code_ptr[1] = s->code_ptr - old_code_ptr; break; CASE_32_64(brcond) From patchwork Wed Feb 17 20:20:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383890 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3130678jao; Wed, 17 Feb 2021 13:00:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5B45e1Urn+ya6egwdbzwhGarWgUWyonABvtYFvoJyE0DlXIMMZLXS56SIt04xW339gi0P X-Received: by 2002:a25:5051:: with SMTP id e78mr2077360ybb.386.1613595634678; Wed, 17 Feb 2021 13:00:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595634; cv=none; d=google.com; s=arc-20160816; b=hxuydtiZEmCNEgjroWC5dhwRj3gg/lrG7CPzmRUiT2HyRDwO+xwGBMTlQyUMVdMpeD P7QJG39NqL7nA4m4bALDWF/UXbmg2CuhQz+4XiCs9blRzq4shGFlbEZyB18WCz1FiCAz aPpYXiDRj6mIwHgHMn1yl0LEmOTSMziPfJaQHzi207CGainZrjml4YqCsKHqh3HVmPGq MQI9UOd+VwDsiVQnKIpruDWB1DnJt+jJ93l5HYbJ0XOx2k4Ri7rasuZufs8U0mjYPGYF mBggMmtCJWPTH/UNmA4pFdkfTL7UZlF0TXW/vltxuJKFN0DAlxVP9OrsMdLyv6pM3nCg AMfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=p6E9LDuPBslW5lnZ+lbP25axObg1A1JUNAlm8q5oVbA=; b=JQMHJSaFAEfX6ItgzpX5E/PVAxR2nxrIrjkIYx6ybmkjnEX5FE3C3sXcF/5F9WggnV R3eYUJFAbWEaYgGWBdbQ6SBoYCgEv77jNu+upGwOltlKOX7WQOwg38wsspTg3xPikhCy h7d4pSfKlmcTPfN/jc2tVXNatUt/BLYydWyLx+Tsg4niZqpjP61CFvKKBb7YlyLE0Zf1 Op4oALOTIyumivLN0b8MJSDTaGXd5jkncTgoMBJTcw50WFlR1JlyUjFOZ9Gp7UZImvZ4 swu9fGl0j62BgyWINKIxGKRzhPuBXyEJ4xBcxOFpZk/QsrgYyN1OkJXa/v6uA73izLm3 nxQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EClC1AzB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 50/71] tcg/tci: Split out tcg_out_op_rrcl Date: Wed, 17 Feb 2021 12:20:15 -0800 Message-Id: <20210217202036.1724901-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c743a8fbd..8cc63124d4 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -341,6 +341,20 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out8(s, c2); + tci_out_label(s, l3); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -565,12 +579,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; CASE_32_64(brcond) - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3])); break; CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ From patchwork Wed Feb 17 20:20:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383893 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3133854jao; Wed, 17 Feb 2021 13:05:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJyE1OoMCaw3VPB+g4A49MIMUE9DrzfiPFMVXIWSvadffQPuF4nHVU25oytoAXmGmxv1QALw X-Received: by 2002:a25:d4d0:: with SMTP id m199mr2162761ybf.26.1613595904384; Wed, 17 Feb 2021 13:05:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595904; cv=none; d=google.com; s=arc-20160816; b=teKDbpkMgsVy5owuLm+lNsrkK1KYUG81XnGhwGMoRnVY1RgYLcE2esq2Uqpsb1vpF+ lvIkMkrur3bL9KypCIufbkhJvS9PXbttanFlkRNSt76253IhdbOFaBLmsKrNouN+fR+e IuXJlQzM3VsQivXyQFgKlnH6nmn9TgsxNvaGXOnxZSO9r9Gfb87kNPF09P2y7UuivcRf f7z409DkxsowNSTheDQB31K7D+scRUNNVMfs4ILJIAkM63LIQTawIcKkx6sArTos7Fu/ 7IbtCJqxFXCojKdp0bx/y7osW4V3Po6WrtmkJRl/FPmTgbZkusTCs+rZqzf6VlfQRHXX HxIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Muk10JaSTB/BV2ItdFkgjXJDIa6PJidFm2ztv5V4ygc=; b=OF7Sw0JrqoaP4cKFEBBuWeDdj/9L6knQ0pbDTU9WBsTJfl2zkYmhDHB4xbLhwLGdun jhnxNhpOWsBWgacT2ah9UpmFJVKxeo6u+t+CdpKK5qAdsKZ5VIKNn5SL4pAfvArDkQH1 Nniveu7CqEnUHGOWKZKDcLDCoj1udPhqCsPaOBL3qxVeBj3xpKS0/irdcaMRRc1cykt7 arYIsq4Eo3Tm1H68gFiKK9oojr1I1Ko03jjdobGOCEcI7mIg/ijTVjkDzcYqhEbpGKUW YUvTvmyia+zsAih6dnYw7xYYOJzfn9ysXTySQBp/kBtyS78FJRwBXPjhR6OhPk4AMNMe yQgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=O8Bkguew; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 51/71] tcg/tci: Split out tcg_out_op_rrrrrr Date: Wed, 17 Feb 2021 12:20:16 -0800 Message-Id: <20210217202036.1724901-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8cc63124d4..f7595fbd65 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,6 +401,23 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } + +static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, + TCGReg r3, TCGReg r4, TCGReg r5) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out_r(s, r4); + tcg_out_r(s, r5); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} #endif static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, @@ -601,14 +618,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out_r(s, args[5]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], + args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: tcg_out_op_t(s, opc); From patchwork Wed Feb 17 20:20:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383913 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3143257jao; Wed, 17 Feb 2021 13:20:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJznGA/DU/C1hXqiLGOOCnFWYbAG4PG89THiEs00Kz7nif0EqRkN8eXeKyiSak9Xht7Np0M8 X-Received: by 2002:a25:b8c7:: with SMTP id g7mr1984039ybm.432.1613596800910; Wed, 17 Feb 2021 13:20:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596800; cv=none; d=google.com; s=arc-20160816; b=v0ySkYYtEjRRzH897roYscIRB1Agig3gj7VUkyO9N7RzCPaHcaEv8iGbnBQYq05M9Q jPL/qaNJOwfQoCpVtnGjzGHwSAnjPTd9CHuaMbX5IxVK80e8WwkdAGQuMfggOIe1zTAb kZvAhxreE4QaM0N1CYqwawJzIO4a8bghgFqG2hQ+SV1qdm2wgf8THF1IC3ktheSTlgja kQQiZFi4qtsoU3mMEWc5uEIi6KJneNz4A44mH1qExWTOx/2ZshbCD9/IIhiWMWhrErL1 llYJmE7oLhvF9mhMgETmxI2gQcMEd0S6Jez2TyK/kAXD1ylMkrWhd0/4vLHu71b2r1Et uMAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RltB6tJRO1PShAvoUlO75Uo0j450X071u7i11eDg0EU=; b=d56t+Rs4Eg8YFBF1N1YMjNyPshvPJHJE8qla4SmcEtcSYFuB+/uoNUA7etxGA3tIx1 EAru8J5Uv+6c2oD7OBPrIhesi9xYh3AQmawwaGHUudw5Ht492k0YCntQORoN8Zin/xcq vZnPB+QL/NF4IbrTfiCZNUzpq+kIcdGmo88bjdEXNjoHrrQnzy9eAeiibzkR5wJwYJL6 HHP7umwsyDrTW/oj6C4aqtUnwj45Y3UcKTI0AEtjPuTaTgz8g8ki1II84CNh3CWZboUD IVVUkjbzUV3pEcmdIwXmFaHG0wS9FNy22aPpPQI0Whdh6K2GL2WokHSxL4HaUFYWhMsw P5aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=egDEQVH2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:23:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 52/71] tcg/tci: Split out tcg_out_op_rrrr Date: Wed, 17 Feb 2021 12:20:17 -0800 Message-Id: <20210217202036.1724901-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f7595fbd65..c2bbd85130 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -385,6 +385,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, } #if TCG_TARGET_REG_BITS == 32 +static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; #endif From patchwork Wed Feb 17 20:20:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383892 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3131593jao; Wed, 17 Feb 2021 13:01:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJzvyhua+S9iouYhAY7q8RkOxQIWEF5m2ztPiREPxrg4nlZtCQjcRhnL1gmlx3vkLRwNDOLb X-Received: by 2002:a25:aa43:: with SMTP id s61mr2209945ybi.32.1613595704334; Wed, 17 Feb 2021 13:01:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613595704; cv=none; d=google.com; s=arc-20160816; b=KmQFa3lqlhYdAAqZzB2BzL1dxyU2+ys/D9Kw2XhDWa3bxp22R5medbpF2b6K+rU5Ml Ny5nH9yLFN8DCx1k1tS+EYR3EuKDuT+qh0/cdG1oVou24dwq4f5HVPdz732lZWX5DUMS LIiWJLcKwo0MZrHluJNrNYGGyxnH4il+menB90ZVxH/Ld80B0T0CJIT78igwtmAb2ki+ WDU4aO/e1cP7Z1rw9VHIebULb7N3/jdUgrYZIUGWCpjbsGHjK/PrBXtKIFvFay96JpC/ uqK+yCG8ari1fzZoolLfbsO6sJ23U9/vb1wTmEv0UchVcMEWLd39xoOgz/uoau6WsB2H QFww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FuCnYTOQyWEVo9ZyllKi/tHo7oVf70VfVQ0xN8tYC5M=; b=hbODG+Dfi6pCErBmzp7GPpM9nG5vyPyvYDZSjMd2zxjc4PL8bKGgj4QxmqgNW+5WFX MEWft726pxRZp9ICxY7A8aeTzfjo/K1K/1eQR5U3k6YGHxwUjwLirpSS3Fypc4CgFwM7 /mSZJ6z9hhpl7CHWW8laTNtL3buT/qBCq9PW4Imz9dXGEyY3xJbhDp+F4+SPxtXyq4/g 9yHsXli34yIBLEHx/q2QH+lO+QwnAXznvzBJPUy9PvvUzKDoavZeWkCVrMCpOdg/jSyg KhKUPnTWnGVjhqxDdXIjgwLRfH1BfJYLwbyLnqMngpJK3BHSV9ZBox/ma7ftGyHOBJQl Ovaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I06pMo94; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 53/71] tcg/tci: Split out tcg_out_op_rrrrcl Date: Wed, 17 Feb 2021 12:20:18 -0800 Message-Id: <20210217202036.1724901-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2bbd85130..fb4aacaca3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -399,6 +399,23 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, + TCGCond c4, TCGLabel *l5) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out8(s, c4); + tci_out_label(s, l5); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -636,14 +653,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out8(s, args[4]); /* condition */ - tci_out_label(s, arg_label(args[5])); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], + args[3], args[4], arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); From patchwork Wed Feb 17 20:20:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383897 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3135697jao; Wed, 17 Feb 2021 13:07:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJwWaIF06pJy2tMKebJ4GKrOgKknasdpQ9XPDrPmBYf+sMUoIpbGS9T84xqyzO+PC81+k2Ei X-Received: by 2002:a25:800c:: with SMTP id m12mr1879097ybk.25.1613596068365; Wed, 17 Feb 2021 13:07:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596068; cv=none; d=google.com; s=arc-20160816; b=VNes37/AKV0vZhXtcWJ1FJa3ixrmR5DKFoxAX7RIMJilfVRKpm71NjSkyfGQ6oeb0a R5xcJdkqZHYQ6HH76SDYs6DtPKON/AfYetpNyqvY+euTIEZb5pw2rmMc0jthtCTuFmat mRi08JlyGn/HF0y9YfLtEBUWTXAxnWS2LBdj6fa0ua9COhI/W8Oi3sD9c0ND9t5Eq2MF koBJTjnOi5Z5lhrPeJ+561kNrzGTgI9Irh/VPXSSnxj9+QRvEIPrdzjJCU6vVhj8KdQ/ /xpvIIiV/9gX8pDC2UE1JPHhiEG4ANkcf47eN4xOmufnUmHCG82oxroeYlyIlq/dBQ73 Hzaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UtDE8Pm65Grc/U22TwT0AwuyG4b+N8yR6xVz8cz41eM=; b=uDYs29BOdy1PpIVCwlbaW4gjKQxdCX8nb5cBAEVjfz7+ifMvayIT912Hz0fkhxO3vS u/uWTJMakFrxibcm/kHa5afiZonQssKIRuCQrIelyGspe3vg7S/1/L4Gz+WG+z5yk8+3 zfFdmhdvPK9X5ZZGNg8P/ukRlnZpjccBwVNjppDRe4TgOT2w6MBNxKbmXUy27e3iI5gw AvCInr+pf8e93NMSeuPl4HoExx46dZ8JB0ULxsjX4f/K223kconR43/tnGUYNIUCrEJg BW7306zAz6EK2heL3NV3AFZtW2TFbI6E3czBeALWTypF/Y78AKhX1G1KhqRU2Jl8vm1A Z7SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="YkC0I/kb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 54/71] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Date: Wed, 17 Feb 2021 12:20:19 -0800 Message-Id: <20210217202036.1724901-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fb4aacaca3..f93772f01f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -314,6 +314,19 @@ static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGArg m2) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out32(s, m2); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { @@ -369,6 +382,20 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out32(s, m3); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -384,6 +411,21 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + tcg_out32(s, m4); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + #if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) @@ -663,29 +705,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); + if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } - tcg_out32(s, *args++); - old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: - tcg_out_op_t(s, opc); - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS == 32) { - tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { + tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); + } else { + tcg_out_op_rrrrm(s, opc, args[0], args[1], + args[2], args[3], args[4]); } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out32(s, *args++); - old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_mb: From patchwork Wed Feb 17 20:20:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383896 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3134981jao; Wed, 17 Feb 2021 13:06:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJwEJYFyronOkAPYN+iuUqH/uxvY023rqMByFZkXbfoUh90pkCS4v3nXrLUBFJeXYko03azH X-Received: by 2002:a05:6902:706:: with SMTP id k6mr2099947ybt.52.1613596000498; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 55/71] tcg/tci: Split out tcg_out_op_v Date: Wed, 17 Feb 2021 12:20:20 -0800 Message-Id: <20210217202036.1724901-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93772f01f..eeafec6d44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -303,6 +303,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { uint8_t *old_code_ptr = s->code_ptr; @@ -587,8 +596,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - uint8_t *old_code_ptr = s->code_ptr; - switch (opc) { case INDEX_op_exit_tb: tcg_out_op_p(s, opc, (void *)args[0]); @@ -725,8 +732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mb: - tcg_out_op_t(s, opc); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_v(s, opc); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ From patchwork Wed Feb 17 20:20:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383915 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3145114jao; Wed, 17 Feb 2021 13:23:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJx8Vk/vWQ4NuKQpOJ0qvljJnWeyEDhl78wIOykNQXl+QFKyHhNyfEnkCWFRLf1DePk4EnF8 X-Received: by 2002:a25:31c1:: with SMTP id x184mr2031942ybx.365.1613596987569; Wed, 17 Feb 2021 13:23:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596987; cv=none; d=google.com; s=arc-20160816; b=rwkZdb9OgVZQqMix39GzTbzsb58vBWT3xWWgkFiO8eviBztK/I//Hmk89EuhbwgDpq NzGor8GbrJu9tsIQAJmfj409C6E4hWnKVP/wjbg0tSGc8wb00/xNh6LXTEZjEGKkBwHR fGmE5g9ZxxTu4EnO1cWzw1zK01SXGQKNUPp662GRyCPlPJTzZ3RGxW15kzjR2w+4GHOQ TIXEbb+p2vzLK6s81fh0pbk0VueOwUi39MQUQJhsV0IpDEds/oYKz/hyccMySMHQGxL3 edATC9ge/WicKjNHHv29WaQK/X9kmbufLHzlbhs9qFW+V7rmpWaTTEdSNO07zxa+/DOP Jf3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kQwYPaxcLPGVIBaZFpt4Ukjta9EglPQhHZw+11ye7O8=; b=YYuNs7AWYniSrrG+F8+qzkDb8rqmjJ7Y2Z1RRS79/TT8Hoipxsp+6IETYwQOEFDIx3 JVAt2BNvdxUvTPe6ISPsSmDzwDvzS6AVIGZgNLvi4KXRK7Yd8x08e4BzZBU1utr2rSiZ piFJbHx2JydatfyYfjt1hm06e6iFOQAkcU/UocAWwgcXnKwUHsuJ282RoXwBVxrs/H1j 2xH0xTTz5zi8XuYWZY7ERfwWOaGe5WxHPt+qMlhdVtoE3VITkTcXJMhsqqQn/3ZGRxT+ i9IC41wyXvnk8NKPo8DkLn5vfUuy/2vmrRf+BRtwyao4ll80SOccnIP+iJsCX+LiarWY N57A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VqjdErix; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 56/71] tcg/tci: Split out tcg_out_op_np Date: Wed, 17 Feb 2021 12:20:21 -0800 Message-Id: <20210217202036.1724901-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eeafec6d44..e4a5872b2a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -312,6 +312,18 @@ static void tcg_out_op_v(TCGContext *s, TCGOpcode op) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_np(TCGContext *s, TCGOpcode op, + uint8_t n0, const void *p1) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out8(s, n0); + tcg_out_i(s, (uintptr_t)p1); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { uint8_t *old_code_ptr = s->code_ptr; @@ -561,7 +573,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { - uint8_t *old_code_ptr = s->code_ptr; const TCGHelperInfo *info; uint8_t which; @@ -574,11 +585,8 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) tcg_debug_assert(info->cif->rtype->size == 8); which = 2; } - tcg_out_op_t(s, INDEX_op_call); - tcg_out8(s, which); - tcg_out_i(s, (uintptr_t)info); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_np(s, INDEX_op_call, which, info); } #if TCG_TARGET_REG_BITS == 64 From patchwork Wed Feb 17 20:20:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383900 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3136611jao; Wed, 17 Feb 2021 13:09:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJwz2WMumJjsqgxirMPZrU+KT3AnpJ6zN5UHtp67G06OYjvQGk/h7OTihsOHhkTS3gmkBv0o X-Received: by 2002:a25:860a:: with SMTP id y10mr1999415ybk.254.1613596151655; Wed, 17 Feb 2021 13:09:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596151; cv=none; d=google.com; s=arc-20160816; b=jBt8aL6bR3JNW++QKExgmGlYPjxbI9qbMm8hDi5BLelP8xnar0mTLKaRddEk5O5/pd 7c11PG62wJg0N+ZaBB3NoFlMbzhAwyNa0yjJZcCTNdCDA1nzClLg8kZIk1gTNpkLjb35 zuAWp74FjHyVNuwkWADqRv3AUE9lxJR3nyZLEMuYiz239Ch8yu8z1k1B0IvZz615OEwh TDuWYs9lRkHm6bmugnXqLfb6e9Lu2jDF9HqbLxyHB9W/rJfZEZVcvu+U6tE4Puet3WI0 Qix2Lz4AXxNOTmSNVewt2yyiWa91yJ1371FO1+wAARCLsXxSo59GWx7aXI4bUABCy0R5 HruQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nbzdCRnUzVvHAlHdm0W/U/kL5Ps02KKsV67u0VtR3Rc=; b=qYODYI1UoCKPi5PJwsJ4p/Dwts01mV+ceTaLBE4d4zvuaJBemGrHVY4cu83d0HuxTi ZkDCjWqa1IhaThVvYov/QItJpUqVrx/8Xs+2ZF15jrGkgv1+Ydev1/uz9c9HLADmEr9M sS5PXEns2igz/ndNLVvb2qcd+fpG0s0XLsYrk65w15fZ/ITUNWl+YZwY7BqyDCiJXpUH hnnPIH67G9EcATzdCo7H5SVWOMagllQoOO7SsrltbLSm4NNKmxHe/foGiIt1v443KW6c GVi5tNgMbr+9FYpLkcaLHJqMK9rA4wed4NgvUXfQR3Twn7Iu8tkUOfFa7QKIWP0nKjnl 0TaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="ER/Nplcn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 57/71] tcg/tci: Split out tcg_out_op_r[iI] Date: Wed, 17 Feb 2021 12:20:22 -0800 Message-Id: <20210217202036.1724901-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 50 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e4a5872b2a..c2d2bd24d7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -324,6 +324,31 @@ static void tcg_out_op_np(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } +static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out32(s, i1); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + +#if TCG_TARGET_REG_BITS == 64 +static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, + TCGReg r0, uint64_t i1) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out64(s, i1); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} +#endif + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { uint8_t *old_code_ptr = s->code_ptr; @@ -550,25 +575,20 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) } static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg t0, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { - uint8_t *old_code_ptr = s->code_ptr; - uint32_t arg32 = arg; - if (type == TCG_TYPE_I32 || arg == arg32) { - tcg_out_op_t(s, INDEX_op_tci_movi_i32); - tcg_out_r(s, t0); - tcg_out32(s, arg32); - } else { - tcg_debug_assert(type == TCG_TYPE_I64); + switch (type) { + case TCG_TYPE_I32: + tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); + break; #if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_tci_movi_i64); - tcg_out_r(s, t0); - tcg_out64(s, arg); -#else - TODO(); + case TCG_TYPE_I64: + tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); + break; #endif + default: + g_assert_not_reached(); } - old_code_ptr[1] = s->code_ptr - old_code_ptr; } static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) From patchwork Wed Feb 17 20:20:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383904 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3138728jao; Wed, 17 Feb 2021 13:12:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJxnD7YdI+XhEBFRCzfexFUtcdht8+d/RwABYvr665nAxmCEBroSA67taKllWcPM2fwqrzbn X-Received: by 2002:a5b:488:: with SMTP id n8mr2129618ybp.224.1613596363975; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary Date: Wed, 17 Feb 2021 12:20:23 -0800 Message-Id: <20210217202036.1724901-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 1 + tcg/tci/tcg-target.c.inc | 1 + 2 files changed, 2 insertions(+) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 4df10e2e83..1558a6e44e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -155,6 +155,7 @@ typedef enum { TCG_REG_R14, TCG_REG_R15, + TCG_REG_TMP = TCG_REG_R13, TCG_AREG0 = TCG_REG_R14, TCG_REG_CALL_STACK = TCG_REG_R15, } TCGReg; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2d2bd24d7..b29e75425d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -829,6 +829,7 @@ static void tcg_target_init(TCGContext *s) MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); /* The call arguments come first, followed by the temp storage. */ From patchwork Wed Feb 17 20:20:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383901 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3137034jao; Wed, 17 Feb 2021 13:09:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJxmz/6t7O+KmGDqEy7HGydpotVbxdHsl6OFf3OIdOypOudhTRVWl5mQO4qRzQquhGbrLbUM X-Received: by 2002:a25:9888:: with SMTP id l8mr1899251ybo.379.1613596197978; Wed, 17 Feb 2021 13:09:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596197; cv=none; d=google.com; s=arc-20160816; b=tZxCmoLiAhgGEhFpAOCiXrvVF+LY1hFf/JbLebl0EbWIZeOVB3dHk4H2+u44ovJ+cP IIzJAHxJ2ptbUoirARErGT1dWmZEbWC3GgHVGNgIjb+ORGhCuQYD69N5iFw1me0KJ6h7 wgUNNoNN0gPj9hC6bliSH07KlQkd6eYv6sy01GUg6qt5iFwSRSsQbqJ1uHXwWtMHYXzL z8+Txa41eMpDXKLi3++db/nyNpqFiCycerIQZcKFOtctGrDxHvoL5Vyr2FwxUUTLsf3y Uxbx0mMAjnHoc3XI7M4utNkuHsao2iNa3ovvjmDmeek5ES1swDq03HrNamuAPm311TP/ J+Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xVPJpsDWn13Ikd2YVdvJyZUJO3co9ndv44w3DFxxxYY=; b=WUAr6XYEiWEdFAQFDeyubvzKgF6xla5WGiUSZEwfmkTpm89k3+9qiiPICVLJPi6iwk SdsB3XfrNzAPZP90+h/XzkvmJC+5xY++wK3EY3B9YOUlPZ0YM7ArugMZF9ZY1oeavBUB tT7ZsoxvVzINOIX6rsTC798dlMq0DabGc1Ofr+uhXMQD1PdNUne4U26rdmXAg4mSSVJq iCPS/4zoq5zbORewdKisWTpMoZlEmuLQuDBHSTfyz7tKEVCWk7k9wEzzZIqldH9d+272 n4JSBUr0vLbyIRP7uHcneW620HssHWqziJowDsAbQn4MgTXK4NS1Z9YBtuo8Q+dFKARL 1zuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=n5JhAdao; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 59/71] tcg/tci: Emit setcond before brcond Date: Wed, 17 Feb 2021 12:20:24 -0800 Message-Id: <20210217202036.1724901-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg != 0. Signed-off-by: Richard Henderson --- tcg/tci.c | 68 ++++++++++------------------------------ tcg/tci/tcg-target.c.inc | 52 +++++++++++------------------- 2 files changed, 35 insertions(+), 85 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 5718fc42a6..3f8c6a0291 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -141,6 +141,16 @@ static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) check_size(start, tb_ptr); } +static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +{ + const uint8_t *start = *tb_ptr; + + *r0 = tci_read_r(tb_ptr); + *l1 = (void *)tci_read_label(tb_ptr); + + check_size(start, tb_ptr); +} + static void tci_args_rr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1) { @@ -212,19 +222,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr, check_size(start, tb_ptr); } -static void tci_args_rrcl(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *c2 = tci_read_b(tb_ptr); - *l3 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -293,21 +290,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr, check_size(start, tb_ptr); } -static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *c4 = tci_read_b(tb_ptr); - *l5 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); -} - static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) { @@ -713,8 +695,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i32: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare32(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if ((uint32_t)regs[r0]) { tb_ptr = ptr; } break; @@ -731,15 +713,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr); - T1 = tci_uint64(regs[r1], regs[r0]); - T2 = tci_uint64(regs[r3], regs[r2]); - if (tci_compare64(T1, T2, condition)) { - tb_ptr = ptr; - continue; - } - break; case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); @@ -867,8 +840,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr); - if (tci_compare64(regs[r0], regs[r1], condition)) { + tci_args_rl(&tb_ptr, &r0, &ptr); + if (regs[r0]) { tb_ptr = ptr; } break; @@ -1178,9 +1151,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), str_c(c), ptr); + tci_args_rl(&tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", + op_name, str_r(r0), ptr); break; case INDEX_op_setcond_i32: @@ -1305,13 +1278,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r3), str_r(r4), str_c(c)); break; - case INDEX_op_brcond2_i32: - tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%p", - op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), str_c(c), ptr); - break; - case INDEX_op_mulu2_i32: tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b29e75425d..e06d4e9380 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -349,6 +349,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, } #endif +static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tci_out_label(s, l1); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { uint8_t *old_code_ptr = s->code_ptr; @@ -400,20 +411,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out8(s, c2); - tci_out_label(s, l3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -487,23 +484,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, - TCGCond c4, TCGLabel *l5) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out8(s, c4); - tci_out_label(s, l5); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -704,7 +684,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; CASE_32_64(brcond) - tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3])); + tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32 + ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64), + TCG_REG_TMP, args[0], args[1], args[2]); + tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3])); break; CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ @@ -730,8 +713,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, args[3], args[4], args[5]); break; case INDEX_op_brcond2_i32: - tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2], - args[3], args[4], arg_label(args[5])); + tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, + args[0], args[1], args[2], args[3], args[4]); + tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5])); break; case INDEX_op_mulu2_i32: tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); From patchwork Wed Feb 17 20:20:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383909 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3141974jao; Wed, 17 Feb 2021 13:17:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJzBnYXuTbmC+IqB7WrId1rYjnTOdrVsMlPeUCzsw1I0qLJBaHUNXb3dWUpYkzBjdcjmddwt X-Received: by 2002:a25:b9c7:: with SMTP id y7mr2110000ybj.458.1613596670237; Wed, 17 Feb 2021 13:17:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596670; cv=none; d=google.com; s=arc-20160816; b=F5eIFBs4+mKYuSqhHP80mTzBnz8pQ0sn0YB1qSg4CQXCal0l5qJ1r40HQohTyr4LNp hAqaeO2Fi3xzL+4nUAHUw8/ox3xfLnl8puWlDtlQWsJtoADY8QotyGleaoslP9yR2Bm5 fSuz6uQRgxLOKo0UQCxsYrAb+c9k+hGEmvGgpCLUdcTWXFkagAQFNixrqkHqo7gXgpHI AAD+1joBu2WGolwsUOBr15UA/mywi9ftPr4VYtH/cBNzixITFB/kteu7K9EBzrqyn0cJ uqqlruvyx7QhcbiAncGcv9GpV+bF5IBSQDIFWPDtdYOKl30TJwVjzRmvwCA+kP0VnNPL AxFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Oqjirx8sUQyYnS7vrLSDlLS9gocI/IN6++5opPveqXM=; b=OubLzFI1R+U/U+YEltmZBUKmlyfCH8LWoRtU6hgxYy24GwgBVpI5PkNwQRm7xOKu/y g9TRMN6P8UUU4EXfMmaq1TDZNirxjxdgm0AyGTHMTpRE6zPIPenkkjIYndka36Dv64Mv qB0f/14rZGEihK0HhqmmzIHK/muyWdvwMt8c33Uq9Uh942AEOojy8aVlhkjFzX8DOGhH 3/npt0xwnpmAgyDDp9jnSv6iP2mfOPEPpOZ0rfumbBX6gR/VMYtGRFVnxrjj6hbU8B/V /cKsZodY36fjKdsRUvsXAaUVKAScU0rI3BaQDIv4QaOstGu1BQyildSAQn7PzMpMr5Ei iFxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tRZfwSOt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Date: Wed, 17 Feb 2021 12:20:25 -0800 Message-Id: <20210217202036.1724901-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 3f8c6a0291..0b2bc905ea 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -36,20 +36,11 @@ __thread uintptr_t tci_tb_ptr; -static void -tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - tci_assert(index != TCG_AREG0); - tci_assert(index != TCG_REG_CALL_STACK); - regs[index] = value; -} - static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - tci_write_reg(regs, low_index, value); - tci_write_reg(regs, high_index, value >> 32); + regs[low_index] = value; + regs[high_index] = value >> 32; } /* Create a 64 bit value from two 32 bit values. */ From patchwork Wed Feb 17 20:20:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383905 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3139122jao; Wed, 17 Feb 2021 13:13:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJzPmXJ/6rHC5dNJQKrB3tce7zrMl4AFuY932Ydrn1pfiQhQyBJ09iAhKmaVvnmfhQYyTS3g X-Received: by 2002:a05:6902:706:: with SMTP id k6mr2138995ybt.52.1613596404055; Wed, 17 Feb 2021 13:13:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596404; cv=none; d=google.com; s=arc-20160816; b=MVQWOz0RctRVua5Ozp5why5wg5vpJr/9HhD7KXVcyeH6UKGKUycTTGdVCyvBg7Vo2z IAFEBLS4g5P1qQNdDAEZntyu17pH28eTusauPUazTV/Tk4XTmQ+rSVbNUgyOxqX/pzj7 ClV8EFjVj6JVUvtD0tNfgP18HNw+E3yr4SVV0HwJJN+lhb5aXU+vXJrF1JniUiluK02K Zeb9meCuqcHijwiFaUtAGf17RUzeauEAbY94OY9O6ASFsxRcJQwUw9bdiR0NG7dB5KTt 8bS2mANlPx+vDXL6DNKQqxaWIAIzTXX2qM7XaqaOLntNXmbIafLEFlQmkZADlODSCfsP sHrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AVuOZddbattcoPTiU8kVVR2IlSzEN7KnRCfoZW6Xl64=; b=cOY4VqC4N0HO6hnZ4qbUJOte22Xf0JccjPF9uUzIFLo8yP8tpnccUIDKATdwOVxf30 SpZK+j6jqUas84Mdy1DLVFtkfWWXYWcwbY4mkB77TF8LYxE1UaTCg9uWgWjWjHReSVPC swuVuFBsUCxd8hzYZ9W/5iZlgoQhGlWfhYDD5yJgWYql1eWQuhSkpdsTgc2Pz3qVfRkW vsnN9sWSJteEeK/an6ns48NMNdu2Z8z5d8F09EDhC96ZF6yvrn2fvFa2ZcfnsR0kUQ0I gMXXT5JxzCOFrq7jpKsvzsaIUage0rvCvMnJehr90QtcDCbHMu3Yqt/ukK81k3DbfZat 9/CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VhixfVJh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units Date: Wed, 17 Feb 2021 12:20:26 -0800 Message-Id: <20210217202036.1724901-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i386, which have 6 register operands. We have, in previous patches, rearranged things such that there are no operations with a label, which have more than one other operand. Which leaves us with a 20-bit field in which to encode a label, giving us a maximum TB size of 512k -- easily large. Change the INDEX_op_tci_movi_{i32,i64} opcodes to tci_mov[il]. The former puts the immediate in the upper 20 bits of the insn, like we do for the label displacement. The later uses a label to reference an entry in the constant pool. Thus, in the worst case we still have a single memory reference for any constant, but now the constants are out-of-line of the bytecode and can be shared between different moves saving space. Change INDEX_op_call to use a label to reference a pair of pointers in the constant pool. This removes the only slightly dodgy link with the layout of struct TCGHelperInfo. The re-encode cannot be done in pieces. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 4 +- tcg/tci/tcg-target.h | 3 +- tcg/tci.c | 534 +++++++++++++++------------------------ tcg/tci/tcg-target.c.inc | 386 +++++++++++++--------------- tcg/tci/README | 20 +- 5 files changed, 380 insertions(+), 567 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index bbb0884af8..5bbec858aa 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -277,8 +277,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #ifdef TCG_TARGET_INTERPRETER /* These opcodes are only for use between the tci generator and interpreter. */ -DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) -DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) #endif #undef TLADDR_ARGS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1558a6e44e..d953f2ead3 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -41,7 +41,7 @@ #define TCG_TARGET_H #define TCG_TARGET_INTERPRETER 1 -#define TCG_TARGET_INSN_UNIT_SIZE 1 +#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #if UINTPTR_MAX == UINT32_MAX @@ -165,6 +165,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 #define HAVE_TCG_QEMU_TB_EXEC +#define TCG_TARGET_NEED_POOL_LABELS /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. diff --git a/tcg/tci.c b/tcg/tci.c index 0b2bc905ea..76bbf440a8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -49,49 +49,6 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) return ((uint64_t)high << 32) + low; } -/* Read constant byte from bytecode. */ -static uint8_t tci_read_b(const uint8_t **tb_ptr) -{ - return *(tb_ptr[0]++); -} - -/* Read register number from bytecode. */ -static TCGReg tci_read_r(const uint8_t **tb_ptr) -{ - uint8_t regno = tci_read_b(tb_ptr); - tci_assert(regno < TCG_TARGET_NB_REGS); - return regno; -} - -/* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) -{ - tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} - -/* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(const uint8_t **tb_ptr) -{ - uint32_t value = *(const uint32_t *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} - -/* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(const uint8_t **tb_ptr) -{ - int32_t value = *(const int32_t *)(*tb_ptr); - *tb_ptr += sizeof(value); - return value; -} - -static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) -{ - return tci_read_i(tb_ptr); -} - /* * Load sets of arguments all at once. The naming convention is: * tci_args_ @@ -106,209 +63,128 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * s = signed ldst offset */ -static void check_size(const uint8_t *start, const uint8_t **tb_ptr) +static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) { - const uint8_t *old_code_ptr = start - 2; - uint8_t op_size = old_code_ptr[1]; - tci_assert(*tb_ptr == old_code_ptr + op_size); + int diff = sextract32(insn, 12, 20); + *l0 = diff ? (void *)tb_ptr + diff : NULL; } -static void tci_args_l(const uint8_t **tb_ptr, void **l0) +static void tci_args_nl(uint32_t insn, const void *tb_ptr, + uint8_t *n0, void **l1) { - const uint8_t *start = *tb_ptr; - - *l0 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *n0 = extract32(insn, 8, 4); + *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; } -static void tci_args_nl(const uint8_t **tb_ptr, uint8_t *n0, void **l1) +static void tci_args_rl(uint32_t insn, const void *tb_ptr, + TCGReg *r0, void **l1) { - const uint8_t *start = *tb_ptr; - - *n0 = tci_read_b(tb_ptr); - *l1 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; } -static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1) +static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *l1 = (void *)tci_read_label(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); } -static void tci_args_rr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1) +static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *i1 = sextract32(insn, 12, 20); } -static void tci_args_ri(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrm(uint32_t insn, TCGReg *r0, + TCGReg *r1, TCGMemOpIdx *m2) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *i1 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *m2 = extract32(insn, 20, 12); } -#if TCG_TARGET_REG_BITS == 64 -static void tci_args_rI(const uint8_t **tb_ptr, - TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *i1 = tci_read_i(tb_ptr); - - check_size(start, tb_ptr); -} -#endif - -static void tci_args_rrm(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *m2 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); } -static void tci_args_rrr(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, TCGReg *r2) +static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *i2 = sextract32(insn, 16, 16); } -static void tci_args_rrs(const uint8_t **tb_ptr, - TCGReg *r0, TCGReg *r1, int32_t *i2) -{ - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *i2 = tci_read_s32(tb_ptr); - - check_size(start, tb_ptr); -} - -static void tci_args_rrrc(const uint8_t **tb_ptr, +static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *c3 = tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *c3 = extract32(insn, 20, 4); } -static void tci_args_rrrm(const uint8_t **tb_ptr, +static void tci_args_rrrm(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *m3 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *m3 = extract32(insn, 20, 12); } -static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *i3 = tci_read_b(tb_ptr); - *i4 = tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *i3 = extract32(insn, 20, 6); + *i4 = extract32(insn, 26, 6); } -static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, - TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4) +static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, + TCGReg *r2, TCGReg *r3, TCGReg *r4) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *m4 = tci_read_i32(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); + *r4 = extract32(insn, 24, 4); } #if TCG_TARGET_REG_BITS == 32 -static void tci_args_rrrr(const uint8_t **tb_ptr, +static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); } -static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *r4 = tci_read_r(tb_ptr); - *c5 = tci_read_b(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); + *r4 = extract32(insn, 24, 4); + *c5 = extract32(insn, 28, 4); } -static void tci_args_rrrrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, +static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { - const uint8_t *start = *tb_ptr; - - *r0 = tci_read_r(tb_ptr); - *r1 = tci_read_r(tb_ptr); - *r2 = tci_read_r(tb_ptr); - *r3 = tci_read_r(tb_ptr); - *r4 = tci_read_r(tb_ptr); - *r5 = tci_read_r(tb_ptr); - - check_size(start, tb_ptr); + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *r2 = extract32(insn, 16, 4); + *r3 = extract32(insn, 20, 4); + *r4 = extract32(insn, 24, 4); + *r5 = extract32(insn, 28, 4); } #endif @@ -447,7 +323,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - const uint8_t *tb_ptr = v_tb_ptr; + const uint32_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; @@ -459,8 +335,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_assert(tb_ptr); for (;;) { - TCGOpcode opc = tb_ptr[0]; - TCGReg r0, r1, r2, r3; + uint32_t insn; + TCGOpcode opc; + TCGReg r0, r1, r2, r3, r4; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; @@ -468,23 +345,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 - TCGReg r4, r5; + TCGReg r5; uint64_t T1, T2; #endif TCGMemOpIdx oi; int32_t ofs; void *ptr; - /* Skip opcode and size entry. */ - tb_ptr += 2; + insn = *tb_ptr++; + opc = extract32(insn, 0, 8); switch (opc) { case INDEX_op_call: - /* - * We are passed a pointer to the TCGHelperInfo, which contains - * the function pointer followed by the ffi_cif pointer. - */ - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); /* Helper functions may need to access the "return address" */ tci_tb_ptr = (uintptr_t)tb_ptr; @@ -502,8 +375,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } /* - * Call the helper function. Any result winds up - * "left-aligned" in the stack[0] slot. + * We are passed a pointer into the constant pool, which + * contains a pair of the function pointer and the cif pointer. + * Any result winds up "left-aligned" in the stack[0] slot. */ { void **pptr = ptr; @@ -535,76 +409,80 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; case INDEX_op_br: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr = ptr; continue; case INDEX_op_setcond_i32: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare32(regs[r1], regs[r2], condition); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); T1 = tci_uint64(regs[r2], regs[r1]); T2 = tci_uint64(regs[r4], regs[r3]); regs[r0] = tci_compare64(T1, T2, condition); break; #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &condition); + tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare64(regs[r1], regs[r2], condition); break; #endif CASE_32_64(mov) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = regs[r1]; break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &t1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &t1); regs[r0] = t1; break; + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + regs[r0] = *(tcg_target_ulong *)ptr; + break; /* Load/store operations (32 bit). */ CASE_32_64(ld8u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint8_t *)ptr; break; CASE_32_64(ld8s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(int8_t *)ptr; break; CASE_32_64(ld16u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint16_t *)ptr; break; CASE_32_64(ld16s) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(int16_t *)ptr; break; case INDEX_op_ld_i32: CASE_64(ld32u) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint32_t *)ptr; break; CASE_32_64(st8) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint8_t *)ptr = regs[r0]; break; CASE_32_64(st16) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint16_t *)ptr = regs[r0]; break; case INDEX_op_st_i32: CASE_64(st32) - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint32_t *)ptr = regs[r0]; break; @@ -612,171 +490,166 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (mixed 32/64 bit). */ CASE_32_64(add) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] + regs[r2]; break; CASE_32_64(sub) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] - regs[r2]; break; CASE_32_64(mul) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] * regs[r2]; break; CASE_32_64(and) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] & regs[r2]; break; CASE_32_64(or) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] | regs[r2]; break; CASE_32_64(xor) - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] ^ regs[r2]; break; /* Arithmetic operations (32 bit). */ case INDEX_op_div_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; break; case INDEX_op_divu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; break; case INDEX_op_rem_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; break; case INDEX_op_remu_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; /* Shift/rotate operations (32 bit). */ case INDEX_op_shl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); break; case INDEX_op_shr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); break; case INDEX_op_sar_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = rol32(regs[r1], regs[r2] & 31); break; case INDEX_op_rotr_i32: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = ror32(regs[r1], regs[r2] & 31); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if ((uint32_t)regs[r0]) { tb_ptr = ptr; } break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (int8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 CASE_32_64(ext16s) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (int16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 CASE_32_64(ext8u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (uint8_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 CASE_32_64(ext16u) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (uint16_t)regs[r1]; break; #endif #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 CASE_32_64(bswap16) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = bswap16(regs[r1]); break; #endif #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 CASE_32_64(bswap32) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = bswap32(regs[r1]); break; #endif #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 CASE_32_64(not) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = ~regs[r1]; break; #endif #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 CASE_32_64(neg) - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = -regs[r1]; break; #endif #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &t1); - regs[r0] = t1; - break; - /* Load/store operations (64 bit). */ case INDEX_op_ld32s_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(int32_t *)ptr; break; case INDEX_op_ld_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); regs[r0] = *(uint64_t *)ptr; break; case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &ofs); + tci_args_rrs(insn, &r0, &r1, &ofs); ptr = (void *)(regs[r1] + ofs); *(uint64_t *)ptr = regs[r0]; break; @@ -784,71 +657,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (64 bit). */ case INDEX_op_div_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; break; case INDEX_op_divu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; break; case INDEX_op_rem_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; break; case INDEX_op_remu_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; /* Shift/rotate operations (64 bit). */ case INDEX_op_shl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] << (regs[r2] & 63); break; case INDEX_op_shr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] >> (regs[r2] & 63); break; case INDEX_op_sar_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = rol64(regs[r1], regs[r2] & 63); break; case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = ror64(regs[r1], regs[r2] & 63); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); if (regs[r0]) { tb_ptr = ptr; } break; case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (int32_t)regs[r1]; break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = (uint32_t)regs[r1]; break; #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); regs[r0] = bswap64(regs[r1]); break; #endif @@ -857,20 +730,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* QEMU specific operations. */ case INDEX_op_exit_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); return (uintptr_t)ptr; case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); tb_ptr = *(void **)ptr; break; case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { @@ -906,14 +779,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_ld_i64: if (TCG_TARGET_REG_BITS == 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr = tci_uint64(regs[r3], regs[r2]); + oi = regs[r4]; } switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -964,10 +838,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_st_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; } else { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } tmp32 = regs[r0]; @@ -994,16 +868,17 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_qemu_st_i64: if (TCG_TARGET_REG_BITS == 64) { - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; tmp64 = regs[r0]; } else { if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = regs[r2]; } else { - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr = tci_uint64(regs[r3], regs[r2]); + oi = regs[r4]; } tmp64 = tci_uint64(regs[r1], regs[r0]); } @@ -1087,14 +962,14 @@ static const char *str_c(TCGCond c) /* Disassemble TCI bytecode. */ int print_insn_tci(bfd_vma addr, disassemble_info *info) { - uint8_t buf[256]; - int length, status; + const uint32_t *tb_ptr = (const void *)(uintptr_t)addr; const TCGOpDef *def; const char *op_name; + uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3; + TCGReg r0, r1, r2, r3, r4; #if TCG_TARGET_REG_BITS == 32 - TCGReg r4, r5; + TCGReg r5; #endif tcg_target_ulong i1; int32_t s2; @@ -1102,71 +977,54 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) TCGMemOpIdx oi; uint8_t pos, len; void *ptr; - const uint8_t *tb_ptr; - status = info->read_memory_func(addr, buf, 2, info); - if (status != 0) { - info->memory_error_func(status, addr, info); - return -1; - } - op = buf[0]; - length = buf[1]; + /* TCI is always the host, so we don't need to load indirect. */ + insn = *tb_ptr++; - if (length < 2) { - info->fprintf_func(info->stream, "invalid length %d", length); - return 1; - } - - status = info->read_memory_func(addr + 2, buf + 2, length - 2, info); - if (status != 0) { - info->memory_error_func(status, addr + 2, info); - return -1; - } + info->fprintf_func(info->stream, "%08x ", insn); + op = extract32(insn, 0, 8); def = &tcg_op_defs[op]; op_name = def->name; - tb_ptr = buf + 2; switch (op) { case INDEX_op_br: case INDEX_op_exit_tb: case INDEX_op_goto_tb: - tci_args_l(&tb_ptr, &ptr); + tci_args_l(insn, tb_ptr, &ptr); info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; case INDEX_op_call: - tci_args_nl(&tb_ptr, &len, &ptr); + tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr); break; case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - tci_args_rl(&tb_ptr, &r0, &ptr); + tci_args_rl(insn, tb_ptr, &r0, &ptr); info->fprintf_func(info->stream, "%-12s %s,0,ne,%p", op_name, str_r(r0), ptr); break; case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: - tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c); + tci_args_rrrc(insn, &r0, &r1, &r2, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); break; - case INDEX_op_tci_movi_i32: - tci_args_ri(&tb_ptr, &r0, &i1); + case INDEX_op_tci_movi: + tci_args_ri(insn, &r0, &i1); info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", op_name, str_r(r0), i1); break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_tci_movi_i64: - tci_args_rI(&tb_ptr, &r0, &i1); - info->fprintf_func(info->stream, "%-12s %s,0x%" TCG_PRIlx "", - op_name, str_r(r0), i1); + case INDEX_op_tci_movl: + tci_args_rl(insn, tb_ptr, &r0, &ptr); + info->fprintf_func(info->stream, "%-12s %s,%p", + op_name, str_r(r0), ptr); break; -#endif case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -1187,7 +1045,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: - tci_args_rrs(&tb_ptr, &r0, &r1, &s2); + tci_args_rrs(insn, &r0, &r1, &s2); info->fprintf_func(info->stream, "%-12s %s,%s,%d", op_name, str_r(r0), str_r(r1), s2); break; @@ -1214,7 +1072,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: - tci_args_rr(&tb_ptr, &r0, &r1); + tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); break; @@ -1249,28 +1107,28 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - tci_args_rrr(&tb_ptr, &r0, &r1, &r2); + tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); break; case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%d,%d", op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: - tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c); + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_c(c)); break; case INDEX_op_mulu2_i32: - tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); @@ -1278,7 +1136,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5); + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); @@ -1296,30 +1154,38 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); switch (len) { case 2: - tci_args_rrm(&tb_ptr, &r0, &r1, &oi); + tci_args_rrm(insn, &r0, &r1, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%x", op_name, str_r(r0), str_r(r1), oi); break; case 3: - tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi); + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%x", op_name, str_r(r0), str_r(r1), str_r(r2), oi); break; case 4: - tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi); - info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%x", + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); + info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), - str_r(r2), str_r(r3), oi); + str_r(r2), str_r(r3), str_r(r4)); break; default: g_assert_not_reached(); } break; + case 0: + /* tcg_out_nop_fill uses zeros */ + if (insn == 0) { + info->fprintf_func(info->stream, "align"); + break; + } + /* fall through */ + default: info->fprintf_func(info->stream, "illegal opcode %d", op); break; } - return length; + return sizeof(insn); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e06d4e9380..0df8384be7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -22,20 +22,7 @@ * THE SOFTWARE. */ -/* TODO list: - * - See TODO comments in code. - */ - -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - -/* Bitfield n...m (in 32 bit value). */ -#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) +#include "../tcg-pool.c.inc" static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { @@ -226,52 +213,16 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - /* tcg_out_reloc always uses the same type, addend. */ - tcg_debug_assert(type == sizeof(tcg_target_long)); + intptr_t diff = value - (intptr_t)(code_ptr + 1); + tcg_debug_assert(addend == 0); - tcg_debug_assert(value != 0); - if (TCG_TARGET_REG_BITS == 32) { - tcg_patch32(code_ptr, value); - } else { - tcg_patch64(code_ptr, value); - } - return true; -} - -/* Write value (native size). */ -static void tcg_out_i(TCGContext *s, tcg_target_ulong v) -{ - if (TCG_TARGET_REG_BITS == 32) { - tcg_out32(s, v); - } else { - tcg_out64(s, v); - } -} - -/* Write opcode. */ -static void tcg_out_op_t(TCGContext *s, TCGOpcode op) -{ - tcg_out8(s, op); - tcg_out8(s, 0); -} - -/* Write register. */ -static void tcg_out_r(TCGContext *s, TCGArg t0) -{ - tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); - tcg_out8(s, t0); -} - -/* Write label. */ -static void tci_out_label(TCGContext *s, TCGLabel *label) -{ - if (label->has_value) { - tcg_out_i(s, label->u.value); - tcg_debug_assert(label->u.value); - } else { - tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); - s->code_ptr += sizeof(tcg_target_ulong); + tcg_debug_assert(type == 20); + + if (diff == sextract32(diff, 0, type)) { + tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff)); + return true; } + return false; } static void stack_bounds_check(TCGReg base, target_long offset) @@ -285,251 +236,236 @@ static void stack_bounds_check(TCGReg base, target_long offset) static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tci_out_label(s, l0); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l0, 0); + insn = deposit32(insn, 0, 8, op); + tcg_out32(s, insn); } static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; + intptr_t diff; - tcg_out_op_t(s, op); - tcg_out_i(s, (uintptr_t)p0); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + /* Special case for exit_tb: map null -> 0. */ + if (p0 == NULL) { + diff = 0; + } else { + diff = p0 - (void *)(s->code_ptr + 1); + tcg_debug_assert(diff != 0); + if (diff != sextract32(diff, 0, 20)) { + tcg_raise_tb_overflow(s); + } + } + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 12, 20, diff); + tcg_out32(s, insn); } static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - -static void tcg_out_op_np(TCGContext *s, TCGOpcode op, - uint8_t n0, const void *p1) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out8(s, n0); - tcg_out_i(s, (uintptr_t)p1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out32(s, (uint8_t)op); } static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out32(s, i1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(i1 == sextract32(i1, 0, 20)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 20, i1); + tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_op_rI(TCGContext *s, TCGOpcode op, - TCGReg r0, uint64_t i1) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out64(s, i1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} -#endif - static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tci_out_label(s, l1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_reloc(s, s->code_ptr, 20, l1, 0); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); } static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + tcg_out32(s, insn); } static void tcg_out_op_rrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGArg m2) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out32(s, m2); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(m2 == extract32(m2, 0, 12)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 20, 12, m2); + tcg_out32(s, insn); } static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + tcg_out32(s, insn); } static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, intptr_t i2) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_debug_assert(i2 == (int32_t)i2); - tcg_out32(s, i2); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(i2 == sextract32(i2, 0, 16)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 16, i2); + tcg_out32(s, insn); } static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, c3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, c3); + tcg_out32(s, insn); } static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out32(s, m3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(m3 == extract32(m3, 0, 12)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 12, m3); + tcg_out32(s, insn); } static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out8(s, b3); - tcg_out8(s, b4); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_debug_assert(b3 == extract32(b3, 0, 6)); + tcg_debug_assert(b4 == extract32(b4, 0, 6)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 6, b3); + insn = deposit32(insn, 26, 6, b4); + tcg_out32(s, insn); } -static void tcg_out_op_rrrrm(TCGContext *s, TCGOpcode op, TCGReg r0, - TCGReg r1, TCGReg r2, TCGReg r3, TCGArg m4) +static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out32(s, m4); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + insn = deposit32(insn, 24, 4, r4); + tcg_out32(s, insn); } #if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + tcg_out32(s, insn); } static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out8(s, c5); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + insn = deposit32(insn, 24, 4, r4); + insn = deposit32(insn, 28, 4, c5); + tcg_out32(s, insn); } static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) { - uint8_t *old_code_ptr = s->code_ptr; + tcg_insn_unit insn = 0; - tcg_out_op_t(s, op); - tcg_out_r(s, r0); - tcg_out_r(s, r1); - tcg_out_r(s, r2); - tcg_out_r(s, r3); - tcg_out_r(s, r4); - tcg_out_r(s, r5); - - old_code_ptr[1] = s->code_ptr - old_code_ptr; + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 4, r2); + insn = deposit32(insn, 20, 4, r3); + insn = deposit32(insn, 24, 4, r4); + insn = deposit32(insn, 28, 4, r5); + tcg_out32(s, insn); } #endif +static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, + TCGReg base, intptr_t offset) +{ + stack_bounds_check(base, offset); + if (offset != sextract32(offset, 0, 16)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset); + tcg_out_op_rrr(s, (TCG_TARGET_REG_BITS == 32 + ? INDEX_op_add_i32 : INDEX_op_add_i64), + TCG_REG_TMP, TCG_REG_TMP, base); + base = TCG_REG_TMP; + offset = 0; + } + tcg_out_op_rrs(s, op, val, base, offset); +} + static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, intptr_t offset) { - stack_bounds_check(base, offset); switch (type) { case TCG_TYPE_I32: - tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i32, val, base, offset); break; #if TCG_TARGET_REG_BITS == 64 case TCG_TYPE_I64: - tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); + tcg_out_ldst(s, INDEX_op_ld_i64, val, base, offset); break; #endif default: @@ -559,22 +495,33 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { switch (type) { case TCG_TYPE_I32: - tcg_out_op_ri(s, INDEX_op_tci_movi_i32, ret, arg); - break; #if TCG_TARGET_REG_BITS == 64 + arg = (int32_t)arg; + /* fall through */ case TCG_TYPE_I64: - tcg_out_op_rI(s, INDEX_op_tci_movi_i64, ret, arg); - break; #endif + break; default: g_assert_not_reached(); } + + if (arg == sextract32(arg, 0, 20)) { + tcg_out_op_ri(s, INDEX_op_tci_movi, ret, arg); + } else { + tcg_insn_unit insn = 0; + + new_pool_label(s, arg, 20, s->code_ptr, 0); + insn = deposit32(insn, 0, 8, INDEX_op_tci_movl); + insn = deposit32(insn, 8, 4, ret); + tcg_out32(s, insn); + } } static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { const TCGHelperInfo *info; uint8_t which; + tcg_insn_unit insn = 0; info = g_hash_table_lookup(helper_table, (gpointer)arg); if (info->cif->rtype == &ffi_type_void) { @@ -586,7 +533,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) which = 2; } - tcg_out_op_np(s, INDEX_op_call, which, info); + new_pool_l2(s, 20, s->code_ptr, 0, + (uintptr_t)info->func, (uintptr_t)info->cif); + insn = deposit32(insn, 0, 8, INDEX_op_call); + insn = deposit32(insn, 8, 4, which); + tcg_out32(s, insn); } #if TCG_TARGET_REG_BITS == 64 @@ -644,8 +595,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_st_i32: CASE_64(st32) CASE_64(st) - stack_bounds_check(args[1], args[2]); - tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); + tcg_out_ldst(s, opc, args[0], args[1], args[2]); break; CASE_32_64(add) @@ -738,8 +688,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } else { - tcg_out_op_rrrrm(s, opc, args[0], args[1], - args[2], args[3], args[4]); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]); + tcg_out_op_rrrrr(s, opc, args[0], args[1], + args[2], args[3], TCG_REG_TMP); } break; @@ -787,6 +738,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return arg_ct->ct & TCG_CT_CONST; } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, sizeof(*p) * count); +} + static void tcg_target_init(TCGContext *s) { #if defined(CONFIG_DEBUG_TCG_INTERPRETER) diff --git a/tcg/tci/README b/tcg/tci/README index 9bb7d7a5d3..f72a40a395 100644 --- a/tcg/tci/README +++ b/tcg/tci/README @@ -23,10 +23,12 @@ This is what TCI (Tiny Code Interpreter) does. Like each TCG host frontend, TCI implements the code generator in tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci. -The additional file tcg/tci.c adds the interpreter. +The additional file tcg/tci.c adds the interpreter and disassembler. -The bytecode consists of opcodes (same numeric values as those used by -TCG), command length and arguments of variable size and number. +The bytecode consists of opcodes (with only a few exceptions, with +the same same numeric values and semantics as used by TCG), and up +to six arguments packed into a 32-bit integer. See comments in tci.c +for details on the encoding. 3) Usage @@ -39,11 +41,6 @@ suggest using this option. Setting it automatically would need additional code in configure which must be fixed when new native TCG implementations are added. -System emulation should work on any 32 or 64 bit host. -User mode emulation might work. Maybe a new linker script (*.ld) -is needed. Byte order might be wrong (on big endian hosts) -and need fixes in configure. - For hosts with native TCG, the interpreter TCI can be enabled by configure --enable-tcg-interpreter @@ -118,13 +115,6 @@ u1 = linux-user-test works in the interpreter. These opcodes raise a runtime exception, so it is possible to see where code must be added. -* The pseudo code is not optimized and still ugly. For hosts with special - alignment requirements, it needs some fixes (maybe aligned bytecode - would also improve speed for hosts which support byte alignment). - -* A better disassembler for the pseudo code would be nice (a very primitive - disassembler is included in tcg-target.c.inc). - * It might be useful to have a runtime option which selects the native TCG or TCI, so QEMU would have to include two TCGs. Today, selecting TCI is a configure option, so you need two compilations of QEMU. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 62/71] tcg/tci: Implement goto_ptr Date: Wed, 17 Feb 2021 12:20:27 -0800 Message-Id: <20210217202036.1724901-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-con-set.h | 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c | 2 ++ tcg/tci.c | 19 +++++++++++++++++++ tcg/tci/tcg-target.c.inc | 16 ++++++++++++++++ 5 files changed, 39 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 316730f32c..ae2dc3b844 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -9,6 +9,7 @@ * Each operand should be a sequence of constraint letters as defined by * tcg-target-con-str.h; the constraint combination is inclusive or. */ +C_O0_I1(r) C_O0_I2(r, r) C_O0_I3(r, r, r) C_O0_I4(r, r, r, r) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d953f2ead3..17911d3297 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -86,7 +86,7 @@ #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 diff --git a/tcg/tcg.c b/tcg/tcg.c index 92aec0d238..ce80adcfbe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1314,10 +1314,12 @@ void tcg_prologue_init(TCGContext *s) } #endif +#ifndef CONFIG_TCG_INTERPRETER /* Assert that goto_ptr is implemented completely. */ if (TCG_TARGET_HAS_goto_ptr) { tcg_debug_assert(tcg_code_gen_epilogue != NULL); } +#endif } void tcg_func_start(TCGContext *s) diff --git a/tcg/tci.c b/tcg/tci.c index 76bbf440a8..c229050c66 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -69,6 +69,11 @@ static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) *l0 = diff ? (void *)tb_ptr + diff : NULL; } +static void tci_args_r(uint32_t insn, TCGReg *r0) +{ + *r0 = extract32(insn, 8, 4); +} + static void tci_args_nl(uint32_t insn, const void *tb_ptr, uint8_t *n0, void **l1) { @@ -738,6 +743,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tb_ptr = *(void **)ptr; break; + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + ptr = (void *)regs[r0]; + if (!ptr) { + return 0; + } + tb_ptr = ptr; + break; + case INDEX_op_qemu_ld_i32: if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); @@ -995,6 +1009,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); break; + case INDEX_op_goto_ptr: + tci_args_r(insn, &r0); + info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); + break; + case INDEX_op_call: tci_args_nl(insn, tb_ptr, &len, &ptr); info->fprintf_func(info->stream, "%-12s %d,%p", op_name, len, ptr); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 0df8384be7..db29bc6e54 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -27,6 +27,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { + case INDEX_op_goto_ptr: + return C_O0_I1(r); + case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -263,6 +266,15 @@ static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) tcg_out32(s, insn); } +static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) +{ + tcg_insn_unit insn = 0; + + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + tcg_out32(s, insn); +} + static void tcg_out_op_v(TCGContext *s, TCGOpcode op) { tcg_out32(s, (uint8_t)op); @@ -567,6 +579,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_goto_ptr: + tcg_out_op_r(s, opc, args[0]); + break; + case INDEX_op_br: tcg_out_op_l(s, opc, arg_label(args[0])); break; From patchwork Wed Feb 17 20:20:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383911 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3142928jao; Wed, 17 Feb 2021 13:19:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJz3XZfr6eUn+HVjCVG8/uH3ncdaaueJ4W9x4TowesAuQIcUk18QdBjvNjNMrH7+4newkeJ/ X-Received: by 2002:a25:cc46:: with SMTP id l67mr2421772ybf.16.1613596768585; Wed, 17 Feb 2021 13:19:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596768; cv=none; d=google.com; s=arc-20160816; b=CFlx43PbjlpChyfzb27niMrxkEZCsp/IPBwZBj04qx6voi+c4i1GnICnTIIblEtd5N ixVJetVKrqb6wj+SGVHDPa13Zdufb81yfFUaKIb/XiO/4QuEUvvkPir2s1krb6dCItAx qmo4dYuXZu9kadA9ols1gPDJUbECZIy30JqKJ4CGDjfOvim7DVdbGL+C98ecBhVd0lhm b4S3/H+IYHRuQK8In1tPI6SMfduC9lPv+vt1ow/zTm1gAejH94n5TnPbIU6kdjFyCG7H zy/ubCvimVZuEk3N/pc1hMii/i6BNykOR8iAraSsxH4MtwzYRLCUQ0RcrJsNtXK2JDWZ qBvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=t8YgkJ1JSVwTBJ9tGciCHNpn3ZeG9bxQ1lhsPKyTifo=; b=AxW8W4W7GOyv4M0Zi5WKeqHMGZr44GOgYNdiioZ9SJDzvN6rW/Buo9kqJMQ2sWwqt9 h5uYxR8q69cePsitC/vIvHFXBFSGPguQuHetBcIonnkWSbJKh7DmZyyeHFXak0SFJnsR D9/Xtr4e/pu7JXvtOf16piHQ1/aJkunK74NYO5j6BLc+L/Ds9Fwum6+KjZvMlOWff5tV ytd6o8nx7wAICOmj5cXpGXIdSk755zkRDxAg1h9+RxPXsHEDy9Qgzz6u7OWzLcaeQAt+ ruwNTt9oVbRgmzsBXtxQg/+pQ030BsT+vlUUOt/uZN0S19lAKdPgjzBpBZ5b1M3XlveL 3pOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ymO3OERG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 63/71] tcg/tci: Implement movcond Date: Wed, 17 Feb 2021 12:20:28 -0800 Message-Id: <20210217202036.1724901-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c | 16 +++++++++++++++- tcg/tci/tcg-target.c.inc | 10 +++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 17911d3297..f53773a555 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -82,7 +82,7 @@ #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 @@ -119,7 +119,7 @@ #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 diff --git a/tcg/tci.c b/tcg/tci.c index c229050c66..2391dd4d3b 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -169,6 +169,7 @@ static void tci_args_rrrr(uint32_t insn, *r2 = extract32(insn, 16, 4); *r3 = extract32(insn, 20, 4); } +#endif static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) @@ -181,6 +182,7 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, *c5 = extract32(insn, 28, 4); } +#if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -421,6 +423,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare32(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i32: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 = tci_compare32(regs[r1], regs[r2], condition); + regs[r0] = regs[tmp32 ? r3 : r4]; + break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); @@ -433,6 +440,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrc(insn, &r0, &r1, &r2, &condition); regs[r0] = tci_compare64(regs[r1], regs[r2], condition); break; + case INDEX_op_movcond_i64: + tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); + tmp32 = tci_compare64(regs[r1], regs[r2], condition); + regs[r0] = regs[tmp32 ? r3 : r4]; + break; #endif CASE_32_64(mov) tci_args_rr(insn, &r0, &r1); @@ -1138,7 +1150,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); break; -#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", @@ -1146,6 +1159,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r3), str_r(r4), str_c(c)); break; +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index db29bc6e54..a0c458a60a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -133,9 +133,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); +#endif + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, r, r); -#endif case INDEX_op_qemu_ld_i32: return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS @@ -419,6 +422,7 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } +#endif static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -436,6 +440,7 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } +#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -591,12 +596,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_op_rrrc(s, opc, args[0], args[1], args[2], args[3]); break; -#if TCG_TARGET_REG_BITS == 32 + CASE_32_64(movcond) case INDEX_op_setcond2_i32: tcg_out_op_rrrrrc(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; -#endif CASE_32_64(ld8u) CASE_32_64(ld8s) From patchwork Wed Feb 17 20:20:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383912 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3143110jao; Wed, 17 Feb 2021 13:19:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJxa0GBS4yxELivI8pNP9CMx8uzFQU9HWbr+jandkjBXP6ng4ed1Lvx5kZnmQ7KBx0y+FJrR X-Received: by 2002:a5b:488:: with SMTP id n8mr2168498ybp.224.1613596787763; Wed, 17 Feb 2021 13:19:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613596787; cv=none; d=google.com; s=arc-20160816; b=m6quySxdeqwDf+Rf2hxZyR7vUhzV5u9RqebGcGfLnXq/zWyK4GKKjUJZ7P3MXYMLt8 p3Bq03ypwCgMTZCoJJV4n5SVMVIRvOvDndLeqQPjJgRQ5EAAmivwJq/vYzZPkILys59b SokvJJlzJ1EbN8zMGMhM2hO4Nn+NZHzoFP8jBunwOP/bO8kYxHNPvioTlZdZZH9Ohq3E CxilcTs19B/jlUdWngQa98QNLxxTXYbHyFSp4JY99Z8dvxxPlRuqmewnQHxHEw59p4uf r2DwNfxD7ZNVhupcpbt49PHpNS8BJ6mMda36Eyxw93b8TmW6EKF33mIH++4/AfVxhGDE oNpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8UhCzfaKYlwmE690TaVTdGnsli7nQ9Ath2fy3ZA2wa8=; b=px558AofyEpmWNcK1DE8uKqeEhsNXOSQ8Ku0k6XU5rmxk6fgyEOWlqmpFqkYvu+eB3 MZfB0lLIArIUzjAPPrTDI+X61ImuRuJEYnAaKulh6y5VB0KlRM1iwait8opckvf5JNVG XGmPrV1t+fNe7iMQ37sLn1fOtVkWnSsJXrhggUmzc/Y+vNvWvGnt0yK98KfIkaZgn4H3 qFkZCE+pUy9GL3lHqovuDh0qXxrDqAi7jB/5yuMN6c2fwshBrov5z7QCCERGYcyisNqt 8n0hUxNe66IFLovMFiS67ut6tDJnufoAmcfysVKYS9CAPYsJatXGOS4WjRPa9j1CVMCb +a1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AP3b9Fxb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor Date: Wed, 17 Feb 2021 12:20:29 -0800 Message-Id: <20210217202036.1724901-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These were already present in tcg-target.c.inc, but not in the interpreter. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 20 ++++++++++---------- tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f53773a555..5945272a43 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -67,20 +67,20 @@ #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 0 @@ -108,16 +108,16 @@ #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_clz_i64 0 #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index 2391dd4d3b..02fad3370d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -530,6 +530,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] ^ regs[r2]; break; +#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 + CASE_32_64(andc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] & ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 + CASE_32_64(orc) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] | ~regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 + CASE_32_64(eqv) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = ~(regs[r1] ^ regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 + CASE_32_64(nand) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = ~(regs[r1] & regs[r2]); + break; +#endif +#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 + CASE_32_64(nor) + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = ~(regs[r1] | regs[r2]); + break; +#endif /* Arithmetic operations (32 bit). */ @@ -1120,6 +1150,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: case INDEX_op_div_i32: case INDEX_op_div_i64: case INDEX_op_rem_i32: From patchwork Wed Feb 17 20:20:30 2021 Content-Type: text/plain; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 65/71] tcg/tci: Implement extract, sextract Date: Wed, 17 Feb 2021 12:20:30 -0800 Message-Id: <20210217202036.1724901-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 42 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 5945272a43..60b67b196b 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -69,8 +69,8 @@ #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_andc_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 1 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 @@ -97,8 +97,8 @@ #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 1 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index 02fad3370d..dcf8dc418f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -122,6 +122,15 @@ static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) *i2 = sextract32(insn, 16, 16); } +static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, + uint8_t *i2, uint8_t *i3) +{ + *r0 = extract32(insn, 8, 4); + *r1 = extract32(insn, 12, 4); + *i2 = extract32(insn, 16, 6); + *i3 = extract32(insn, 22, 6); +} + static void tci_args_rrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) { @@ -609,6 +618,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i32 + case INDEX_op_extract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = extract32(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i32 + case INDEX_op_sextract_i32: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = sextract32(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i32: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -749,6 +770,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; +#endif +#if TCG_TARGET_HAS_extract_i64 + case INDEX_op_extract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = extract64(regs[r1], pos, len); + break; +#endif +#if TCG_TARGET_HAS_sextract_i64 + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + regs[r0] = sextract64(regs[r1], pos, len); + break; #endif case INDEX_op_brcond_i64: tci_args_rl(insn, tb_ptr, &r0, &ptr); @@ -1190,6 +1223,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); break; + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + tci_args_rrbb(insn, &r0, &r1, &pos, &len); + info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", + op_name, str_r(r0), str_r(r1), pos, len); + break; + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index a0c458a60a..cedd0328df 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -63,6 +63,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: case INDEX_op_bswap64_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32: @@ -352,6 +356,21 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } +static void tcg_out_op_rrbb(TCGContext *s, TCGOpcode op, TCGReg r0, + TCGReg r1, uint8_t b2, uint8_t b3) +{ + tcg_insn_unit insn = 0; + + tcg_debug_assert(b2 == extract32(b2, 0, 6)); + tcg_debug_assert(b3 == extract32(b3, 0, 6)); + insn = deposit32(insn, 0, 8, op); + insn = deposit32(insn, 8, 4, r0); + insn = deposit32(insn, 12, 4, r1); + insn = deposit32(insn, 16, 6, b2); + insn = deposit32(insn, 22, 6, b3); + tcg_out32(s, insn); +} + static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3) { @@ -653,6 +672,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; + CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */ + CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */ + { + TCGArg pos = args[2], len = args[3]; + TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32; + + tcg_debug_assert(pos < max); + tcg_debug_assert(pos + len <= max); + + tcg_out_op_rrbb(s, opc, args[0], args[1], pos, len); + } + break; + CASE_32_64(brcond) tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32 ? 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 66/71] tcg/tci: Implement clz, ctz, ctpop Date: Wed, 17 Feb 2021 12:20:31 -0800 Message-Id: <20210217202036.1724901-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 12 +++++------ tcg/tci.c | 44 ++++++++++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.c.inc | 9 ++++++++ 3 files changed, 59 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 60b67b196b..59859bd8a6 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -75,9 +75,9 @@ #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_orc_i32 1 @@ -112,9 +112,9 @@ #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_orc_i64 1 diff --git a/tcg/tci.c b/tcg/tci.c index dcf8dc418f..068d742a80 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -588,6 +588,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i32 + case INDEX_op_clz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 = regs[r1]; + regs[r0] = tmp32 ? clz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i32 + case INDEX_op_ctz_i32: + tci_args_rrr(insn, &r0, &r1, &r2); + tmp32 = regs[r1]; + regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i32 + case INDEX_op_ctpop_i32: + tci_args_rr(insn, &r0, &r1); + regs[r0] = ctpop32(regs[r1]); + break; +#endif /* Shift/rotate operations (32 bit). */ @@ -740,6 +760,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; break; +#if TCG_TARGET_HAS_clz_i64 + case INDEX_op_clz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctz_i64 + case INDEX_op_ctz_i64: + tci_args_rrr(insn, &r0, &r1, &r2); + regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; + break; +#endif +#if TCG_TARGET_HAS_ctpop_i64 + case INDEX_op_ctpop_i64: + tci_args_rr(insn, &r0, &r1); + regs[r0] = ctpop64(regs[r1]); + break; +#endif /* Shift/rotate operations (64 bit). */ @@ -1166,6 +1204,8 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_not_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: tci_args_rr(insn, &r0, &r1); info->fprintf_func(info->stream, "%-12s %s,%s", op_name, str_r(r0), str_r(r1)); @@ -1211,6 +1251,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: tci_args_rrr(insn, &r0, &r1, &r2); info->fprintf_func(info->stream, "%-12s %s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2)); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cedd0328df..664d715440 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -67,6 +67,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_extract_i64: case INDEX_op_sextract_i32: case INDEX_op_sextract_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32: @@ -122,6 +124,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_setcond_i64: case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: return C_O1_I2(r, r, r); case INDEX_op_brcond_i32: @@ -657,6 +663,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(clz) /* Optional (TCG_TARGET_HAS_clz_*). */ + CASE_32_64(ctz) /* Optional (TCG_TARGET_HAS_ctz_*). */ tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); break; @@ -705,6 +713,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ tcg_out_op_rr(s, opc, args[0], args[1]); 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2 Date: Wed, 17 Feb 2021 12:20:32 -0800 Message-Id: <20210217202036.1724901-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 35 +++++++++++++++++++++++++++++------ tcg/tci/tcg-target.c.inc | 16 ++++++++++------ 3 files changed, 43 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 59859bd8a6..71a44bbfb0 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -83,7 +83,7 @@ #define TCG_TARGET_HAS_orc_i32 1 #define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 @@ -120,13 +120,13 @@ #define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 -#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 #else diff --git a/tcg/tci.c b/tcg/tci.c index 068d742a80..d76b9f5798 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -39,7 +39,7 @@ __thread uintptr_t tci_tb_ptr; static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - regs[low_index] = value; + regs[low_index] = (uint32_t)value; regs[high_index] = value >> 32; } @@ -169,7 +169,6 @@ static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, *r4 = extract32(insn, 24, 4); } -#if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) { @@ -178,7 +177,6 @@ static void tci_args_rrrr(uint32_t insn, *r2 = extract32(insn, 16, 4); *r3 = extract32(insn, 20, 4); } -#endif static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) @@ -670,11 +668,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; +#endif /* TCG_TARGET_REG_BITS == 32 */ +#if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); - tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]); + tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); break; -#endif /* TCG_TARGET_REG_BITS == 32 */ +#endif +#if TCG_TARGET_HAS_muls2_i32 + case INDEX_op_muls2_i32: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; + tci_write_reg64(regs, r1, r0, tmp64); + break; +#endif #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 CASE_32_64(ext8s) tci_args_rr(insn, &r0, &r1); @@ -778,6 +786,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, regs[r0] = ctpop64(regs[r1]); break; #endif +#if TCG_TARGET_HAS_mulu2_i64 + case INDEX_op_mulu2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif +#if TCG_TARGET_HAS_muls2_i64 + case INDEX_op_muls2_i64: + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); + break; +#endif /* Shift/rotate operations (64 bit). */ @@ -1285,14 +1305,17 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r3), str_r(r4), str_c(c)); break; -#if TCG_TARGET_REG_BITS == 32 case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3)); break; +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 664d715440..eb48633fba 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -141,10 +141,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); - case INDEX_op_mulu2_i32: - return C_O2_I2(r, r, r, r); #endif + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: + return C_O2_I2(r, r, r, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: case INDEX_op_setcond2_i32: @@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { @@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } -#endif static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -728,10 +730,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, args[0], args[1], args[2], args[3], args[4]); tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5])); break; - case INDEX_op_mulu2_i32: +#endif + + CASE_32_64(mulu2) + CASE_32_64(muls2) tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; -#endif case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: From patchwork Wed Feb 17 20:20:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383916 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3145723jao; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 68/71] tcg/tci: Implement add2, sub2 Date: Wed, 17 Feb 2021 12:20:33 -0800 Message-Id: <20210217202036.1724901-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 ++++---- tcg/tci.c | 40 ++++++++++++++++++++++++++-------------- tcg/tci/tcg-target.c.inc | 15 ++++++++------- 3 files changed, 38 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 71a44bbfb0..515b3c7a56 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -121,11 +121,11 @@ #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_muls2_i64 1 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 diff --git a/tcg/tci.c b/tcg/tci.c index d76b9f5798..0240d850cf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -189,7 +189,6 @@ static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, *c5 = extract32(insn, 28, 4); } -#if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) { @@ -200,7 +199,6 @@ static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, *r4 = extract32(insn, 24, 4); *r5 = extract32(insn, 28, 4); } -#endif static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) { @@ -351,17 +349,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, for (;;) { uint32_t insn; TCGOpcode opc; - TCGReg r0, r1, r2, r3, r4; + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; target_ulong taddr; uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; -#if TCG_TARGET_REG_BITS == 32 - TCGReg r5; uint64_t T1, T2; -#endif TCGMemOpIdx oi; int32_t ofs; void *ptr; @@ -655,20 +650,22 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tb_ptr = ptr; } break; -#if TCG_TARGET_REG_BITS == 32 +#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 case INDEX_op_add2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 + T2); break; +#endif +#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 case INDEX_op_sub2_i32: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); T1 = tci_uint64(regs[r3], regs[r2]); T2 = tci_uint64(regs[r5], regs[r4]); tci_write_reg64(regs, r1, r0, T1 - T2); break; -#endif /* TCG_TARGET_REG_BITS == 32 */ +#endif #if TCG_TARGET_HAS_mulu2_i32 case INDEX_op_mulu2_i32: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); @@ -798,6 +795,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); break; #endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_add2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 = regs[r2] + regs[r4]; + T2 = regs[r3] + regs[r5] + (T1 < regs[r2]); + regs[r0] = T1; + regs[r1] = T2; + break; +#endif +#if TCG_TARGET_HAS_add2_i64 + case INDEX_op_sub2_i64: + tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); + T1 = regs[r2] - regs[r4]; + T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]); + regs[r0] = T1; + regs[r1] = T2; + break; +#endif /* Shift/rotate operations (64 bit). */ @@ -1114,10 +1129,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) const char *op_name; uint32_t insn; TCGOpcode op; - TCGReg r0, r1, r2, r3, r4; -#if TCG_TARGET_REG_BITS == 32 - TCGReg r5; -#endif + TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong i1; int32_t s2; TCGCond c; @@ -1315,15 +1327,15 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) str_r(r2), str_r(r3)); break; -#if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); info->fprintf_func(info->stream, "%-12s %s,%s,%s,%s,%s,%s", op_name, str_r(r0), str_r(r1), str_r(r2), str_r(r3), str_r(r4), str_r(r5)); break; -#endif case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eb48633fba..9b2e2c32a1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -134,11 +134,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_brcond_i64: return C_O0_I2(r, r); -#if TCG_TARGET_REG_BITS == 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ case INDEX_op_add2_i32: + case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: return C_O2_I4(r, r, r, r, r, r); + +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); #endif @@ -467,7 +469,6 @@ static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGReg r5) @@ -483,7 +484,6 @@ static void tcg_out_op_rrrrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 28, 4, r5); tcg_out32(s, insn); } -#endif static void tcg_out_ldst(TCGContext *s, TCGOpcode op, TCGReg val, TCGReg base, intptr_t offset) @@ -719,12 +719,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_op_rr(s, opc, args[0], args[1]); break; -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: + CASE_32_64(add2) + CASE_32_64(sub2) tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2], args[3], args[4], args[5]); break; + +#if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, args[0], args[1], args[2], args[3], args[4]); From patchwork Wed Feb 17 20:20:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383920 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3148499jao; Wed, 17 Feb 2021 13:29:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJxdIysKmOdx9kFXYMD0ZFIVcGEr5PoIVKdo4x+sJVTkp39BgC4YfDbqaK7gbBSoqDPiDEGl X-Received: by 2002:a25:105:: with SMTP id 5mr2003082ybb.133.1613597379638; Wed, 17 Feb 2021 13:29:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613597379; cv=none; d=google.com; s=arc-20160816; b=yztzzTNBBUhj836gTGdH6dlU2Rr306SVvmJ6/JXk9aZR9E5UcjrFJwWbygMIb7tTkN Rlfe3P7AvEh+rPIp+cPbN/I/mSGcS40OiJebhZEPflJMzfRY8bZi9xumNVYNAObl9Ayq ASc5KH/voTlrxstdVVRi6WdPxL7h8G6fFFHVqua8TXZCPshigkvDsmiB/thj3/zcYwRq hLb/DNiR9OPsb3KCmWfyYc9sAk1D2XRqqRywdlijDECPTr9IviM8o4fPiw20QUCMk40j O/Qt1kwWNMposBt3CQm5TLtJmTTwkL47d+GX3qc+5HZWbbvkjNT5RvrkM7INtne/vMMU kw3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ao4OKRpDcfbemUwRIlrAeEvX8kliF+Y+aAzUNEwCXa8=; b=MzgIQrVfI0o5nQgWxHLeIZi3CpmiqYLgk2hF4i65rRT45y6B0pjZrnMK5qGnKEEILJ C0+w4O6sXwtVhayi09/r+ggdpvYutz+oXxiY7tn+qKUJa2yuf3Oq9YJnAlF6iDq6HPWb oIWTFCvvagwXcWnKCUDCiyxU06Qe9ro5TVK9mMEm6TNBFMEA3p01q42nofF+ozlqTR9n JL0ibzJCxwZCEvJEKtvhax2ftBVGZIjy+muv0crJT43V33de05h85DHcQF4jcrY41npa LGBahex+IC2io5+lCE7qxEI3XlW3j0kNwMVdZ4FD8PURt370oIxttHy5v7uAvhWLkTCw cR9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eyMui52Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Date: Wed, 17 Feb 2021 12:20:34 -0800 Message-Id: <20210217202036.1724901-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Expand the single-use macros into the new functions. Use cpu_ldsb_mmuidx_ra and cpu_ldsw_le_mmuidx_ra so that the trace event receives the correct sign flag. Signed-off-by: Richard Henderson --- tcg/tci.c | 215 +++++++++++++++++++----------------------------------- 1 file changed, 75 insertions(+), 140 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 0240d850cf..84bef41af3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -284,34 +284,77 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) return result; } -#define qemu_ld_ub \ - cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leuw \ - cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leul \ - cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leq \ - cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beuw \ - cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beul \ - cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beq \ - cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_b(X) \ - cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lew(X) \ - cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lel(X) \ - cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_leq(X) \ - cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bew(X) \ - cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bel(X) \ - cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_beq(X) \ - cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, + TCGMemOpIdx oi, const void *tb_ptr) +{ + uintptr_t ra = (uintptr_t)tb_ptr; + int mmu_idx = get_mmuidx(oi); + MemOp mop = get_memop(oi); + + switch (mop & (MO_BSWAP | MO_SSIZE)) { + case MO_UB: + return cpu_ldub_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_SB: + return cpu_ldsb_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEUW: + return cpu_lduw_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEUW: + return cpu_lduw_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LESW: + return cpu_ldsw_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BESW: + return cpu_ldsw_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEUL: + return cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEUL: + return cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LESL: + return (int32_t)cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BESL: + return (int32_t)cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEQ: + return cpu_ldq_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEQ: + return cpu_ldq_be_mmuidx_ra(env, taddr, mmu_idx, ra); + + default: + g_assert_not_reached(); + } +} + +static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, + TCGMemOpIdx oi, const void *tb_ptr) +{ + uintptr_t ra = (uintptr_t)tb_ptr; + int mmu_idx = get_mmuidx(oi); + MemOp mop = get_memop(oi); + + switch (mop & (MO_BSWAP | MO_SIZE)) { + case MO_UB: + cpu_stb_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEUW: + cpu_stw_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEUW: + cpu_stw_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEUL: + cpu_stl_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEUL: + cpu_stl_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEQ: + cpu_stq_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEQ: + cpu_stq_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + default: + g_assert_not_reached(); + } +} #if TCG_TARGET_REG_BITS == 64 # define CASE_32_64(x) \ @@ -908,34 +951,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp32 = qemu_ld_ub; - break; - case MO_SB: - tmp32 = (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp32 = qemu_ld_leuw; - break; - case MO_LESW: - tmp32 = (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp32 = qemu_ld_leul; - break; - case MO_BEUW: - tmp32 = qemu_ld_beuw; - break; - case MO_BESW: - tmp32 = (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp32 = qemu_ld_beul; - break; - default: - g_assert_not_reached(); - } + tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr); regs[r0] = tmp32; break; @@ -951,46 +967,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = tci_uint64(regs[r3], regs[r2]); oi = regs[r4]; } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp64 = qemu_ld_ub; - break; - case MO_SB: - tmp64 = (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp64 = qemu_ld_leuw; - break; - case MO_LESW: - tmp64 = (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp64 = qemu_ld_leul; - break; - case MO_LESL: - tmp64 = (int32_t)qemu_ld_leul; - break; - case MO_LEQ: - tmp64 = qemu_ld_leq; - break; - case MO_BEUW: - tmp64 = qemu_ld_beuw; - break; - case MO_BESW: - tmp64 = (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp64 = qemu_ld_beul; - break; - case MO_BESL: - tmp64 = (int32_t)qemu_ld_beul; - break; - case MO_BEQ: - tmp64 = qemu_ld_beq; - break; - default: - g_assert_not_reached(); - } + tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); if (TCG_TARGET_REG_BITS == 32) { tci_write_reg64(regs, r1, r0, tmp64); } else { @@ -1007,25 +984,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = tci_uint64(regs[r2], regs[r1]); } tmp32 = regs[r0]; - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp32); - break; - case MO_LEUW: - qemu_st_lew(tmp32); - break; - case MO_LEUL: - qemu_st_lel(tmp32); - break; - case MO_BEUW: - qemu_st_bew(tmp32); - break; - case MO_BEUL: - qemu_st_bel(tmp32); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); break; case INDEX_op_qemu_st_i64: @@ -1044,31 +1003,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } tmp64 = tci_uint64(regs[r1], regs[r0]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp64); - break; - case MO_LEUW: - qemu_st_lew(tmp64); - break; - case MO_LEUL: - qemu_st_lel(tmp64); - break; - case MO_LEQ: - qemu_st_leq(tmp64); - break; - case MO_BEUW: - qemu_st_bew(tmp64); - break; - case MO_BEUL: - qemu_st_bel(tmp64); - break; - case MO_BEQ: - qemu_st_beq(tmp64); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); break; case INDEX_op_mb: From patchwork Wed Feb 17 20:20:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383918 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3147210jao; 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Date: Wed, 17 Feb 2021 12:20:35 -0800 Message-Id: <20210217202036.1724901-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Signed-off-by: Richard Henderson --- configure | 3 +++ tests/tcg/Makefile.target | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Thomas Huth diff --git a/configure b/configure index a79b3746d4..b8924276bc 100755 --- a/configure +++ b/configure @@ -5797,6 +5797,9 @@ fi if test "$optreset" = "yes" ; then echo "HAVE_OPTRESET=y" >> $config_host_mak fi +if test "$tcg" = "enabled" -a "$tcg_interpreter" = "true" ; then + echo "CONFIG_TCG_INTERPRETER=y" >> $config_host_mak +fi if test "$fdatasync" = "yes" ; then echo "CONFIG_FDATASYNC=y" >> $config_host_mak fi diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 24d75a5801..fa5813192a 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -77,8 +77,10 @@ LDFLAGS= QEMU_OPTS= -# If TCG debugging is enabled things are a lot slower -ifeq ($(CONFIG_DEBUG_TCG),y) +# If TCG debugging, or TCI is enabled things are a lot slower +ifneq ($(CONFIG_TCG_INTERPRETER),) +TIMEOUT=90 +else ifneq ($(CONFIG_DEBUG_TCG),) TIMEOUT=60 else TIMEOUT=15 From patchwork Wed Feb 17 20:20:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 383921 Delivered-To: patch@linaro.org Received: by 2002:a02:c80e:0:0:0:0:0 with SMTP id p14csp3150221jao; Wed, 17 Feb 2021 13:32:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJyvemsK5cAjb+ZuLS9U6gx+zvSzM9+lnqUmf5FsiVjnP7I97UW2qZyJ6iNIbvbb5QWcgj9Y X-Received: by 2002:a25:41d5:: with SMTP id o204mr2195966yba.256.1613597565539; Wed, 17 Feb 2021 13:32:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1613597565; cv=none; d=google.com; s=arc-20160816; b=u+2rSWg9KmTbf2jwFIdymteZTHtVZLf7KWQNedssUhw6jmHfQJXOkiBL8cNoCz/tE6 Lg3fwb/BG5E1hnhj69pY7Lm6B4V7sYYy90NViBOsaDvmDDhrUrbvclkR7gkG4SEkwh+A hnNpW8qbgP41xfB+/DThpNKHq4REgFkCes3ynGL2YeiYwxHcgRAzTA2bhJJbBga0UfNx tMRmFAhQMpgIt0pd69MgZhAdvfv+GWYiahklkA0sLZeeSGUjhmtFTcJG268VVOcSnkOv oqAC1eT1RjBRzqWXwaCW99wJb5isSU9/ZhZuEE539VNr8ulxlt24k4vqXpZJqHI3fvEp 5NGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sOfLAVkLgg63RmxbpsuuYlLjEnk78TrO9DvNZg7MM0M=; b=f2NBS0Vx8azvmy/cWQfTI3ezzTsGzuPkbtQf8wUVofT9EKiZG6yI9LnR7cK1nw2Xz9 G/66bad+fKI8l7ysmeOwhTUAYF3LKwPzwPCW1giCvo9zJF/r1xPQ5LN5bnUu0yN4zkSl ynHJuatvBlgWf/dy0DfD3LFr51PbZyQ2F8WSGrPZATuwA5+prj8jbRXQlnWMPqo5cGMP aYhlGaeYTh2de/Bv+NpKB0NjP52NqAPtrbvgACOyUrfa4PBYh0Z7HFLKbfCilzLuu/vd W/eNGRzGIRXKUcaNjv5g5i364dCNmQOzPYyBkJmYcLp5BEKm5w9IFo78J8VY8dMUivzD ZAoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KpEDhHjJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Date: Wed, 17 Feb 2021 12:20:36 -0800 Message-Id: <20210217202036.1724901-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We're currently only testing TCI with a 64-bit host -- also test with a 32-bit host. Enable a selection of softmmu and user-only targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- .gitlab-ci.d/crossbuilds.yml | 17 ++++++++++++++--- .../docker/dockerfiles/fedora-i386-cross.docker | 1 + 2 files changed, 15 insertions(+), 3 deletions(-) -- 2.25.1 Acked-by: Thomas Huth diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 66547b6683..99300f786b 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -6,7 +6,8 @@ - mkdir build - cd build - PKG_CONFIG_PATH=$PKG_CONFIG_PATH - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-user + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_OPTS + --disable-user --target-list-exclude="arm-softmmu cris-softmmu i386-softmmu microblaze-softmmu mips-softmmu mipsel-softmmu mips64-softmmu ppc-softmmu sh4-softmmu xtensa-softmmu" @@ -27,7 +28,7 @@ - PKG_CONFIG_PATH=$PKG_CONFIG_PATH ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-tools --enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS - - make -j$(expr $(nproc) + 1) all check-build + - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS .cross_user_build_job: stage: build @@ -36,7 +37,8 @@ - mkdir build - cd build - PKG_CONFIG_PATH=$PKG_CONFIG_PATH - ../configure --enable-werror $QEMU_CONFIGURE_OPTS --disable-system + ../configure --enable-werror $QEMU_CONFIGURE_OPTS $ACCEL_CONFIGURE_OPTS + --disable-system - make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS cross-armel-system: @@ -81,6 +83,15 @@ cross-i386-user: IMAGE: fedora-i386-cross MAKE_CHECK_ARGS: check +cross-i386-tci: + extends: .cross_accel_build_job + timeout: 60m + variables: + IMAGE: fedora-i386-cross + ACCEL: tcg-interpreter + ACCEL_CONFIGURE_OPTS: --target-list=i386-softmmu,i386-linux-user,aarch64-softmmu,aarch64-linux-user,ppc-softmmu,ppc-linux-user + MAKE_CHECK_ARGS: check + cross-mips-system: extends: .cross_system_build_job variables: diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker index a6e411291b..aa66314c65 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -5,6 +5,7 @@ ENV PACKAGES \ findutils \ gcc \ git \ + libffi-devel.i686 \ libtasn1-devel.i686 \ libzstd-devel.i686 \ make \