From patchwork Tue Mar 20 08:36:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 132137 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp575414ljb; Tue, 20 Mar 2018 01:36:55 -0700 (PDT) X-Google-Smtp-Source: AG47ELv7BXW6/a48vZV+TPxtXdg9R0d9GCr6s+jiepTCT9P7nm1hmqkVLKkVYk+q8DibyvdB6/wM X-Received: by 2002:a17:902:309:: with SMTP id 9-v6mr15982001pld.63.1521535015657; Tue, 20 Mar 2018 01:36:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521535015; cv=none; d=google.com; s=arc-20160816; b=a/MpWBcJNDJR0mOrvElumdGJPCkY7/qq000u9mKgK+UVY16nGDWRipytRIDcsJi4gj a3I/xoQzUVg7oQKa4O9W6BQgCN18PX//5cgjq0ltFM945/HcjjG8N+gMr0u/w72Ry8w2 59XUsp+CjIQ8gYQsyMLrbwh3XKyq/8XWeRJOYz9PX1Xg/hyj53LnlDU5R1VAzRlnkn2d CkV6/5lblbVHYEkwlrKSggcq1Z/E6honMoR+Gzsv//o8ZioZLNs+Lfw5Xy6ntTXXx0t3 bBo7ysVPp/+Sz3V3DgOYgEx1MqiJ1HIdvgq8JSvKteVrftTDNjJgPC27E0VZQ30AwNXv IgeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6pLv/ZEEGj3Egz5P3wvQC154jeCusay4stgycogIkLo=; b=qmzUggOQLjqvfvwupViSEMO96j0o49S7PDFtY05OuKwAmuuJsYM252QzOw9eF6bgNH dpR0pFaE6PGXujDkLbO/UqrdOnriDogxcfeKk9+lc9MjICJFbbQsGoFlLVZ92kP/kcNS an7vlH05EtSzJ3QK/9+zGfh+EpBvosN3R34POckQU/tY41CZ7I2MM6Srza5FygV1E4uH SkIpCnAThJnWhZEV/3sNJp8TRYcPmvwpv66xQzP2azPz93/OXXSHtGPrs7W+VpJXNefo njhdz/5i1rWNqrZJterVumu12y9QGTY1G/HQM/agFoeLSe5wytbu31SWsl9wrrB5BiQS DnrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BHgQ1j69; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n5si898928pgd.345.2018.03.20.01.36.55; Tue, 20 Mar 2018 01:36:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BHgQ1j69; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752293AbeCTIgw (ORCPT + 28 others); Tue, 20 Mar 2018 04:36:52 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:42325 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752254AbeCTIgr (ORCPT ); Tue, 20 Mar 2018 04:36:47 -0400 Received: by mail-pg0-f65.google.com with SMTP id f10so196612pgs.9 for ; Tue, 20 Mar 2018 01:36:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6pLv/ZEEGj3Egz5P3wvQC154jeCusay4stgycogIkLo=; b=BHgQ1j69RoA3fDFkmVXsjBnX4DO6Hgp1O3t9+E5R/MwXIGSSKPx3pu1p7dqaPHTyPA xaZ1+p2IgL2HWsbFtX1F73G49l3A0x70h9nGfvaO5dbAjEEN07VK4BSIPQtpIl6+J+Zp 2cj8/ckCWN45Bpg/ns4ooeEsZeIaeY+Uml6X0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6pLv/ZEEGj3Egz5P3wvQC154jeCusay4stgycogIkLo=; b=U308WD0cFyicf3LHtSFDSo2Y20Wh/gh50/uhWfh2EJB/BpvalYXwbk8vCH+98IQ+hs ru/CzxqXIC/BR2cBY1MirjbwB2iLbOsrDDvxVhN9685HHj9gUvWOqvCuertXB0excGty MnhEYHlGQ3h4likiT5qxpo68RadcDR83c9/bAKi1eAqDLHQr8q1vDGbtwzq674BfsTM9 KT1Cv4E8rADszdiM+9KPNyAPQDEoOWMaxgps93GhBBF8hiDBNbeszx2QyY/U8KUv8nfG 8FuF43wK2w+qmlGrUBR4tLorn2CLCd+JsBVGXsuzNv4XIuGw4w5PY3aD1Fe6qAdQOwdP 8ekw== X-Gm-Message-State: AElRT7FiwQ3X7BXRT3cVW7h+2Ez13tg4RbL7yw1FcS31vA/o7o3SXYb/ GVmG4I13p2L9qkg8vFxJjX3X8DKAPVI= X-Received: by 10.98.74.143 with SMTP id c15mr12955219pfj.83.1521535006787; Tue, 20 Mar 2018 01:36:46 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id q62sm2590048pfd.61.2018.03.20.01.36.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Mar 2018 01:36:46 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Mark Brown , Billows Wu , Chunyan Zhang Subject: [PATCH 1/3] mmc: sdhci: add sd host v4 mode Date: Tue, 20 Mar 2018 16:36:24 +0800 Message-Id: <1521534986-21907-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521534986-21907-1-git-send-email-zhang.chunyan@linaro.org> References: <1521534986-21907-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduces a flag to record this. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 6 ++++++ drivers/mmc/host/sdhci.h | 6 ++++++ 2 files changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2020e57..da4d91e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3289,6 +3289,12 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; + if (host->version >= SDHCI_SPEC_400) { + if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_V4_MODE) + host->v4_mode = true; + } + if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) return; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c95b0a4..128b0ba 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -184,6 +184,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -270,6 +271,8 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 /* * End of controller registers. @@ -551,6 +554,9 @@ struct sdhci_host { u32 sdma_boundary; unsigned long private[0] ____cacheline_aligned; + + /* Host Version 4 Enable */ + bool v4_mode; }; struct sdhci_ops { From patchwork Tue Mar 20 08:36:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 132139 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp575841ljb; Tue, 20 Mar 2018 01:37:25 -0700 (PDT) X-Google-Smtp-Source: AG47ELvi7cswzB9bL532SVTECGuvV5M0JvoL+GDo5Yw19BtEClkKZlAmmEX+rx7FDsMX+mE5P7mk X-Received: by 2002:a17:902:5a87:: with SMTP id r7-v6mr11064914pli.173.1521535045718; Tue, 20 Mar 2018 01:37:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521535045; cv=none; d=google.com; s=arc-20160816; b=cVIb80P4zNROSJMsR0KaJFb3gpBKOqnpqRv0rR47n0+7e7TZO/cjo1G51i/Mug0+lQ PequR6coPTENWGaMncca6KFjFznlWao0QLqD9XZLaI1j5ppaeiM+lf8uN/7OsapMhU7I MIyWBcNef85loxzLVmcx06rWchiYLDunzv+6u34TGvQ8bNA9Ebq7/BHoZrtNcc1V0obi mqsXzYVDikBBNMiNhLhOQmwcg37pVQddYYp6fnTv1ENEJ4AB7Gi65ToPlSYzoj8UYkcS 35SerXsbbsxYzLZRZz+KW7DTCNPx+P1Ex/EsqiFklVufZbftVNgSrAFWmcLqjTlq17gU mKFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=FqNDPU7XDHgqYln04xz6NNajOLlzDycLuV3GQjd3moY=; b=YzlJjgAu1bnGU5RZD9nQ5c77rTOMOEybGKufmWmC+aZIS2bb/AABAZzJ18onFtfgCE Us7W+hWU+xzBXmN6FaSkmHFSbFFhRQQ67TqTfEi3pejZ4i0eFg8mv35tL4l2edyx1IfI ejq5wgz73pHHXnvITWiVrC4xkXck/yXgt/9j74Beb2m9ykx1AIiBPSruyaQpI38X2gDv s1B1rTaQZvO3GoH+CO3MHrf+TOuXZsgMePD1zqcdui71w4yfmuExXAeb45DulW4gGJP+ a451J32VIs2zizTmXdhB4EHxCW39sXHbPdaoLgDulnX+DObfn8U/gRgqAAXBGugG5HGB /mmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e7WvX2jC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r8-v6si1213998pli.12.2018.03.20.01.37.25; Tue, 20 Mar 2018 01:37:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e7WvX2jC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752375AbeCTIhV (ORCPT + 28 others); Tue, 20 Mar 2018 04:37:21 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:37598 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752277AbeCTIgu (ORCPT ); Tue, 20 Mar 2018 04:36:50 -0400 Received: by mail-pg0-f68.google.com with SMTP id n11so364548pgp.4 for ; Tue, 20 Mar 2018 01:36:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FqNDPU7XDHgqYln04xz6NNajOLlzDycLuV3GQjd3moY=; b=e7WvX2jC1YEAenChWvqTktLFytAMSOX9rCmU7R8NzN8Dthidlpe7gfQvTVUaGG1ld6 6zGLrWZpe1jjrI3yhQz+JQWDFBapMo9KAFL5IuvH+g8yh+eQffYb/5IxIPVybIuGJfJX ly2TwAbkDj2+QuMro5ESWDFo43Rh4n68+LpRI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FqNDPU7XDHgqYln04xz6NNajOLlzDycLuV3GQjd3moY=; b=momWIZystXJrn9Uy8v5XQ5LiqlPywfECuOjQq7Db2aZqdLo2z6xM2ozRsHjbefNbDx 5IdKIb09NzGxijfzg+GjbqPXqu8b+FYOloh5HwZYo7k/6wi5ZriUo4bRJswUenYC01O9 j2KfB39N7z4MSYweLNQhtNairCLKExyh6n0Ij7O6x2TL+z74KK2m9aUCGvVbCjrk3GZk SEfHsASwbIIpEzQBooqbYzcqMEE9OS7dmFb18tiMsCrqYuYIHJcV24tBquC5UR5fbZc1 UbRNQ1HlkMNd25llc3IJUmxPm4maTs00DwisWxGeWc4LmjuHQCMCTB/72BXNaSoCZMz6 jrwA== X-Gm-Message-State: AElRT7F5H+xiv3Q8LqGDXGlT0ZSQuApfDwbHwRhNEtWjluAhG9roSXVc 8AJIsGRV+RFEjWBCVxaQQ2D+KA== X-Received: by 10.98.225.9 with SMTP id q9mr1336538pfh.23.1521535010126; Tue, 20 Mar 2018 01:36:50 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id q62sm2590048pfd.61.2018.03.20.01.36.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Mar 2018 01:36:49 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Mark Brown , Billows Wu , Chunyan Zhang Subject: [PATCH 2/3] mmc: sdhci: made changes for SDMA System Address register Date: Tue, 20 Mar 2018 16:36:25 +0800 Message-Id: <1521534986-21907-3-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521534986-21907-1-git-send-email-zhang.chunyan@linaro.org> References: <1521534986-21907-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index da4d91e..748a3a3 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -805,6 +805,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { u8 ctrl; + u32 reg; struct mmc_data *data = cmd->data; if (sdhci_data_line_cmd(cmd)) @@ -894,8 +895,10 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); + reg = host->v4_mode ? SDHCI_ADMA_ADDRESS : + SDHCI_DMA_ADDRESS; sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + reg); } } @@ -2721,6 +2724,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) */ if (intmask & SDHCI_INT_DMA_END) { u32 dmastart, dmanow; + u32 reg; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2733,7 +2737,9 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) host->data->bytes_xfered = dmanow - dmastart; DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + reg = host->v4_mode ? SDHCI_ADMA_ADDRESS : + SDHCI_DMA_ADDRESS; + sdhci_writel(host, dmanow, reg); } if (intmask & SDHCI_INT_DATA_END) { From patchwork Tue Mar 20 08:36:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 132138 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp575538ljb; Tue, 20 Mar 2018 01:37:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELsdA3J8gUcFBrX0N90qCqmTud7uGrCOTvSsaVDcGVLJG/0LKKtx+EHTgSnfynh1gZbrw/dc X-Received: by 2002:a17:902:8607:: with SMTP id f7-v6mr11867839plo.11.1521535023757; Tue, 20 Mar 2018 01:37:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521535023; cv=none; d=google.com; s=arc-20160816; b=ammwEI0aafX3w2gV3OjuOU+WuGUhkGplJ06PP4RRspjZ+Xv+rFxKpuIrHRkYDxRloY 0oQWuU2ChqcGCtPHOIAxIagY/i5zBA31j39cnBzspXm/zJa4ghglBfhrFy2XRtUdgc2a zsFm04saghnEbClaIxMvkt5OsJkTQwbT2ofy4NisMINK8Zciz6/LxRGV9hXKqIF5pvVY yG4ZeqsS3XtO4jnouy+W/MSRz1shPXmiLEggkSh0F917A7N1qa20R9xdAXneUl2fRQRo jih0d3sOd1NooGT5VsNgu2HZkPbTnYCixuVsfaLAiUEofuup6Vjzb8BnsIwRQVM5TCrQ 93aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Vptr69juWfZAhMZ/ISf4ChoXeM/noKTIKBtiWR/zvkQ=; b=xI1pQFxw6f4Hz5qhRM40XXIgn4hof3J+rsCasrKGpsEJIsnQ+K4+Nek/lwpMq5o21b fM3FskXpnlbyFeTKXgXQky5FHNlOq8c9AGkqdZcmKoTfsn/ciBqXMbSx3GFFYXvGzDCm iGVu6QM8Auy3qS1LQgNIKq5ZHeFPDeXIcH7eQTNc/0IWAzD+2hz8lAheBfel+Sk3oqbS +EaFoLeFamurOF2b6CzQtxVU4iksbv0m4Lqm3v028apcxCG3VteJzdAZKOGfNkT3K/PB VMs7LrPCVHjXoob0JvC0Pz/Gz/TISEpfdckVSyL5pMZmutBC4uHMBFx+4KhX/Om42jra 7W2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F9BNdT0m; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n5si898928pgd.345.2018.03.20.01.37.03; Tue, 20 Mar 2018 01:37:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F9BNdT0m; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752334AbeCTIhA (ORCPT + 28 others); Tue, 20 Mar 2018 04:37:00 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:34566 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752273AbeCTIgy (ORCPT ); Tue, 20 Mar 2018 04:36:54 -0400 Received: by mail-pl0-f65.google.com with SMTP id u11-v6so566443plq.1 for ; Tue, 20 Mar 2018 01:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vptr69juWfZAhMZ/ISf4ChoXeM/noKTIKBtiWR/zvkQ=; b=F9BNdT0mfhMXN9f0e/58zgvaRRg5LhH0gMlDcdLl0Tf7mWeTxXUzdqv5bCxP0ABRv6 kII1sSHWDpBfLSRfuHrANBJBRMOxyrPtFHXBhBLUcW5Nn8tnsXfsCtmmGyzsx9aNEMNk vYAXrZVTLR55YGbCOIhwKXCYdEhCZUyLo9c2I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vptr69juWfZAhMZ/ISf4ChoXeM/noKTIKBtiWR/zvkQ=; b=mutwFEbRHPw6DrwFT5lXAIpj6HtJl7T1JvL7lLcxrzJSe4W7MX4pY2msrSr3kWZ/u6 8bqKXguzJ9YmagKMVzLFK1Y3UKobdjUg8EUqh7AZtjnQ32RkpZ2qIk3p6DFUjIKymGK0 OJi96yC/Md9GJ3G6ubKwUOj0lDyEpLLvfbnfYaxfyagkHzMapv1+JaAy4g4KZGE92RuU lb/Ktq+o/Vr+KMwM9CSX39qUW+Qw3CcqCgXjNtAo2p+lka38trIHq0tnZ8/7r4naHidH UdG+T0KONSX1PEdeGdVc83jDg0c2CHVgUCLGqQmfjlu3rl+6+MZIIAZbV5iGIeyDrAuG 4MrA== X-Gm-Message-State: AElRT7FbwG3Llq5YspWvwKWsJjEh5JxIVzSgo8l0eTbFmq509HaleWB/ idJJtpuPNCyOnypx9MUHXP8lGQ== X-Received: by 2002:a17:902:b185:: with SMTP id s5-v6mr15449389plr.109.1521535013633; Tue, 20 Mar 2018 01:36:53 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id q62sm2590048pfd.61.2018.03.20.01.36.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Mar 2018 01:36:52 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Mark Brown , Billows Wu , Chunyan Zhang Subject: [PATCH 3/3] mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode Date: Tue, 20 Mar 2018 16:36:26 +0800 Message-Id: <1521534986-21907-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521534986-21907-1-git-send-email-zhang.chunyan@linaro.org> References: <1521534986-21907-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. There are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 50 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 23 +++++++++++++++++----- 2 files changed, 55 insertions(+), 18 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 748a3a3..137905c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -585,6 +585,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, void *desc, *align; char *buffer; int len, offset, i; + unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host); + unsigned int adma2_mask = SDHCI_ADMA2_MASK(host); /* * The spec does not specify endianness of descriptor table. @@ -608,8 +610,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, * buffer for the (up to three) bytes that screw up the * alignment. */ - offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & - SDHCI_ADMA2_MASK; + offset = (adma2_align - (addr & adma2_align)) & + adma2_mask; if (offset) { if (data->flags & MMC_DATA_WRITE) { buffer = sdhci_kmap_atomic(sg, &flags); @@ -623,8 +625,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, BUG_ON(offset > 65536); - align += SDHCI_ADMA2_ALIGN; - align_addr += SDHCI_ADMA2_ALIGN; + align += adma2_align; + align_addr += adma2_align; desc += host->desc_sz; @@ -668,13 +670,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host, void *align; char *buffer; unsigned long flags; + unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host); + unsigned int adma2_mask = SDHCI_ADMA2_MASK(host); if (data->flags & MMC_DATA_READ) { bool has_unaligned = false; /* Do a quick scan of the SG list for any unaligned mappings */ for_each_sg(data->sg, sg, host->sg_count, i) - if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { + if (sg_dma_address(sg) & adma2_mask) { has_unaligned = true; break; } @@ -686,15 +690,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host, align = host->align_buffer; for_each_sg(data->sg, sg, host->sg_count, i) { - if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { - size = SDHCI_ADMA2_ALIGN - - (sg_dma_address(sg) & SDHCI_ADMA2_MASK); + if (sg_dma_address(sg) & adma2_mask) { + size = adma2_align - + (sg_dma_address(sg) & adma2_mask); buffer = sdhci_kmap_atomic(sg, &flags); memcpy(buffer, align, size); sdhci_kunmap_atomic(buffer, &flags); - align += SDHCI_ADMA2_ALIGN; + align += adma2_align; } } } @@ -3387,6 +3391,26 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_use_64bit_dma(struct sdhci_host *host) +{ + u32 addr64bit_en; + + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode, 64-bit DMA Addressing for V4 mode + * is enabled only if 64-bit Addressing =1 in the Host Control 2 + * register. + */ + if (host->version == SDHCI_SPEC_410 && host->v4_mode) { + addr64bit_en = (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_64BIT_ADDR); + return addr64bit_en && (host->caps & SDHCI_CAN_64BIT_V4); + } + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3458,7 +3482,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_use_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3492,15 +3516,15 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; } - host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; + host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN(host); buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 128b0ba..820a863 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -206,6 +207,7 @@ #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_64BIT_V4 0x8000000 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 @@ -297,9 +299,14 @@ struct sdhci_adma2_32_desc { __le32 addr; } __packed __aligned(4); -/* ADMA2 data alignment */ -#define SDHCI_ADMA2_ALIGN 4 -#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) +/* + * ADMA2 data alignment + * According to SD Host Controller spec v4.10, if Host Version 4 Enable is set + * in the Host Control 2 register, 128-bit Descriptor will be selected which + * shall be aligned 8-byte address boundary. + */ +#define SDHCI_ADMA2_ALIGN(host) ((host)->v4_mode ? 8 : 4) +#define SDHCI_ADMA2_MASK(host) (SDHCI_ADMA2_ALIGN(host) - 1) /* * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte @@ -308,8 +315,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte