From patchwork Thu Feb 11 05:22:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 381261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9BFDC433E0 for ; Thu, 11 Feb 2021 05:24:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9DA1A64E7C for ; Thu, 11 Feb 2021 05:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229705AbhBKFX5 (ORCPT ); Thu, 11 Feb 2021 00:23:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229512AbhBKFXz (ORCPT ); Thu, 11 Feb 2021 00:23:55 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D79E7C06178A for ; Wed, 10 Feb 2021 21:22:36 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id l18so2778466pji.3 for ; Wed, 10 Feb 2021 21:22:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AogpeLuC6h2kbFRYh8jcxM2VMpLXaY9SBeWFYBbrCSA=; b=qemjCONMGzAQ0NwTu3cqoW70NuUDn+rAE++LbZMHgRYAkzC3ZjriXPCHEL1nsC+e8k XlkeRggIgE9Y1wJcFeFWB0SXButixlGaBGIRn/qgK3XKgWtEUgaJBtOfSKHKOkRpnAy9 HJJrybQubhkyq8srL5lq26fpkNB4K8I88ydcA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AogpeLuC6h2kbFRYh8jcxM2VMpLXaY9SBeWFYBbrCSA=; b=DK2Sn5s2l3ZBu9Cwvu91zb7EjVc5ZJ3bN3+ofLeMJO1pLOsZ0s7eZstZlkB4znBjX6 zG6IIZOsE0LRFcwTOi6THNe0vJlGddagd+P8VwFcUGO1wTNpxd7/8jjBi60MvMQ65Ju5 iYCz/WHw49WdYGY9Ynrl+JTfKX2D0Vdk0EAbjGONHuqw+5oikxB9wTRAljzPRLlBjX0Z uvyMf45oDLgIMmopSJwUREbpg+qgiZSOQ08Xlx4hNBevdZqgOiJV0OjksT5PUVQithSU Hjee+xtwJMRRDNiY7evRuje6z7oZniGyLrXfeFHCOwQDoJICNra6nQ54REM0RJGyXlb9 sYKA== X-Gm-Message-State: AOAM533tJRmOxOEShmnHaEYzUtOuCG4/htuOXtmX8qwWBmd31L7c52aV WtorZuLM57+A4JErGgUq2oZsRQ== X-Google-Smtp-Source: ABdhPJy2wFjME1q+iuw0xrlRvsS0mzOVToh4DLZZpe6O9KBDNwverFfIK2xGmM4pNCocfDDhCQ9WNQ== X-Received: by 2002:a17:90a:bf0c:: with SMTP id c12mr2446478pjs.36.1613020956478; Wed, 10 Feb 2021 21:22:36 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:36 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 2/7] dt-bindings: clk: mstar msc313 mpll binding description Date: Thu, 11 Feb 2021 14:22:01 +0900 Message-Id: <20210211052206.2955988-3-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a binding description for the MStar/SigmaStar MPLL clock block. Signed-off-by: Daniel Palmer --- .../bindings/clock/mstar,msc313-mpll.yaml | 46 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml new file mode 100644 index 000000000000..0df5d75d4ebc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 MPLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that + takes the external xtal input and multiplies it to create a high + frequency clock and divides that down into a number of clocks that + peripherals use. + +properties: + compatible: + const: mstar,msc313-mpll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + mpll@206000 { + compatible = "mstar,msc313-mpll"; + reg = <0x206000 0x200>; + #clock-cells = <1>; + clocks = <&xtal>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0622ff96ca2a..d004436c8860 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2145,6 +2145,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* +F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ From patchwork Thu Feb 11 05:22:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 381260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A04C2C433E6 for ; Thu, 11 Feb 2021 05:24:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75D6764DE7 for ; Thu, 11 Feb 2021 05:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229574AbhBKFYT (ORCPT ); Thu, 11 Feb 2021 00:24:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229694AbhBKFX4 (ORCPT ); Thu, 11 Feb 2021 00:23:56 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A2F7C061794 for ; Wed, 10 Feb 2021 21:22:39 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id l18so2778563pji.3 for ; Wed, 10 Feb 2021 21:22:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yf/rno8iZl7FiboO52D+Z5FCjHSUrFGjrs6kb9VfxZc=; b=QQaYk92R9MSar5LbEY4Jz089WlCH6zJeIBpW8S733JOJGnjcFWJrEGr0M/A8U9M/A1 dEDNAK4kp66DRXzpc1gzgQDmyeR7Hf0RraVqbWZloY45Qi2EbgsDtk/T4hUxN0G2teON /mWjK76kl02w6Yq5LcTtqGFIP4nc9SC7AOAz4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yf/rno8iZl7FiboO52D+Z5FCjHSUrFGjrs6kb9VfxZc=; b=R/TX5riZQ6Qi7VGABtA4WIYqFJEccuhvlkoDrrXOgIc1HT9zKDWaR2fx40m4Nn2H5p u/viZCFZAz4OhEAum/FPJlos7rqAtY+3jxn6Dzs9/tcKMIOFq+3+zBRzpd1lpduH3/g0 KDklBKVLUpr2oZsMNMA7q2NuxHAVCTVBUdjUNkO/jBisLUnWjAwTyvg3TBZDmiCEo1Gp goWu07cUogz19afgAntl3dCz+UWlC8WlU8ctKvu2Ic86nNXTI/W/7TwvhD8nqDecHeIR UyD9ez6DU0mKshMVJ6cuj9f5QTuwdZk1GcwfyCSyuiQVEbB8UKOiaFvJ3zqYA81+1+dc p8nA== X-Gm-Message-State: AOAM531rUtZ0tYOzVm8UFssmvk46hhIeSJDMM/r03wIRNtT5gSc6V7ML hX8VorSFqP7wVT0/NplBFQSy0Q== X-Google-Smtp-Source: ABdhPJyECE81mEOyMfrxozkhKJ8viUwa7YTWL+FWSQNlzFlE08xfRgbmMzRYgQT3Za4w3olp7HaKcg== X-Received: by 2002:a17:90a:b38b:: with SMTP id e11mr2441170pjr.214.1613020958643; Wed, 10 Feb 2021 21:22:38 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:38 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 3/7] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Date: Thu, 11 Feb 2021 14:22:02 +0900 Message-Id: <20210211052206.2955988-4-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally register fixed factor clocks for things like dividers don't need to manually unregister them on remove or if probe fails. Signed-off-by: Daniel Palmer --- drivers/clk/clk-fixed-factor.c | 39 ++++++++++++++++++++++++++++------ include/linux/clk-provider.h | 4 +++- 2 files changed, 36 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 910e6e74ae90..4f7bf3929d6d 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); +static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *res) +{ + clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor *)res)->hw); +} + static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, int index, - unsigned long flags, unsigned int mult, unsigned int div) + unsigned long flags, unsigned int mult, unsigned int div, + bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; @@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, struct clk_hw *hw; int ret; - fix = kmalloc(sizeof(*fix), GFP_KERNEL); + /* You can't use devm without a dev */ + if (devm && !dev) + return ERR_PTR(-EINVAL); + + if (devm) + fix = devres_alloc(devm_clk_hw_register_fixed_factor_release, + sizeof(*fix), GFP_KERNEL); + else + fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) return ERR_PTR(-ENOMEM); @@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else ret = of_clk_hw_register(np, hw); if (ret) { - kfree(fix); + if (devm) + devres_free(fix); + else + kfree(fix); hw = ERR_PTR(ret); - } + } else if (devm) + devres_add(dev, fix); return hw; } @@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1, - flags, mult, div); + flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); @@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div) +{ + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1, + flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); + #ifdef CONFIG_OF static const struct of_device_id set_rate_parent_matches[] = { { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" }, @@ -185,7 +212,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) flags |= CLK_SET_RATE_PARENT; hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0, - flags, mult, div); + flags, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index e4316890661a..58f6fe866ae9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); - +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div); /** * struct clk_fractional_divider - adjustable fractional divider clock * From patchwork Thu Feb 11 05:22:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 381259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 165F6C433DB for ; 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:42 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 5/7] ARM: mstar: Select MSTAR_MSC313_MPLL Date: Thu, 11 Feb 2021 14:22:04 +0900 Message-Id: <20210211052206.2955988-6-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All of the ARCH_MSTARV7 chips have an MPLL as the source for peripheral clocks so select MSTAR_MSC313_MPLL. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 576d1ab293c8..cd300eeedc20 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -4,6 +4,7 @@ menuconfig ARCH_MSTARV7 select ARM_GIC select ARM_HEAVY_MB select MST_IRQ + select MSTAR_MSC313_MPLL help Support for newer MStar/Sigmastar SoC families that are based on Armv7 cores like the Cortex A7 and share the same