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[209.132.180.67]) by mx.google.com with ESMTP id 126si9336028pgj.673.2018.03.19.00.27.33; Mon, 19 Mar 2018 00:27:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HYDfDi9C; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755218AbeCSH1d (ORCPT + 10 others); Mon, 19 Mar 2018 03:27:33 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:37184 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754531AbeCSH1c (ORCPT ); Mon, 19 Mar 2018 03:27:32 -0400 Received: by mail-pg0-f65.google.com with SMTP id n11so1869552pgp.4 for ; Mon, 19 Mar 2018 00:27:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id; bh=eY0WMgSleY9Dv1otn7LNmBJN0/3tA0QkJDVUOm8WKPA=; b=HYDfDi9Cjy2XMF68DkaOnsOsqblb86ZxZQU3/8s4NfID3q/FGZQmGqneA1DioOEXzr 2ET49ILX7Mx1M8ftBRsQ+IsfUdqU8TuYY0/mjb119J04HHCCq4Z16kxI0qpwFBXdudwY /EZz1WnDsEsNLj6/JA6HpQpxD6/La8koqIuHg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=eY0WMgSleY9Dv1otn7LNmBJN0/3tA0QkJDVUOm8WKPA=; b=SSGFZkqpyivq0uoMvX66s1/KVdAPz6m+Bp2PtUMPMUsLTKf3QHKfo6iplBCbQsjwWO 7PdBByAbLLiaySvboPWvQJXObDUSwIOriPS5ZG050gp6W8mIBi96mZ//wL2HfGAsMGnc Mt4PuVNlMnzO1WX1d3Lz1UYWez2yOPSg8BleYF6n+Yt2kN2AWvZRfX3Zk31fyQ6VM3Sy Wahn7AkOvnjxTIn6QMtc2dnM3BlwCQE+px0SIQpj5HVlXRZWGz7KOglHCJJWtXKVYRgU BVL+RtzMl0Ecym53eBjuZKYOc2hl3J/7glwVL+Wmbjb/ldbgMZ8orsacMkz/f1rb3hUU NisQ== X-Gm-Message-State: AElRT7HYSUZlp7BdregmPxhEj6GEI/1mq4BzOYX04P4Z/jhAXsO16fgI gqXDx+3+JyLvMNuCXrqfviuyhOv5Zng= X-Received: by 10.98.98.194 with SMTP id w185mr9453591pfb.206.1521444451565; Mon, 19 Mar 2018 00:27:31 -0700 (PDT) Received: from localhost.localdomain ([218.255.99.6]) by smtp.gmail.com with ESMTPSA id c4sm25153728pgt.24.2018.03.19.00.27.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Mar 2018 00:27:31 -0700 (PDT) From: Ard Biesheuvel To: stable@vger.kernel.org Subject: [PATCH] irqchip/gic-v3-its: Ensure nr_ites >= nr_lpis Date: Mon, 19 Mar 2018 15:27:26 +0800 Message-Id: <20180319072726.4273-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Commit 4f2c7583e33e upstream. When struct its_device instances are created, the nr_ites member will be set to a power of 2 that equals or exceeds the requested number of MSIs passed to the msi_prepare() callback. At the same time, the LPI map is allocated to be some multiple of 32 in size, where the allocated size may be less than the requested size depending on whether a contiguous range of sufficient size is available in the global LPI bitmap. This may result in the situation where the nr_ites < nr_lpis, and since nr_ites is what we program into the hardware when we map the device, the additional LPIs will be non-functional. For bog standard hardware, this does not really matter. However, in cases where ITS device IDs are shared between different PCIe devices, we may end up allocating these additional LPIs without taking into account that they don't actually work. So let's make nr_ites at least 32. This ensures that all allocated LPIs are 'live', and that its_alloc_device_irq() will fail when attempts are made to allocate MSIs beyond what was allocated in the first place. Signed-off-by: Ard Biesheuvel [maz: updated comment] Signed-off-by: Marc Zyngier [ardb: trivial tweak of unrelated context] Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-gic-v3-its.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.11.0 diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index acb9d250a905..ac15e5d5d9b2 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -684,7 +684,7 @@ static struct irq_chip its_irq_chip = { * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. */ #define IRQS_PER_CHUNK_SHIFT 5 -#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) +#define IRQS_PER_CHUNK (1UL << IRQS_PER_CHUNK_SHIFT) static unsigned long *lpi_bitmap; static u32 lpi_chunks; @@ -1320,11 +1320,10 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, dev = kzalloc(sizeof(*dev), GFP_KERNEL); /* - * At least one bit of EventID is being used, hence a minimum - * of two entries. No, the architecture doesn't let you - * express an ITT with a single entry. + * We allocate at least one chunk worth of LPIs bet device, + * and thus that many ITEs. The device may require less though. */ - nr_ites = max(2UL, roundup_pow_of_two(nvecs)); + nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs)); sz = nr_ites * its->ite_size; sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; itt = kzalloc(sz, GFP_KERNEL);