From patchwork Wed Feb 10 21:08:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 380687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 715DEC433DB for ; Wed, 10 Feb 2021 21:09:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 44EEA64ED7 for ; Wed, 10 Feb 2021 21:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232343AbhBJVJk (ORCPT ); Wed, 10 Feb 2021 16:09:40 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:42829 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231193AbhBJVJC (ORCPT ); Wed, 10 Feb 2021 16:09:02 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id C232E23E71; Wed, 10 Feb 2021 22:08:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612991298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QK2bcR/rLsouR+qBwCFySa41ZRH5nsbzNnUjxxYoa+E=; b=ZDiIFSoysac4hCGQX9o/ScNXEM0MqEVCdcqYadKtEPyDuZO0E3CR1dWWoTsRN2SWjH7UFs cB+QxknPtZTvPXE89RoRH0Ly4rJKczPWidzhfqITiFmuuzvQsPFyS4VJwSoq8DObcgfol2 HbJ5MopRLI5Zl15qEi09wu0XnBb7Uxs= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next v3 2/9] net: phy: icplus: use PHY_ID_MATCH_EXACT() for IP101A/G Date: Wed, 10 Feb 2021 22:08:02 +0100 Message-Id: <20210210210809.30125-3-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210210210809.30125-1-michael@walle.cc> References: <20210210210809.30125-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org According to the datasheet of the IP101A/G there is no revision field and MII_PHYSID2 always reads as 0x0c54. Use PHY_ID_MATCH_EXACT() then. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- Changes since v2: - none Changes since v1: - none drivers/net/phy/icplus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index 4407b1eb1a3d..ae3cf61c5ac2 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -349,7 +349,7 @@ static struct phy_driver icplus_driver[] = { .suspend = genphy_suspend, .resume = genphy_resume, }, { - PHY_ID_MATCH_MODEL(IP101A_PHY_ID), + PHY_ID_MATCH_EXACT(IP101A_PHY_ID), .name = "ICPlus IP101A/G", /* PHY_BASIC_FEATURES */ .probe = ip101a_g_probe, @@ -365,7 +365,7 @@ module_phy_driver(icplus_driver); static struct mdio_device_id __maybe_unused icplus_tbl[] = { { PHY_ID_MATCH_MODEL(IP175C_PHY_ID) }, { PHY_ID_MATCH_MODEL(IP1001_PHY_ID) }, - { PHY_ID_MATCH_MODEL(IP101A_PHY_ID) }, + { PHY_ID_MATCH_EXACT(IP101A_PHY_ID) }, { } }; From patchwork Wed Feb 10 21:08:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 380686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C116C433DB for ; Wed, 10 Feb 2021 21:10:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D71A864EDA for ; Wed, 10 Feb 2021 21:10:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233440AbhBJVJq (ORCPT ); Wed, 10 Feb 2021 16:09:46 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:42407 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232715AbhBJVJC (ORCPT ); Wed, 10 Feb 2021 16:09:02 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 7990323E73; Wed, 10 Feb 2021 22:08:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612991298; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UpL4V9o/g1ZEzgTRTKGihsAOBF2EZFW47qT5eRSu6k0=; b=OIt5bVB013h/dvuwee7JEXdalBm4FukqUeNgXtnq4MytnBEDjVlTclKHZNTB4jjHZnldRd +wKlcQpyQ9nApkhJOYA2pzGqz/77IhLxk0Sp7Rxu78VUrGlQ8IJdeaTzsCuIc2PKsuA8nH f/U65Xangx6vBBRJaaeuZR9ZoJZXQU4= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next v3 3/9] net: phy: icplus: drop address operator for functions Date: Wed, 10 Feb 2021 22:08:03 +0100 Message-Id: <20210210210809.30125-4-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210210210809.30125-1-michael@walle.cc> References: <20210210210809.30125-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Don't sometimes use the address operator and sometimes not. Drop it and make the code look uniform. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- Changes since v2: - none Changes since v1: - none drivers/net/phy/icplus.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index ae3cf61c5ac2..43b69addc0ce 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -336,16 +336,16 @@ static struct phy_driver icplus_driver[] = { PHY_ID_MATCH_MODEL(IP175C_PHY_ID), .name = "ICPlus IP175C", /* PHY_BASIC_FEATURES */ - .config_init = &ip175c_config_init, - .config_aneg = &ip175c_config_aneg, - .read_status = &ip175c_read_status, + .config_init = ip175c_config_init, + .config_aneg = ip175c_config_aneg, + .read_status = ip175c_read_status, .suspend = genphy_suspend, .resume = genphy_resume, }, { PHY_ID_MATCH_MODEL(IP1001_PHY_ID), .name = "ICPlus IP1001", /* PHY_GBIT_FEATURES */ - .config_init = &ip1001_config_init, + .config_init = ip1001_config_init, .suspend = genphy_suspend, .resume = genphy_resume, }, { @@ -355,7 +355,7 @@ static struct phy_driver icplus_driver[] = { .probe = ip101a_g_probe, .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, - .config_init = &ip101a_g_config_init, + .config_init = ip101a_g_config_init, .suspend = genphy_suspend, .resume = genphy_resume, } }; From patchwork Wed Feb 10 21:08:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 380685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3EF0C433E9 for ; Wed, 10 Feb 2021 21:10:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ABF1C64EDC for ; Wed, 10 Feb 2021 21:10:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233561AbhBJVKn (ORCPT ); Wed, 10 Feb 2021 16:10:43 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:35211 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233035AbhBJVJC (ORCPT ); Wed, 10 Feb 2021 16:09:02 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id C928023E79; Wed, 10 Feb 2021 22:08:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612991300; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7SGmR1b124kFMup1lsRUfWs7YWWxzAWy9HWqUpTt6Gk=; b=FTLRFq9B6UtGgBriACGB7lv5SYY7BkFTKU1kRgAqJnisi5igUErwylJZndUuy3z7EfPVsB RGcObMWSsP77tKsudqXCFJmI3LJ9cw2aQpuhpxiDCd83XaL/38kPkqgcVHUIVLgycTfwKk I5RR+NIPKp4pP6TcMg1w7z1IV55KT7s= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next v3 6/9] net: phy: icplus: don't set APS_EN bit on IP101G Date: Wed, 10 Feb 2021 22:08:06 +0100 Message-Id: <20210210210809.30125-7-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210210210809.30125-1-michael@walle.cc> References: <20210210210809.30125-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- Changes since v2: - none Changes since v1: - dropped the model check. Instead use two different functions. Andrew, I've dropped your Reviewed-by because of this. drivers/net/phy/icplus.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index dee4f4d988a2..bc2b58061507 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -208,10 +208,10 @@ static int ip101a_g_probe(struct phy_device *phydev) return 0; } -static int ip101a_g_config_init(struct phy_device *phydev) +static int ip101a_g_config_intr_pin(struct phy_device *phydev) { struct ip101a_g_phy_priv *priv = phydev->priv; - int err, c; + int err; /* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */ switch (priv->sel_intr32) { @@ -241,11 +241,24 @@ static int ip101a_g_config_init(struct phy_device *phydev) break; } + return 0; +} + +static int ip101a_config_init(struct phy_device *phydev) +{ + int ret; + /* Enable Auto Power Saving mode */ - c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); - c |= IP101A_G_APS_ON; + ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON); + if (ret) + return ret; - return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); + return ip101a_g_config_intr_pin(phydev); +} + +static int ip101g_config_init(struct phy_device *phydev) +{ + return ip101a_g_config_intr_pin(phydev); } static int ip101a_g_ack_interrupt(struct phy_device *phydev) @@ -379,7 +392,7 @@ static struct phy_driver icplus_driver[] = { .probe = ip101a_g_probe, .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, - .config_init = ip101a_g_config_init, + .config_init = ip101a_config_init, .soft_reset = genphy_soft_reset, .suspend = genphy_suspend, .resume = genphy_resume, @@ -389,7 +402,7 @@ static struct phy_driver icplus_driver[] = { .probe = ip101a_g_probe, .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, - .config_init = ip101a_g_config_init, + .config_init = ip101g_config_init, .soft_reset = genphy_soft_reset, .suspend = genphy_suspend, .resume = genphy_resume, From patchwork Wed Feb 10 21:08:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 380684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFB96C433E0 for ; Wed, 10 Feb 2021 21:11:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AD2A64ED7 for ; Wed, 10 Feb 2021 21:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233648AbhBJVLU (ORCPT ); Wed, 10 Feb 2021 16:11:20 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:53755 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233093AbhBJVJD (ORCPT ); Wed, 10 Feb 2021 16:09:03 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 2360423E7C; Wed, 10 Feb 2021 22:08:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612991300; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FW4BYWBqW8SNQrgsgk2uiH5A2nrDzGNuf5PphN8DTx8=; b=rQtszOHsi4BNUXhpRzj9rbugeIXBp7JATXL3lyZ5/Gb5IxdLzHPf/y89h+hLTd06nGGCgR I4Pg4mdGJFj0VUJcVIFthpm7U+BiL4Dejw7PWOxboC6xThN9EkaiEf5syOgAo+qWtLg+7I 0ZKk9O7z47t+YlIUwuHLA5yAlOZP0Rk= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next v3 7/9] net: phy: icplus: fix paged register access Date: Wed, 10 Feb 2021 22:08:07 +0100 Message-Id: <20210210210809.30125-8-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210210210809.30125-1-michael@walle.cc> References: <20210210210809.30125-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle --- Changes since v2: - none Changes since v1: - introduce a noop read/write_page() for the IP101A - also use phy_*_paged() for the interrupt status register Andrew, I've dropped your Reviewed-by because of this. drivers/net/phy/icplus.c | 65 ++++++++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 13 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index bc2b58061507..7e0ef05b1cae 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -49,6 +49,8 @@ MODULE_LICENSE("GPL"); #define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d #define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2) +#define IP101G_DEFAULT_PAGE 16 + #define IP175C_PHY_ID 0x02430d80 #define IP1001_PHY_ID 0x02430d90 #define IP101A_PHY_ID 0x02430c54 @@ -211,23 +213,25 @@ static int ip101a_g_probe(struct phy_device *phydev) static int ip101a_g_config_intr_pin(struct phy_device *phydev) { struct ip101a_g_phy_priv *priv = phydev->priv; - int err; + int oldpage, err; + + oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE); /* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */ switch (priv->sel_intr32) { case IP101GR_SEL_INTR32_RXER: - err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL, - IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0); + err = __phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL, + IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0); if (err < 0) - return err; + goto out; break; case IP101GR_SEL_INTR32_INTR: - err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL, - IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, - IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32); + err = __phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL, + IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, + IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32); if (err < 0) - return err; + goto out; break; default: @@ -241,7 +245,8 @@ static int ip101a_g_config_intr_pin(struct phy_device *phydev) break; } - return 0; +out: + return phy_restore_page(phydev, oldpage, err); } static int ip101a_config_init(struct phy_device *phydev) @@ -263,8 +268,10 @@ static int ip101g_config_init(struct phy_device *phydev) static int ip101a_g_ack_interrupt(struct phy_device *phydev) { - int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); + int err; + err = phy_read_paged(phydev, IP101G_DEFAULT_PAGE, + IP101A_G_IRQ_CONF_STATUS); if (err < 0) return err; @@ -283,10 +290,12 @@ static int ip101a_g_config_intr(struct phy_device *phydev) /* INTR pin used: Speed/link/duplex will cause an interrupt */ val = IP101A_G_IRQ_PIN_USED; - err = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val); + err = phy_write_paged(phydev, IP101G_DEFAULT_PAGE, + IP101A_G_IRQ_CONF_STATUS, val); } else { val = IP101A_G_IRQ_ALL_MASK; - err = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val); + err = phy_write_paged(phydev, IP101G_DEFAULT_PAGE, + IP101A_G_IRQ_CONF_STATUS, val); if (err) return err; @@ -300,7 +309,8 @@ static irqreturn_t ip101a_g_handle_interrupt(struct phy_device *phydev) { int irq_status; - irq_status = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); + irq_status = phy_read_paged(phydev, IP101G_DEFAULT_PAGE, + IP101A_G_IRQ_CONF_STATUS); if (irq_status < 0) { phy_error(phydev); return IRQ_NONE; @@ -316,6 +326,31 @@ static irqreturn_t ip101a_g_handle_interrupt(struct phy_device *phydev) return IRQ_HANDLED; } +/* The IP101A doesn't really have a page register. We just pretend to have one + * so we can use the paged versions of the callbacks of the IP101G. + */ +static int ip101a_read_page(struct phy_device *phydev) +{ + return IP101G_DEFAULT_PAGE; +} + +static int ip101a_write_page(struct phy_device *phydev, int page) +{ + WARN_ONCE(page != IP101G_DEFAULT_PAGE, "wrong page selected\n"); + + return 0; +} + +static int ip101g_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, IP101G_PAGE_CONTROL); +} + +static int ip101g_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, IP101G_PAGE_CONTROL, page); +} + static int ip101a_g_has_page_register(struct phy_device *phydev) { int oldval, val, ret; @@ -390,6 +425,8 @@ static struct phy_driver icplus_driver[] = { .name = "ICPlus IP101A", .match_phy_device = ip101a_match_phy_device, .probe = ip101a_g_probe, + .read_page = ip101a_read_page, + .write_page = ip101a_write_page, .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, .config_init = ip101a_config_init, @@ -400,6 +437,8 @@ static struct phy_driver icplus_driver[] = { .name = "ICPlus IP101G", .match_phy_device = ip101g_match_phy_device, .probe = ip101a_g_probe, + .read_page = ip101g_read_page, + .write_page = ip101g_write_page, .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, .config_init = ip101g_config_init, From patchwork Wed Feb 10 21:08:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 380683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35E05C433E0 for ; Wed, 10 Feb 2021 21:13:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC87164E31 for ; Wed, 10 Feb 2021 21:13:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233395AbhBJVML (ORCPT ); Wed, 10 Feb 2021 16:12:11 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:43009 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233250AbhBJVJE (ORCPT ); Wed, 10 Feb 2021 16:09:04 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 482C523E83; Wed, 10 Feb 2021 22:08:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612991301; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IPzdzpCv5iJ0JCU3J6OhuVBzTLOea+RnWf/Wijzc2iU=; b=tN+tKRV09K9EzhZ/aoDmkOl726UsmTyvFepUCKiBSd6pTwD3YhUvHlyO6ccqhR4focMVZX 8CfI0AYhrLYxPZ/oQ/L2rnIsOzqRPGaOzkzw3kHV5pvdFtfGQzXI7zqGzQoEaJ28cXLPMA 2bFL1W7LSs5qFJrnOkymuOWOoOWVTy0= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next v3 9/9] net: phy: icplus: add MDI/MDIX support for IP101A/G Date: Wed, 10 Feb 2021 22:08:09 +0100 Message-Id: <20210210210809.30125-10-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210210210809.30125-1-michael@walle.cc> References: <20210210210809.30125-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- Changes since v2: - none Changes since v1: - none, except that the callbacks are register for both IP101A and IP101G PHY drivers drivers/net/phy/icplus.c | 93 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index 96e9d1d12992..cc5b25714002 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -37,12 +37,17 @@ MODULE_LICENSE("GPL"); #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ #define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */ +#define IP101A_G_AUTO_MDIX_DIS BIT(11) #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */ #define IP101A_G_IRQ_ALL_MASK BIT(11) /* IRQ's inactive */ #define IP101A_G_IRQ_SPEED_CHANGE BIT(2) #define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1) #define IP101A_G_IRQ_LINK_CHANGE BIT(0) +#define IP101A_G_PHY_STATUS 18 +#define IP101A_G_MDIX BIT(9) +#define IP101A_G_PHY_SPEC_CTRL 30 +#define IP101A_G_FORCE_MDIX BIT(3) #define IP101G_PAGE_CONTROL 0x14 #define IP101G_PAGE_CONTROL_MASK GENMASK(4, 0) @@ -297,6 +302,90 @@ static int ip101g_config_init(struct phy_device *phydev) return ip101a_g_config_intr_pin(phydev); } +static int ip101a_g_read_status(struct phy_device *phydev) +{ + int oldpage, ret, stat1, stat2; + + ret = genphy_read_status(phydev); + if (ret) + return ret; + + oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE); + + ret = __phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); + if (ret < 0) + goto out; + stat1 = ret; + + ret = __phy_read(phydev, IP101A_G_PHY_SPEC_CTRL); + if (ret < 0) + goto out; + stat2 = ret; + + if (stat1 & IP101A_G_AUTO_MDIX_DIS) { + if (stat2 & IP101A_G_FORCE_MDIX) + phydev->mdix_ctrl = ETH_TP_MDI_X; + else + phydev->mdix_ctrl = ETH_TP_MDI; + } else { + phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + } + + if (stat2 & IP101A_G_MDIX) + phydev->mdix = ETH_TP_MDI_X; + else + phydev->mdix = ETH_TP_MDI; + + ret = 0; + +out: + return phy_restore_page(phydev, oldpage, ret); +} + +static int ip101a_g_config_mdix(struct phy_device *phydev) +{ + u16 ctrl = 0, ctrl2 = 0; + int oldpage, ret; + + switch (phydev->mdix_ctrl) { + case ETH_TP_MDI: + ctrl = IP101A_G_AUTO_MDIX_DIS; + break; + case ETH_TP_MDI_X: + ctrl = IP101A_G_AUTO_MDIX_DIS; + ctrl2 = IP101A_G_FORCE_MDIX; + break; + case ETH_TP_MDI_AUTO: + break; + default: + return 0; + } + + oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE); + + ret = __phy_modify(phydev, IP10XX_SPEC_CTRL_STATUS, + IP101A_G_AUTO_MDIX_DIS, ctrl); + if (ret) + goto out; + + ret = __phy_modify(phydev, IP101A_G_PHY_SPEC_CTRL, + IP101A_G_FORCE_MDIX, ctrl2); + +out: + return phy_restore_page(phydev, oldpage, ret); +} + +static int ip101a_g_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret = ip101a_g_config_mdix(phydev); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + static int ip101a_g_ack_interrupt(struct phy_device *phydev) { int err; @@ -502,6 +591,8 @@ static struct phy_driver icplus_driver[] = { .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, .config_init = ip101a_config_init, + .config_aneg = ip101a_g_config_aneg, + .read_status = ip101a_g_read_status, .soft_reset = genphy_soft_reset, .suspend = genphy_suspend, .resume = genphy_resume, @@ -514,6 +605,8 @@ static struct phy_driver icplus_driver[] = { .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, .config_init = ip101g_config_init, + .config_aneg = ip101a_g_config_aneg, + .read_status = ip101a_g_read_status, .soft_reset = genphy_soft_reset, .get_sset_count = ip101g_get_sset_count, .get_strings = ip101g_get_strings,