From patchwork Sat Mar 17 10:09:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 131959 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp489619ljb; Sat, 17 Mar 2018 03:11:24 -0700 (PDT) X-Google-Smtp-Source: AG47ELuvhG1Y7y8ycBRC+XG4ERWDxbk2e3YP3MbZk+z9FrZ8z4lQ2MJzVG0IeImmF5CtiUM0WVIz X-Received: by 2002:a17:902:a981:: with SMTP id bh1-v6mr5284571plb.255.1521281484092; Sat, 17 Mar 2018 03:11:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521281484; cv=none; d=google.com; s=arc-20160816; b=tIi99J1FNk/VEAfV5J7WdLp5p0ZbEs9S/nWbKO/Pb6aOzPVZFeCpFtL54OAa0quiDq ZpKEeWdxy2ER4JThWQwFa4YfsXf9yOeCtk9FCeHd2AGJZfn1wgUkf/B4o2JMH1JP2HjA zEsAQFP+P+HtMCe8II5QG2gb6Q7cTKKWsGThwRsJ7WY6I/YOmowLnpahoh42t2YcdCZC 5DHbMBmUcYYJN4v6szeBUkRuRKPZLLLjTtXiwEloBYYbFrYVYmVW6qIUeXqi2UqRku8/ n6/kUWqDxqLbLRWnp44adWiTShS9mVWwVv12u84ceIzorbi/5AEs5xGapC3XgSdhjRXD k0OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=GrFMhbR7yKiv60oRzhy3QPFqVk1Xitp7DmvnvpUrF60=; b=CEVerAYgL4vgbwKTtCH6dJvKZ2Yk0Y6WCnXBgAsI7yCecr/+VG7vd7wC5o40H5rDsQ H5jYjJeRaGvedwm1eRg73u3H7nFuOEtdxr9cLiot7SBIo7uYz6vZ6JnfdmJRe23SH8ct +j6kVdCrZrq+XNKZPMbWXJbcipPH1TGq3jcBa0zXJv+UJPtp1Xh5bOviorG+qwS5ykIn USJgKtY1/96gqTTK+dm77aubovjKiie54e/AhKx9EjwQhQ7lxMvvvyrPVfbuHaedEu4o Gjb6hHPaSRBViDPn9If/ESESghVsjVoX7QHgGEe8Qhl/teYonJgS2ZiejdZMw/C/vZI9 tLmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ac3/74pB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b5-v6si725002plk.567.2018.03.17.03.11.23; Sat, 17 Mar 2018 03:11:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ac3/74pB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752290AbeCQKLQ (ORCPT + 28 others); Sat, 17 Mar 2018 06:11:16 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:32988 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752172AbeCQKLN (ORCPT ); Sat, 17 Mar 2018 06:11:13 -0400 Received: by mail-pf0-f193.google.com with SMTP id q13so5159511pff.0 for ; Sat, 17 Mar 2018 03:11:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GrFMhbR7yKiv60oRzhy3QPFqVk1Xitp7DmvnvpUrF60=; b=ac3/74pBfdFG2H1keFpjsxQjkeT/SdALmAYFVGDXhcAUgIHNEQsI7Ibhox93fRph5j gXZddn/ctisYYEZI8nbZcemLXp1nTbN5rG2kPCpX/j+bCyeApfcF3oyoUp+KHibzvK7w 578JMcXnH6PVBf5gtAk62UQcQTZDCLFvhVHRw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GrFMhbR7yKiv60oRzhy3QPFqVk1Xitp7DmvnvpUrF60=; b=YWaeu/Xm/czJ4U9q1Fz++rGRnXSkR2XfmnRk4x3BiZ5sSEk/+a8GyUXj2BkzDD6XwV M5qCBcjdsGH/yhsZP7CPNXvHT7qIgUdPV0FasPPoD59TdJQuGH5w++Cqpm2pB8fsjMZJ IzchRG2J2R2iDidGW9pXLfhO/ZvuitBRlK89ZCp93l2gMoPq/JzFw7wbzAPa3nS7Woe5 m4X5QTsYS/UTYWbQt6bKFrfP57BFiUBEMnXrI8Q99ti/kPDIgNeUCV/nF3bFQVdKa20g pvYZIG+neLMPN9Lw+Af/pb0RhF6grFH8rC8482oZYcFrtF80TY+50NtnygYC/UOE9T/P ho4w== X-Gm-Message-State: AElRT7F8cUJDTlkYcjpp6z+VnvjvEJmL42V4guv2ouaYpQ4GTyOPYssF O8P3USmHVt1QqAwdl4NO9//u X-Received: by 10.101.70.203 with SMTP id n11mr4083088pgr.166.1521281472331; Sat, 17 Mar 2018 03:11:12 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.11.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:11:11 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 01/12] dt-bindings: clock: Add Actions S900 clock bindings Date: Sat, 17 Mar 2018 15:39:41 +0530 Message-Id: <20180317100952.28538-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Actions Semi S900 clock bindings. Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring --- .../devicetree/bindings/clock/actions,s900-cmu.txt | 47 ++++++++ include/dt-bindings/clock/actions,s900-cmu.h | 129 +++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/actions,s900-cmu.txt create mode 100644 include/dt-bindings/clock/actions,s900-cmu.h -- 2.14.1 diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt new file mode 100644 index 000000000000..93e4fb827cd6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt @@ -0,0 +1,47 @@ +* Actions S900 Clock Management Unit (CMU) + +The Actions S900 clock management unit generates and supplies clock to various +controllers within the SoC. The clock binding described here is applicable to +S900 SoC. + +Required Properties: + +- compatible: should be "actions,s900-cmu" +- reg: physical base address of the controller and length of memory mapped + region. +- clocks: Reference to the parent clocks ("hosc", "losc") +- #clock-cells: should be 1. + +Each clock is assigned an identifier, and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/actions,s900-cmu.h header and can be used in device +tree sources. + +External clocks: + +The hosc clock used as input for the plls is generated outside the SoC. It is +expected that it is defined using standard clock bindings as "hosc". + +Actions S900 CMU also requires one more clock: + - "losc" - internal low frequency oscillator + +Example: Clock Management Unit node: + + cmu: clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0x0 0xe0160000 0x0 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + +Example: UART controller node that consumes clock generated by the clock +management unit: + + uart: serial@e012a000 { + compatible = "actions,s900-uart", "actions,owl-uart"; + reg = <0x0 0xe012a000 0x0 0x2000>; + interrupts = ; + clocks = <&cmu CLK_UART5>; + }; diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h new file mode 100644 index 000000000000..7c1251565f43 --- /dev/null +++ b/include/dt-bindings/clock/actions,s900-cmu.h @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree binding constants for Actions Semi S900 Clock Management Unit +// +// Copyright (c) 2014 Actions Semi Inc. +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H +#define __DT_BINDINGS_CLOCK_S900_CMU_H + +#define CLK_NONE 0 + +/* fixed rate clocks */ +#define CLK_LOSC 1 +#define CLK_HOSC 2 + +/* pll clocks */ +#define CLK_CORE_PLL 3 +#define CLK_DEV_PLL 4 +#define CLK_DDR_PLL 5 +#define CLK_NAND_PLL 6 +#define CLK_DISPLAY_PLL 7 +#define CLK_DSI_PLL 8 +#define CLK_ASSIST_PLL 9 +#define CLK_AUDIO_PLL 10 + +/* system clock */ +#define CLK_CPU 15 +#define CLK_DEV 16 +#define CLK_NOC 17 +#define CLK_NOC_MUX 18 +#define CLK_NOC_DIV 19 +#define CLK_AHB 20 +#define CLK_APB 21 +#define CLK_DMAC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 + +#define CLK_BISP 24 +#define CLK_CSI0 25 +#define CLK_CSI1 26 + +#define CLK_DE0 27 +#define CLK_DE1 28 +#define CLK_DE2 29 +#define CLK_DE3 30 +#define CLK_DSI 32 + +#define CLK_GPU 33 +#define CLK_GPU_CORE 34 +#define CLK_GPU_MEM 35 +#define CLK_GPU_SYS 36 + +#define CLK_HDE 37 +#define CLK_I2C0 38 +#define CLK_I2C1 39 +#define CLK_I2C2 40 +#define CLK_I2C3 41 +#define CLK_I2C4 42 +#define CLK_I2C5 43 +#define CLK_I2SRX 44 +#define CLK_I2STX 45 +#define CLK_IMX 46 +#define CLK_LCD 47 +#define CLK_NAND0 48 +#define CLK_NAND1 49 +#define CLK_PWM0 50 +#define CLK_PWM1 51 +#define CLK_PWM2 52 +#define CLK_PWM3 53 +#define CLK_PWM4 54 +#define CLK_PWM5 55 +#define CLK_SD0 56 +#define CLK_SD1 57 +#define CLK_SD2 58 +#define CLK_SD3 59 +#define CLK_SENSOR 60 +#define CLK_SPEED_SENSOR 61 +#define CLK_SPI0 62 +#define CLK_SPI1 63 +#define CLK_SPI2 64 +#define CLK_SPI3 65 +#define CLK_THERMAL_SENSOR 66 +#define CLK_UART0 67 +#define CLK_UART1 68 +#define CLK_UART2 69 +#define CLK_UART3 70 +#define CLK_UART4 71 +#define CLK_UART5 72 +#define CLK_UART6 73 +#define CLK_VCE 74 +#define CLK_VDE 75 + +#define CLK_USB3_480MPLL0 76 +#define CLK_USB3_480MPHY0 77 +#define CLK_USB3_5GPHY 78 +#define CLK_USB3_CCE 79 +#define CLK_USB3_MAC 80 + +#define CLK_TIMER 83 + +#define CLK_HDMI_AUDIO 84 + +#define CLK_24M 85 + +#define CLK_EDP 86 + +#define CLK_24M_EDP 87 +#define CLK_EDP_PLL 88 +#define CLK_EDP_LINK 89 + +#define CLK_USB2H0_PLLEN 90 +#define CLK_USB2H0_PHY 91 +#define CLK_USB2H0_CCE 92 +#define CLK_USB2H1_PLLEN 93 +#define CLK_USB2H1_PHY 94 +#define CLK_USB2H1_CCE 95 + +#define CLK_DDR0 96 +#define CLK_DDR1 97 +#define CLK_DMM 98 + +#define CLK_ETH_MAC 99 +#define CLK_RMII_REF 100 + +#define CLK_NR_CLKS (CLK_RMII_REF + 1) + +#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ From patchwork Sat Mar 17 10:09:44 2018 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id 61-v6si7784735plr.136.2018.03.17.03.11.43; Sat, 17 Mar 2018 03:11:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TXLW35lb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752565AbeCQKLh (ORCPT + 28 others); Sat, 17 Mar 2018 06:11:37 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:43375 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752464AbeCQKLd (ORCPT ); Sat, 17 Mar 2018 06:11:33 -0400 Received: by mail-pg0-f65.google.com with SMTP id e9so5057729pgs.10 for ; Sat, 17 Mar 2018 03:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SQGyxKuKh7kk1DTIAS5AB/WGlPSeIM69CRcjILG6EAg=; b=TXLW35lbiuKTFCyeTtM+izjBBQJv42lEW6uYjCZMZhrBvkWQhtF9SO4f4972OUKnh8 p+uduRKVmc4cRe7+A3LyUVgeIxc9nRBJ/LgV2UHpfdwryw1Vzok6LoTfYVmoxk/YnBnm vAO7fSN6XnZU+BP3WT3cqFuPTRzA4U9tcDYiE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SQGyxKuKh7kk1DTIAS5AB/WGlPSeIM69CRcjILG6EAg=; b=N+9CWxzX8a5egDgzwJuYKi+AWQI/WXrg9AxkFqe6yQiDdKOFUXfRyjUaSpAv6TFAaX fQxumJVaOc+XnpcuwIeqczT42JUefNVp6r42PtMMB1Q4SXF0PUjC7UFB4MQHltg3oky1 d+Zx1nJq7nMDfsjGqnhx8Sou45X3jwJ7ljyYFT4fkxUoz2WmP0C9ms3mL3M4l0apQf9s yFwvsxWi9jGcPgQkZi92TpxGVVh+CfYVHKfs01Ato/PikbTgr896N7urfVNCmMc8f/Xh JSPs6nOUeyCCcArdKipKW8XNp/TP2SN7tpYbyl7FXZGgemGAIQeR/BQZAkA0kUxny0r7 mkuw== X-Gm-Message-State: AElRT7HOIpimV/RtC8S96xq590lxZDeWmkBw7QQe8ULNAYEPCnVwEBEg ON7xFqGSTvgcJme/0OWSpzap X-Received: by 10.99.176.12 with SMTP id h12mr3095858pgf.448.1521281492316; Sat, 17 Mar 2018 03:11:32 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.11.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:11:31 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 04/12] clk: actions: Add common clock driver support Date: Sat, 17 Mar 2018 15:39:44 +0530 Message-Id: <20180317100952.28538-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi common clock driver with generic structures and interface functions. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/actions/Kconfig | 4 ++ drivers/clk/actions/Makefile | 3 ++ drivers/clk/actions/owl-common.c | 84 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-common.h | 41 ++++++++++++++++++++ 6 files changed, 134 insertions(+) create mode 100644 drivers/clk/actions/Kconfig create mode 100644 drivers/clk/actions/Makefile create mode 100644 drivers/clk/actions/owl-common.c create mode 100644 drivers/clk/actions/owl-common.h -- 2.14.1 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 98ce9fc6e6c0..6313a4f4327a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -238,6 +238,7 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +source "drivers/clk/actions/Kconfig" source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..b7909df532ed 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name +obj-y += actions/ obj-$(CONFIG_COMMON_CLK_AT91) += at91/ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig new file mode 100644 index 000000000000..13a3e5083d43 --- /dev/null +++ b/drivers/clk/actions/Kconfig @@ -0,0 +1,4 @@ +config CLK_ACTIONS + bool "Clock driver for Actions Semi SoCs" + depends on ARCH_ACTIONS || COMPILE_TEST + default ARCH_ACTIONS diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile new file mode 100644 index 000000000000..64a50fc2d335 --- /dev/null +++ b/drivers/clk/actions/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o + +clk-owl-y += owl-common.o diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c new file mode 100644 index 000000000000..a7cb698fdc86 --- /dev/null +++ b/drivers/clk/actions/owl-common.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL common clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include + +#include "owl-common.h" + +static const struct regmap_config owl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xffff, + .fast_io = true, +}; + +static void owl_clk_set_regmap(const struct owl_clk_desc *desc, + struct regmap *regmap) +{ + int i; + struct owl_clk_common *clks; + + for (i = 0; i < desc->num_clks; i++) { + clks = desc->clks[i]; + if (!clks) + continue; + + clks->regmap = regmap; + } +} + +int owl_clk_regmap_init(struct platform_device *pdev, + const struct owl_clk_desc *desc) +{ + void __iomem *base; + struct device_node *node = pdev->dev.of_node; + struct regmap *regmap; + + base = of_iomap(node, 0); + regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config); + if (IS_ERR_OR_NULL(regmap)) { + pr_err("failed to init regmap\n"); + return PTR_ERR(regmap); + } + + owl_clk_set_regmap(desc, regmap); + + return 0; +} + +int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks) +{ + int i, ret; + struct clk_hw *hw; + + for (i = 0; i < hw_clks->num; i++) { + + hw = hw_clks->hws[i]; + + if (!hw) + continue; + + ret = devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "Couldn't register clock %d - %s\n", + i, hw->init->name); + return ret; + } + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks); + if (ret) + dev_err(dev, "Failed to add clock provider\n"); + + return ret; +} diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h new file mode 100644 index 000000000000..4fd726ec54a6 --- /dev/null +++ b/drivers/clk/actions/owl-common.h @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL common clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_COMMON_H_ +#define _OWL_COMMON_H_ + +#include +#include +#include + +struct device_node; + +struct owl_clk_common { + struct regmap *regmap; + struct clk_hw hw; +}; + +struct owl_clk_desc { + struct owl_clk_common **clks; + unsigned long num_clks; + struct clk_hw_onecell_data *hw_clks; +}; + +static inline struct owl_clk_common * + hw_to_owl_clk_common(const struct clk_hw *hw) +{ + return container_of(hw, struct owl_clk_common, hw); +} + +int owl_clk_regmap_init(struct platform_device *pdev, + const struct owl_clk_desc *desc); +int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks); + +#endif /* _OWL_COMMON_H_ */ From patchwork Sat Mar 17 10:09:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 131963 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp490015ljb; Sat, 17 Mar 2018 03:11:49 -0700 (PDT) X-Google-Smtp-Source: AG47ELsfWf3wEOJ54mep6KfzAqj1xW+1MfWzcoXHggzpkgd5dChbokQ2sbuEtxVY4+fmWijd7C3W X-Received: by 10.99.171.72 with SMTP id k8mr4108618pgp.355.1521281509302; Sat, 17 Mar 2018 03:11:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521281509; cv=none; d=google.com; s=arc-20160816; b=ffsPzgCpmVPGjXaHIgLiAoIb7/SsaMIlawxfjWKoxLdFE/WoshPv/c9gtL9Q+yLHlk yQHFxeWZXpk20krrPanIjMXKp7C/aGSsV1s9brqtpQgGNrURrI8ubWQwynPPkcNpDJg7 9IPVgToxARJ1D+/BIPeQCFKQs7ulmT2R8vbXQ+RW2Ge05YAI9i0M3/OAN5sAmyLibVin CX1JI+z+D+AMja15tBkiEmqo0nY6fdxSpBhOljI1yCbq+lctvLFX+wO3GqoMCNjXCCmT h8sJFNXyLqdX+r5RaJtFLf7HbfzritmyDoAfZNdaW7E6siG7azx3bcEu8BJBRv5LQsoB iU4g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id n3-v6si7848038pld.347.2018.03.17.03.11.49; Sat, 17 Mar 2018 03:11:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LeGEIzgM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752656AbeCQKLp (ORCPT + 28 others); Sat, 17 Mar 2018 06:11:45 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:38645 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752521AbeCQKLj (ORCPT ); Sat, 17 Mar 2018 06:11:39 -0400 Received: by mail-pl0-f65.google.com with SMTP id m22-v6so7306087pls.5 for ; Sat, 17 Mar 2018 03:11:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Tok+ItM6RVX4iLhCpEbSqqi5TKJXcFO9HlirsgGga4A=; b=LeGEIzgMYLLwHz75P2DEnenb8//ncFuE5wzVHEykUbEu3aHACb5+s3oZxuBfXNNvx5 /LnlXGAlf0rwod6g0fIcEenwHaN01grT8Mpy/0hknQu1dMheaVXReLaudtiRjYnZq90o Yi5vJAyRj7G5rMYQ6sU3LRxCCewLa4xbQn8f0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Tok+ItM6RVX4iLhCpEbSqqi5TKJXcFO9HlirsgGga4A=; b=K3oTZ49xEFVx6TfDWvrgrKMEwMl44KYhQ7D9347KNz4hK4Kcg/xxBlAKGcjaPk9nbt HVeyGTU+/yt6/lNtbfebpsWpMwapBkqLNO/TCQu9ObBiBlLRWWpuVFGnSLykFljCoyX5 X0zcdAZTdEcqwP0V9UCmt0z46b3VR8FzgSJ+2JIitnRv1SKLWZai19ogKZ6fC3xpVHMx HV7SQ/L8B5s0oeSQ61YYq52N1Rb37sVhH+ivD7K08ZejKV1OknsOLoQygMvSHJc/WP9e CL7XuJmgmT+Pzj6EaFZcSWmcKvsBenIerku3Co/5UHCYG8+2JdOg05sjW/Fsrhwlshgb D4gQ== X-Gm-Message-State: AElRT7EpuSfgQOkb9Q6o/kXOG3/WbxEKPWnhz3xGd/1RnLeZbvs8hjaN fjHmPe2mt74OicLv1vSF1dQy X-Received: by 2002:a17:902:7716:: with SMTP id n22-v6mr5075025pll.268.1521281499332; Sat, 17 Mar 2018 03:11:39 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.11.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:11:38 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 05/12] clk: actions: Add gate clock support Date: Sat, 17 Mar 2018 15:39:45 +0530 Message-Id: <20180317100952.28538-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi gate clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-gate.c | 77 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-gate.h | 73 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/clk/actions/owl-gate.c create mode 100644 drivers/clk/actions/owl-gate.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 64a50fc2d335..1f0917872c9d 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o +clk-owl-y += owl-gate.o diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c new file mode 100644 index 000000000000..25dd94ac0f35 --- /dev/null +++ b/drivers/clk/actions/owl-gate.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL gate clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-gate.h" + +void clk_gate_set(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw, bool enable) +{ + int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + u32 reg; + + set ^= enable; + + regmap_read(common->regmap, gate_hw->reg, ®); + + if (set) + reg |= BIT(gate_hw->bit_idx); + else + reg &= ~BIT(gate_hw->bit_idx); + + regmap_write(common->regmap, gate_hw->reg, reg); +} + +static void owl_gate_disable(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + clk_gate_set(common, &gate->gate_hw, false); +} + +static int owl_gate_enable(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + clk_gate_set(common, &gate->gate_hw, true); + + return 0; +} + +int clk_is_enabled(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw) +{ + u32 reg; + + regmap_read(common->regmap, gate_hw->reg, ®); + + if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE) + reg ^= BIT(gate_hw->bit_idx); + + return !!(reg & BIT(gate_hw->bit_idx)); +} + +static int owl_gate_is_enabled(struct clk_hw *hw) +{ + struct owl_gate *gate = hw_to_owl_gate(hw); + struct owl_clk_common *common = &gate->common; + + return clk_is_enabled(common, &gate->gate_hw); +} + +const struct clk_ops owl_gate_ops = { + .disable = owl_gate_disable, + .enable = owl_gate_enable, + .is_enabled = owl_gate_is_enabled, +}; diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h new file mode 100644 index 000000000000..4fc609647ae4 --- /dev/null +++ b/drivers/clk/actions/owl-gate.h @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL gate clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_GATE_H_ +#define _OWL_GATE_H_ + +#include "owl-common.h" + +struct owl_gate_hw { + u32 reg; + u8 bit_idx; + u8 gate_flags; +}; + +struct owl_gate { + struct owl_gate_hw gate_hw; + struct owl_clk_common common; +}; + +#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ + { \ + .reg = _reg, \ + .bit_idx = _bit_idx, \ + .gate_flags = _gate_flags, \ + } + +#define OWL_GATE(_struct, _name, _parent, _reg, \ + _bit_idx, _gate_flags, _flags) \ + struct owl_gate _struct = { \ + .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_gate_ops, \ + _flags), \ + } \ + } \ + +#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ + _bit_idx, _gate_flags, _flags) \ + struct owl_gate _struct = { \ + .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ + &owl_gate_ops, \ + _flags), \ + }, \ + } \ + +static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_gate, common); +} + +void clk_gate_set(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw, bool enable); +int clk_is_enabled(const struct owl_clk_common *common, + const struct owl_gate_hw *gate_hw); + +extern const struct clk_ops owl_gate_ops; + +#endif /* _OWL_GATE_H_ */ From patchwork Sat Mar 17 10:09:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 131964 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp490116ljb; Sat, 17 Mar 2018 03:11:55 -0700 (PDT) X-Google-Smtp-Source: AG47ELtZr8TEqqULD5Gl1g2/otJ2MQ93GT/FuX78Mxah7szApT9gb6EDx0r7CX8x53MF1XClbFuG X-Received: by 10.99.119.74 with SMTP id s71mr4016249pgc.321.1521281515824; Sat, 17 Mar 2018 03:11:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521281515; cv=none; d=google.com; s=arc-20160816; b=CHf3VG34rYQSOBB758Py8PnCr0P97wwK68gqtQzaIUBxVGeczpavd3TqiU5D6+40SM O54Sip5Z+yscoKeQWd/vkpsHvCuBe8n14F+etwMiR7Bglvrqx/hEzqgqjWFGaK6c44ip KI9Jw7aLGGyFsxHFLtx1ZEBfCTBT/kjKzKqBYQRscs9F4cvcVmVWXvnuPuB6PfN9xMIx ZfwPOTsX1paQNueMIG2H0jzRjs7HYzPrSX8+/R5XhnSaQX50BjbtOAu6/61HCIYBn1Yd 6KJB2jiAHHaOSuP3I5JwNPkKdS3bJLNtG29AmVkZqvk9amUwOMfOT1Mk2hAV5cqbP39P iZRA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id n3-v6si7848038pld.347.2018.03.17.03.11.55; Sat, 17 Mar 2018 03:11:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=awsHA6Rx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752723AbeCQKLw (ORCPT + 28 others); Sat, 17 Mar 2018 06:11:52 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:42107 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752674AbeCQKLr (ORCPT ); Sat, 17 Mar 2018 06:11:47 -0400 Received: by mail-pl0-f65.google.com with SMTP id w15-v6so7300854plq.9 for ; Sat, 17 Mar 2018 03:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=awsHA6RxAGUZWq/zd2OjOVCMy1LwpomXwU5dsD1tORj1svjNp0ibhJQmXQ74iUbOCb rflIIyAxxix0vUMlZ82NmRmmIJiFckrMQ8EU76LNbU03gZBLfIkNgEfU83AP8JjeJqnG /00JI/3TVqeAoQioKXUj4FgPEDY24Ib1eDQAY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=sQxjh1tbOPyvHN+Vjxu0nDO2bU1GuQ6kcy6bpvVYgQk7Q0DBJRJDUQ3AZx7BqZ5kYM 6ATy+D/MXYE3q7qPAhoHPhf8VjOAtNDbVjyZgrEBwaGrBUCW+zAPJJN6RD/aR2A3+23F GbXG2l2d9ThIIP/PnIEi5PSOikkeJAmb0XtZ9l43mJOm5t1E0him0RJLHNfp5tvKPlg0 EzfO7tbV4DiTpG/20NqFvk1y+88IEX/g6E8lRG06yaG1XCgA5+QVA1Df7r0kIR3gOMj8 RwUhIsofgkLbKCivJ0PDND0oBuGHLGVAi+xEziCBxSJuBEWbAoM8HyQ+B+eBj2RXkac4 XrIg== X-Gm-Message-State: AElRT7FPCgDiKaitq+AuBqF/clWWi0xot9FffSXBUqmI8MzknRPe0U2R vf8Ub8DuqWMB3JwYzP7TLsuq X-Received: by 2002:a17:902:96a:: with SMTP id 97-v6mr5155853plm.183.1521281506931; Sat, 17 Mar 2018 03:11:46 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.11.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:11:46 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 06/12] clk: actions: Add mux clock support Date: Sat, 17 Mar 2018 15:39:46 +0530 Message-Id: <20180317100952.28538-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi mux clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-mux.c | 60 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-mux.h | 61 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 drivers/clk/actions/owl-mux.c create mode 100644 drivers/clk/actions/owl-mux.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 1f0917872c9d..2d4aa8f35d90 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o clk-owl-y += owl-gate.o +clk-owl-y += owl-mux.o diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c new file mode 100644 index 000000000000..f9c6cf2540e4 --- /dev/null +++ b/drivers/clk/actions/owl-mux.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL mux clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-mux.h" + +u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, + const struct owl_mux_hw *mux_hw) +{ + u32 reg; + u8 parent; + + regmap_read(common->regmap, mux_hw->reg, ®); + parent = reg >> mux_hw->shift; + parent &= BIT(mux_hw->width) - 1; + + return parent; +} + +static u8 owl_mux_get_parent(struct clk_hw *hw) +{ + struct owl_mux *mux = hw_to_owl_mux(hw); + + return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw); +} + +int owl_mux_helper_set_parent(const struct owl_clk_common *common, + struct owl_mux_hw *mux_hw, u8 index) +{ + u32 reg; + + regmap_read(common->regmap, mux_hw->reg, ®); + reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift); + regmap_write(common->regmap, mux_hw->reg, + reg | (index << mux_hw->shift)); + + return 0; +} + +static int owl_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct owl_mux *mux = hw_to_owl_mux(hw); + + return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index); +} + +const struct clk_ops owl_mux_ops = { + .get_parent = owl_mux_get_parent, + .set_parent = owl_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; diff --git a/drivers/clk/actions/owl-mux.h b/drivers/clk/actions/owl-mux.h new file mode 100644 index 000000000000..834284c8c3ae --- /dev/null +++ b/drivers/clk/actions/owl-mux.h @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL mux clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_MUX_H_ +#define _OWL_MUX_H_ + +#include "owl-common.h" + +struct owl_mux_hw { + u32 reg; + u8 shift; + u8 width; +}; + +struct owl_mux { + struct owl_mux_hw mux_hw; + struct owl_clk_common common; +}; + +#define OWL_MUX_HW(_reg, _shift, _width) \ + { \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + } + +#define OWL_MUX(_struct, _name, _parents, _reg, \ + _shift, _width, _flags) \ + struct owl_mux _struct = { \ + .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &owl_mux_ops, \ + _flags), \ + }, \ + } + +static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_mux, common); +} + +u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, + const struct owl_mux_hw *mux_hw); +int owl_mux_helper_set_parent(const struct owl_clk_common *common, + struct owl_mux_hw *mux_hw, u8 index); + +extern const struct clk_ops owl_mux_ops; + +#endif /* _OWL_MUX_H_ */ From patchwork Sat Mar 17 10:09:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 131965 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp490220ljb; Sat, 17 Mar 2018 03:12:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELuEMCQo8CM/+NBBshHQuj5J+cUj9fUalma/SHmk4xqqVlGEx994Hlks4LKCNGYehTBto5vT X-Received: by 10.99.135.67 with SMTP id i64mr4041234pge.346.1521281523362; Sat, 17 Mar 2018 03:12:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521281523; cv=none; d=google.com; s=arc-20160816; b=AXDIsxA6bDzORSE60H1c5Fi88kqZ7yuK5sg5uYs4oAnleJw3+HzOv6IR4waFxxI+vI XbyOHwZnUPMYT/EtKIki+PQPZktRhB8W/JtW0ZAcCwlG6SoZdKjwpcrwNGywew8lngPm 1nnpcNjDAPXkRVZYdytFSTh/S0YezTp4CUKuh+6/kbsUP7KWxQV0/60qbfD+1T2bynQP IG5xA9dQups4ljH2nEyQK98hjYda+kQl+hEyL+UxwZMA7AWhvGq5HeT2XtIH1fkHRuKY vLsp1Wz1ADczeyIL4FWArnbgHinLYebGXXOKnFyJLliNur/dl3f3sdWIWCraPzLfkOlq V8VQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id c15si7137320pfm.199.2018.03.17.03.12.03; Sat, 17 Mar 2018 03:12:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DSDJ3YUg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752787AbeCQKL7 (ORCPT + 28 others); Sat, 17 Mar 2018 06:11:59 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:38959 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752674AbeCQKLy (ORCPT ); Sat, 17 Mar 2018 06:11:54 -0400 Received: by mail-pg0-f68.google.com with SMTP id t6so178560pgt.6 for ; Sat, 17 Mar 2018 03:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Uy+OnSE0HzTbPuBqcNNil7FWRqCLLGEQ+YyxDvuuSwQ=; b=DSDJ3YUgUcXUGBpmDDwlkdaUAfgHvfufepbXZ52JYxNGvzxzsIP0Kfgug/wP4hkGDQ AgCv+ABnCW4ewSn8JBOCOZOChpET/4cgdVw3HrQofBtsooi4woaTJt7eK/P6m6pUOTNV eQQ2dgKdXaqV92kXBBIJMBn8tccEgOrtMOx/w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Uy+OnSE0HzTbPuBqcNNil7FWRqCLLGEQ+YyxDvuuSwQ=; b=OPLYXkRr3NSfpAV1bJU+/yIXe7QbdFKXp9J1P857UooVfD3iN/fFNHHaGslEupt0Iu S2nc8lEtZAJYnerFUmIV3+2qTXJErojFqqHDJJQtTFU4MdWm8UH0jq+DnwdCJaMVeeL3 RmnNVNoUO12oHQWZ9QwlTiuPsvBH02yaTxqy3USK5xP9TSQRoOAmeerOcPEXsKYQJW3u PEQqwzzP/ZuK1lg0QYvEq3WiUpvgUFZj7/Lm6JZCTL1s2BBAftRpeQqJtyoig88DoFVL 1rjElq3X7fPV8dskS/dzj1fZvrmrZIbGyjTRdbSnZ9lPSprrK/9GGjOzcVqv6EDwAq8C Qp6Q== X-Gm-Message-State: AElRT7Fiy2rJG88ohyvXronSaxO/bPpEXf+RG4JJzabSBI6VpQzASc17 K1cFgyTVY7Az+RpXLRjJcX38 X-Received: by 10.99.110.133 with SMTP id j127mr4060926pgc.79.1521281514056; Sat, 17 Mar 2018 03:11:54 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.11.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:11:53 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 07/12] clk: actions: Add divider clock support Date: Sat, 17 Mar 2018 15:39:47 +0530 Message-Id: <20180317100952.28538-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi divider clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-divider.c | 94 +++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-divider.h | 75 +++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/clk/actions/owl-divider.c create mode 100644 drivers/clk/actions/owl-divider.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 2d4aa8f35d90..5ce75df57e1a 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o clk-owl-y += owl-gate.o clk-owl-y += owl-mux.o +clk-owl-y += owl-divider.o diff --git a/drivers/clk/actions/owl-divider.c b/drivers/clk/actions/owl-divider.c new file mode 100644 index 000000000000..cddac00fe324 --- /dev/null +++ b/drivers/clk/actions/owl-divider.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL divider clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-divider.h" + +long owl_divider_helper_round_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return divider_round_rate(&common->hw, rate, parent_rate, + div_hw->table, div_hw->width, + div_hw->div_flags); +} + +static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_divider *div = hw_to_owl_divider(hw); + + return owl_divider_helper_round_rate(&div->common, &div->div_hw, + rate, parent_rate); +} + +unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long parent_rate) +{ + unsigned long val; + unsigned int reg; + + regmap_read(common->regmap, div_hw->reg, ®); + val = reg >> div_hw->shift; + val &= (1 << div_hw->width) - 1; + + return divider_recalc_rate(&common->hw, parent_rate, + val, div_hw->table, + div_hw->div_flags, + div_hw->width); +} + +static unsigned long owl_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_divider *div = hw_to_owl_divider(hw); + + return owl_divider_helper_recalc_rate(&div->common, + &div->div_hw, parent_rate); +} + +int owl_divider_helper_set_rate(const struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long parent_rate) +{ + unsigned long val; + unsigned int reg; + + val = divider_get_val(rate, parent_rate, div_hw->table, + div_hw->width, 0); + + regmap_read(common->regmap, div_hw->reg, ®); + reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift); + + regmap_write(common->regmap, div_hw->reg, + reg | (val << div_hw->shift)); + + return 0; +} + +static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_divider *div = hw_to_owl_divider(hw); + + return owl_divider_helper_set_rate(&div->common, &div->div_hw, + rate, parent_rate); +} + +const struct clk_ops owl_divider_ops = { + .recalc_rate = owl_divider_recalc_rate, + .round_rate = owl_divider_round_rate, + .set_rate = owl_divider_set_rate, +}; diff --git a/drivers/clk/actions/owl-divider.h b/drivers/clk/actions/owl-divider.h new file mode 100644 index 000000000000..92d3e3d23967 --- /dev/null +++ b/drivers/clk/actions/owl-divider.h @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL divider clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_DIVIDER_H_ +#define _OWL_DIVIDER_H_ + +#include "owl-common.h" + +struct owl_divider_hw { + u32 reg; + u8 shift; + u8 width; + u8 div_flags; + struct clk_div_table *table; +}; + +struct owl_divider { + struct owl_divider_hw div_hw; + struct owl_clk_common common; +}; + +#define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ + { \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _div_flags, \ + .table = _table, \ + } + +#define OWL_DIVIDER(_struct, _name, _parent, _reg, \ + _shift, _width, _table, _div_flags, _flags) \ + struct owl_divider _struct = { \ + .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \ + _div_flags, _table), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_divider_ops, \ + _flags), \ + }, \ + } + +static inline struct owl_divider *hw_to_owl_divider(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_divider, common); +} + +long owl_divider_helper_round_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long *parent_rate); + +unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long parent_rate); + +int owl_divider_helper_set_rate(const struct owl_clk_common *common, + const struct owl_divider_hw *div_hw, + unsigned long rate, + unsigned long parent_rate); + +extern const struct clk_ops owl_divider_ops; + +#endif /* _OWL_DIVIDER_H_ */ From patchwork Sat Mar 17 10:09:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 131970 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp491099ljb; Sat, 17 Mar 2018 03:13:06 -0700 (PDT) X-Google-Smtp-Source: AG47ELsXD1+zvCJK7I03/cD3WwFQgqxWGfY8q3/uHeYmi67aNz/Cvqr6LyoywpEuZnxVmwYv2Ism X-Received: by 2002:a17:902:f64:: with SMTP id 91-v6mr5195467ply.232.1521281586215; Sat, 17 Mar 2018 03:13:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521281586; cv=none; d=google.com; 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[209.132.180.67]) by mx.google.com with ESMTP id p17si6452929pge.348.2018.03.17.03.13.05; Sat, 17 Mar 2018 03:13:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ax8R+v8f; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753227AbeCQKNC (ORCPT + 28 others); Sat, 17 Mar 2018 06:13:02 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:43738 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752313AbeCQKMQ (ORCPT ); Sat, 17 Mar 2018 06:12:16 -0400 Received: by mail-pf0-f195.google.com with SMTP id j2so5146050pff.10 for ; Sat, 17 Mar 2018 03:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5bYICLgSgRZmZkeuTD84g/VsanmBFZQlJiqPBfwwlsc=; b=ax8R+v8fTTZyDZNJ10u7xWqeJpS7pBwwnmf6zqwl+CdXOTOOLJFI3zkJ3Sw7HMrBEO GKjt2NnUfY556jzALYVUSadUE//FPJJo5EGj18joL8WoKZZ+/SIg9JTt9oksJSkMQhfm cqYTR0SEHnGi/eFKNiuBz/KzD70L3Kpjg+qtw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5bYICLgSgRZmZkeuTD84g/VsanmBFZQlJiqPBfwwlsc=; b=pe0yhK/k+Ddm/J51XXeGPr7aeBqg1PrAOu6RwETPCNqwzZc3GG2lrLWfCRj4h5+A2g CNetmVwqzCYc/AdVx+YYuSH8FGJXsedZ6rE8gJQNRH9yN5gjndoDiSSY0X7K932Ent3B 4uqJv3HPOrdbHirevUiBs0cAGBIfHvlW0lQQOh8laN4QHLWdF40Gkh43Kdt9R9/JJcvn ybkrQDqCHGBtBadVdNe3Q0tLLxMDPWcwQKmeQIG9gvVRWNQ5ThW5tTHmhqLCavrGt2fX CYeIMpE0bMxhX8280l+NCE/Xbf/Qg64k3LHBhD1SIDbdIju+JytjZTcVn8eLIKnLEg+p /q4w== X-Gm-Message-State: AElRT7E+LJ+wJm+fOOe7nrXi+XK3Vu+vhi7kxDmfvlbH+lJKhp5aMulG fjS/ePTE+3I/XiGVSdVTtDeD X-Received: by 10.98.90.196 with SMTP id o187mr4394519pfb.170.1521281535612; Sat, 17 Mar 2018 03:12:15 -0700 (PDT) Received: from mani-Aspire-E5-573.domain.name ([171.49.203.57]) by smtp.gmail.com with ESMTPSA id i27sm3771625pfj.123.2018.03.17.03.12.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 17 Mar 2018 03:12:15 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v5 10/12] clk: actions: Add composite clock support Date: Sat, 17 Mar 2018 15:39:50 +0530 Message-Id: <20180317100952.28538-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> References: <20180317100952.28538-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi composite clock. This clock consists of gate, mux, divider, factor and fixed factor clocks. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-composite.c | 200 ++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-composite.h | 118 +++++++++++++++++++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/clk/actions/owl-composite.c create mode 100644 drivers/clk/actions/owl-composite.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index b618696ba54e..dc905b285bdc 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -6,3 +6,4 @@ clk-owl-y += owl-mux.o clk-owl-y += owl-divider.o clk-owl-y += owl-factor.o clk-owl-y += owl-fixed-factor.o +clk-owl-y += owl-composite.o diff --git a/drivers/clk/actions/owl-composite.c b/drivers/clk/actions/owl-composite.c new file mode 100644 index 000000000000..d0ffbfc2c34c --- /dev/null +++ b/drivers/clk/actions/owl-composite.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL composite clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-composite.h" + +static u8 owl_comp_get_parent(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_mux_helper_get_parent(&comp->common, &comp->mux_hw); +} + +static int owl_comp_set_parent(struct clk_hw *hw, u8 index) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_mux_helper_set_parent(&comp->common, &comp->mux_hw, index); +} + +static void owl_comp_disable(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + struct owl_clk_common *common = &comp->common; + + clk_gate_set(common, &comp->gate_hw, false); +} + +static int owl_comp_enable(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + struct owl_clk_common *common = &comp->common; + + clk_gate_set(common, &comp->gate_hw, true); + + return 0; +} + +static int owl_comp_is_enabled(struct clk_hw *hw) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + struct owl_clk_common *common = &comp->common; + + return clk_is_enabled(common, &comp->gate_hw); +} + +static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw, + rate, parent_rate); +} + +static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw, + parent_rate); +} + +static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw, + rate, parent_rate); +} + +static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_factor_helper_round_rate(&comp->common, + &comp->rate.factor_hw, + rate, parent_rate); +} + +static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_factor_helper_recalc_rate(&comp->common, + &comp->rate.factor_hw, + parent_rate); +} + +static int owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_factor_helper_set_rate(&comp->common, + &comp->rate.factor_hw, + rate, parent_rate); +} + +static long owl_comp_fix_fact_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_fix_fact_helper_round_rate(&comp->common, + &comp->rate.fix_fact_hw, + rate, parent_rate); +} + +static unsigned long owl_comp_fix_fact_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_composite *comp = hw_to_owl_comp(hw); + + return owl_fix_fact_helper_recalc_rate(&comp->common, + &comp->rate.fix_fact_hw, + parent_rate); +} + +static int owl_comp_fix_fact_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + /* + * We must report success but we can do so unconditionally because + * clk_fix_fact_round_rate returns values that ensure this call is a + * nop. + */ + + return 0; +} + +const struct clk_ops owl_comp_div_ops = { + /* mux_ops */ + .get_parent = owl_comp_get_parent, + .set_parent = owl_comp_set_parent, + + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, + + /* div_ops */ + .round_rate = owl_comp_div_round_rate, + .recalc_rate = owl_comp_div_recalc_rate, + .set_rate = owl_comp_div_set_rate, +}; + + +const struct clk_ops owl_comp_fact_ops = { + /* mux_ops */ + .get_parent = owl_comp_get_parent, + .set_parent = owl_comp_set_parent, + + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, + + /* fact_ops */ + .round_rate = owl_comp_fact_round_rate, + .recalc_rate = owl_comp_fact_recalc_rate, + .set_rate = owl_comp_fact_set_rate, +}; + +const struct clk_ops owl_comp_fix_fact_ops = { + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, + + /* fix_fact_ops */ + .round_rate = owl_comp_fix_fact_round_rate, + .recalc_rate = owl_comp_fix_fact_recalc_rate, + .set_rate = owl_comp_fix_fact_set_rate, +}; + + +const struct clk_ops owl_comp_pass_ops = { + /* mux_ops */ + .get_parent = owl_comp_get_parent, + .set_parent = owl_comp_set_parent, + + /* gate_ops */ + .disable = owl_comp_disable, + .enable = owl_comp_enable, + .is_enabled = owl_comp_is_enabled, +}; diff --git a/drivers/clk/actions/owl-composite.h b/drivers/clk/actions/owl-composite.h new file mode 100644 index 000000000000..0763ba1ce2ad --- /dev/null +++ b/drivers/clk/actions/owl-composite.h @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL composite clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_COMPOSITE_H_ +#define _OWL_COMPOSITE_H_ + +#include "owl-common.h" +#include "owl-mux.h" +#include "owl-gate.h" +#include "owl-factor.h" +#include "owl-fixed-factor.h" +#include "owl-divider.h" + +union owl_rate { + struct owl_divider_hw div_hw; + struct owl_factor_hw factor_hw; + struct owl_fix_fact_hw fix_fact_hw; +}; + +struct owl_composite { + struct owl_mux_hw mux_hw; + struct owl_gate_hw gate_hw; + union owl_rate rate; + struct owl_clk_common common; +}; + +#define OWL_COMP_DIV(_struct, _name, _parent, \ + _mux, _gate, _div, _flags) \ + struct owl_composite _struct = { \ + .mux_hw = _mux, \ + .gate_hw = _gate, \ + .rate.div_hw = _div, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &owl_comp_div_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ + _gate, _div, _flags) \ + struct owl_composite _struct = { \ + .gate_hw = _gate, \ + .rate.div_hw = _div, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_comp_div_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_FACTOR(_struct, _name, _parent, \ + _mux, _gate, _factor, _flags) \ + struct owl_composite _struct = { \ + .mux_hw = _mux, \ + .gate_hw = _gate, \ + .rate.factor_hw = _factor, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &owl_comp_fact_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ + _gate, _fix_fact, _flags) \ + struct owl_composite _struct = { \ + .gate_hw = _gate, \ + .rate.fix_fact_hw = _fix_fact, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_comp_fix_fact_ops,\ + _flags), \ + }, \ + } + +#define OWL_COMP_PASS(_struct, _name, _parent, \ + _mux, _gate, _flags) \ + struct owl_composite _struct = { \ + .mux_hw = _mux, \ + .gate_hw = _gate, \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parent, \ + &owl_comp_pass_ops,\ + _flags), \ + }, \ + } + +static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_composite, common); +} + +extern const struct clk_ops owl_comp_div_ops; +extern const struct clk_ops owl_comp_fact_ops; +extern const struct clk_ops owl_comp_fix_fact_ops; +extern const struct clk_ops owl_comp_pass_ops; + +#endif /* _OWL_COMPOSITE_H_ */ From patchwork Sat Mar 17 10:09:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 131968 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp490630ljb; Sat, 17 Mar 2018 03:12:30 -0700 (PDT) X-Google-Smtp-Source: AG47ELtFgZ5OuS3/BT64ytViyYZZZSa8calydGWh8tViQ11s054vtH7Ah4neURIEOSc0PJ2LxK62 X-Received: by 2002:a17:902:7482:: with SMTP id h2-v6mr5277966pll.264.1521281549988; Sat, 17 Mar 2018 03:12:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521281549; cv=none; d=google.com; s=arc-20160816; b=JS5hPJM5gfj54TGOe3/+M78HifxQ/g+cTkOVLZ8BJmtmyU2vAcXR4QvW6R4rz58Gqe B4nuWib8vpRVPV74XPjsM5cBjZ/QXPI4RZ8HrVSziPtwh0LU+BgaC8HsdBrmJl8onwSv z/Dj+Vsnojh6HWwR6y+GAlMoTPoRutaW9XXEHI80ZIqMaO7Boz9P8DNBQViVXIipBxlr M4ZU2Kj+njAQV8aN5LTdTmB/mnUg8YZaxYF//GawXvyN2jKTitQxRRV+lRsiQ4Rxe4hx tsc2S9aHfceyeBt5w5EgZyO6Xh/7ufTTvB2egm4vIv6XO1d+8z/0jUg7Hw0veB+NBGeT oPnA== ARC-Message-Signature: i=1; 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Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-pll.c | 194 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-pll.h | 92 ++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 drivers/clk/actions/owl-pll.c create mode 100644 drivers/clk/actions/owl-pll.h -- 2.14.1 diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index dc905b285bdc..22bf986bd67c 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -7,3 +7,4 @@ clk-owl-y += owl-divider.o clk-owl-y += owl-factor.o clk-owl-y += owl-fixed-factor.o clk-owl-y += owl-composite.o +clk-owl-y += owl-pll.o diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c new file mode 100644 index 000000000000..3560c7324f9c --- /dev/null +++ b/drivers/clk/actions/owl-pll.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL pll clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include +#include + +#include "owl-pll.h" + +static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) +{ + u32 mul; + + mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); + if (mul < pll_hw->min_mul) + mul = pll_hw->min_mul; + else if (mul > pll_hw->max_mul) + mul = pll_hw->max_mul; + + return mul &= mul_mask(pll_hw); +} + +static unsigned int _get_table_rate(const struct clk_pll_table *table, + unsigned int val) +{ + const struct clk_pll_table *clkt; + + for (clkt = table; clkt->rate; clkt++) + if (clkt->val == val) + return clkt->rate; + + return 0; +} + +static const struct clk_pll_table *_get_pll_table( + const struct clk_pll_table *table, unsigned long rate) +{ + const struct clk_pll_table *clkt; + + for (clkt = table; clkt->rate; clkt++) { + if (clkt->rate == rate) { + table = clkt; + break; + } else if (clkt->rate < rate) + table = clkt; + } + + return table; +} + +static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct owl_pll *pll = hw_to_owl_pll(hw); + struct owl_pll_hw *pll_hw = &pll->pll_hw; + const struct clk_pll_table *clkt; + u32 mul; + + if (pll_hw->table) { + clkt = _get_pll_table(pll_hw->table, rate); + return clkt->rate; + } + + /* fixed frequency */ + if (pll_hw->width == 0) + return pll_hw->bfreq; + + mul = owl_pll_calculate_mul(pll_hw, rate); + + return pll_hw->bfreq * mul; +} + +static unsigned long owl_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct owl_pll *pll = hw_to_owl_pll(hw); + struct owl_pll_hw *pll_hw = &pll->pll_hw; + const struct owl_clk_common *common = &pll->common; + u32 val; + + if (pll_hw->table) { + regmap_read(common->regmap, pll_hw->reg, &val); + + val = val >> pll_hw->shift; + val &= mul_mask(pll_hw); + + return _get_table_rate(pll_hw->table, val); + } + + /* fixed frequency */ + if (pll_hw->width == 0) + return pll_hw->bfreq; + + regmap_read(common->regmap, pll_hw->reg, &val); + + val = val >> pll_hw->shift; + val &= mul_mask(pll_hw); + + return pll_hw->bfreq * val; +} + +static int owl_pll_is_enabled(struct clk_hw *hw) +{ + struct owl_pll *pll = hw_to_owl_pll(hw); + struct owl_pll_hw *pll_hw = &pll->pll_hw; + const struct owl_clk_common *common = &pll->common; + u32 reg; + + regmap_read(common->regmap, pll_hw->reg, ®); + + return !!(reg & BIT(pll_hw->bit_idx)); +} + +static void owl_pll_set(const struct owl_clk_common *common, + const struct owl_pll_hw *pll_hw, bool enable) +{ + u32 reg; + + regmap_read(common->regmap, pll_hw->reg, ®); + + if (enable) + reg |= BIT(pll_hw->bit_idx); + else + reg &= ~BIT(pll_hw->bit_idx); + + regmap_write(common->regmap, pll_hw->reg, reg); +} + +static int owl_pll_enable(struct clk_hw *hw) +{ + struct owl_pll *pll = hw_to_owl_pll(hw); + const struct owl_clk_common *common = &pll->common; + + owl_pll_set(common, &pll->pll_hw, true); + + return 0; +} + +static void owl_pll_disable(struct clk_hw *hw) +{ + struct owl_pll *pll = hw_to_owl_pll(hw); + const struct owl_clk_common *common = &pll->common; + + owl_pll_set(common, &pll->pll_hw, false); +} + +static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct owl_pll *pll = hw_to_owl_pll(hw); + struct owl_pll_hw *pll_hw = &pll->pll_hw; + const struct owl_clk_common *common = &pll->common; + const struct clk_pll_table *clkt; + u32 val, reg; + + /* fixed frequency */ + if (pll_hw->width == 0) + return 0; + + if (pll_hw->table) { + clkt = _get_pll_table(pll_hw->table, rate); + val = clkt->val; + } else { + val = owl_pll_calculate_mul(pll_hw, rate); + } + + regmap_read(common->regmap, pll_hw->reg, ®); + + reg &= ~mul_mask(pll_hw); + reg |= val << pll_hw->shift; + + regmap_write(common->regmap, pll_hw->reg, reg); + + udelay(PLL_STABILITY_WAIT_US); + + return 0; +} + +const struct clk_ops owl_pll_ops = { + .enable = owl_pll_enable, + .disable = owl_pll_disable, + .is_enabled = owl_pll_is_enabled, + .round_rate = owl_pll_round_rate, + .recalc_rate = owl_pll_recalc_rate, + .set_rate = owl_pll_set_rate, +}; diff --git a/drivers/clk/actions/owl-pll.h b/drivers/clk/actions/owl-pll.h new file mode 100644 index 000000000000..0aae30abd5dc --- /dev/null +++ b/drivers/clk/actions/owl-pll.h @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL pll clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_PLL_H_ +#define _OWL_PLL_H_ + +#include "owl-common.h" + +/* last entry should have rate = 0 */ +struct clk_pll_table { + unsigned int val; + unsigned long rate; +}; + +struct owl_pll_hw { + u32 reg; + u32 bfreq; + u8 bit_idx; + u8 shift; + u8 width; + u8 min_mul; + u8 max_mul; + const struct clk_pll_table *table; +}; + +struct owl_pll { + struct owl_pll_hw pll_hw; + struct owl_clk_common common; +}; + +#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ + _width, _min_mul, _max_mul, _table) \ + { \ + .reg = _reg, \ + .bfreq = _bfreq, \ + .bit_idx = _bit_idx, \ + .shift = _shift, \ + .width = _width, \ + .min_mul = _min_mul, \ + .max_mul = _max_mul, \ + .table = _table, \ + } + +#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ + _shift, _width, _min_mul, _max_mul, _table, _flags) \ + struct owl_pll _struct = { \ + .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ + _width, _min_mul, \ + _max_mul, _table), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &owl_pll_ops, \ + _flags), \ + }, \ + } + +#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ + _shift, _width, _min_mul, _max_mul, _table, _flags) \ + struct owl_pll _struct = { \ + .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ + _width, _min_mul, \ + _max_mul, _table), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ + &owl_pll_ops, \ + _flags), \ + }, \ + } + +#define mul_mask(m) ((1 << ((m)->width)) - 1) +#define PLL_STABILITY_WAIT_US (50) + +static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_pll, common); +} + +extern const struct clk_ops owl_pll_ops; + +#endif /* _OWL_PLL_H_ */