From patchwork Tue Feb 9 16:40:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 379821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22CF9C433E6 for ; Tue, 9 Feb 2021 16:42:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C69CC64EC0 for ; Tue, 9 Feb 2021 16:42:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233013AbhBIQlz (ORCPT ); Tue, 9 Feb 2021 11:41:55 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:33249 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232906AbhBIQll (ORCPT ); Tue, 9 Feb 2021 11:41:41 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 64C5523E64; Tue, 9 Feb 2021 17:40:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612888857; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mxApDAXJmHKHUYvXyL5CsFbTjYayf0MgglmAfUCSgpY=; b=eBFjj+UaGtQPA/BKr2AnPStAmUqMfC9+JSq+o2sahE/3prRshJa9ga/XhH3KjApxByRwMc yIzb8n0sgUmtpTeHcrpkfu2b0AjPGBaCOixpJ2tRhFsU4zy+erFXhHbyB0jhDWygt4Bxeh VQPBwCYYwhPJ6zc5gumx8V4cW1Hzh6s= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next 1/9] net: phy: icplus: use PHY_ID_MATCH_MODEL() macro Date: Tue, 9 Feb 2021 17:40:43 +0100 Message-Id: <20210209164051.18156-2-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209164051.18156-1-michael@walle.cc> References: <20210209164051.18156-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Simpify the initializations of the structures. There is no functional change. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- drivers/net/phy/icplus.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index b632947cbcdf..4407b1eb1a3d 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -47,6 +47,10 @@ MODULE_LICENSE("GPL"); #define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d #define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2) +#define IP175C_PHY_ID 0x02430d80 +#define IP1001_PHY_ID 0x02430d90 +#define IP101A_PHY_ID 0x02430c54 + /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin * (pin number 21). The hardware default is RXER (receive error) mode. But it * can be configured to interrupt mode manually. @@ -329,9 +333,8 @@ static irqreturn_t ip101a_g_handle_interrupt(struct phy_device *phydev) static struct phy_driver icplus_driver[] = { { - .phy_id = 0x02430d80, + PHY_ID_MATCH_MODEL(IP175C_PHY_ID), .name = "ICPlus IP175C", - .phy_id_mask = 0x0ffffff0, /* PHY_BASIC_FEATURES */ .config_init = &ip175c_config_init, .config_aneg = &ip175c_config_aneg, @@ -339,17 +342,15 @@ static struct phy_driver icplus_driver[] = { .suspend = genphy_suspend, .resume = genphy_resume, }, { - .phy_id = 0x02430d90, + PHY_ID_MATCH_MODEL(IP1001_PHY_ID), .name = "ICPlus IP1001", - .phy_id_mask = 0x0ffffff0, /* PHY_GBIT_FEATURES */ .config_init = &ip1001_config_init, .suspend = genphy_suspend, .resume = genphy_resume, }, { - .phy_id = 0x02430c54, + PHY_ID_MATCH_MODEL(IP101A_PHY_ID), .name = "ICPlus IP101A/G", - .phy_id_mask = 0x0ffffff0, /* PHY_BASIC_FEATURES */ .probe = ip101a_g_probe, .config_intr = ip101a_g_config_intr, @@ -362,9 +363,9 @@ static struct phy_driver icplus_driver[] = { module_phy_driver(icplus_driver); static struct mdio_device_id __maybe_unused icplus_tbl[] = { - { 0x02430d80, 0x0ffffff0 }, - { 0x02430d90, 0x0ffffff0 }, - { 0x02430c54, 0x0ffffff0 }, + { PHY_ID_MATCH_MODEL(IP175C_PHY_ID) }, + { PHY_ID_MATCH_MODEL(IP1001_PHY_ID) }, + { PHY_ID_MATCH_MODEL(IP101A_PHY_ID) }, { } }; From patchwork Tue Feb 9 16:40:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 379820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A347C4332B for ; Tue, 9 Feb 2021 16:42:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BCD3264EAC for ; Tue, 9 Feb 2021 16:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233050AbhBIQmY (ORCPT ); Tue, 9 Feb 2021 11:42:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232995AbhBIQlq (ORCPT ); Tue, 9 Feb 2021 11:41:46 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2998AC061574; Tue, 9 Feb 2021 08:41:06 -0800 (PST) Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id ADEC223E6D; Tue, 9 Feb 2021 17:40:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612888858; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ggXo6TMoWYrrwtJbj3OGZvRr/reK/ZIs82Ig8HOKQc4=; b=TsDcQm697XQubGHMpWdS3eF/EurjUfHqboYsFbhwbAYgay5orcsmeOuvR1p1MU7oizHqL5 6WEX5Emw5O5dwvXELAjGuBYblCsFrl01smn6PGP/XTQGGp/hMb8Zupfx6Hhw1EjzR6Vql8 hZu0oRn42/IfahQ0XFm0DQS96pLZ0YQ= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next 3/9] net: phy: icplus: drop address operator for functions Date: Tue, 9 Feb 2021 17:40:45 +0100 Message-Id: <20210209164051.18156-4-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209164051.18156-1-michael@walle.cc> References: <20210209164051.18156-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Don't sometimes use the address operator and sometimes not. Drop it and make the code look uniform. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- drivers/net/phy/icplus.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index ae3cf61c5ac2..43b69addc0ce 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -336,16 +336,16 @@ static struct phy_driver icplus_driver[] = { PHY_ID_MATCH_MODEL(IP175C_PHY_ID), .name = "ICPlus IP175C", /* PHY_BASIC_FEATURES */ - .config_init = &ip175c_config_init, - .config_aneg = &ip175c_config_aneg, - .read_status = &ip175c_read_status, + .config_init = ip175c_config_init, + .config_aneg = ip175c_config_aneg, + .read_status = ip175c_read_status, .suspend = genphy_suspend, .resume = genphy_resume, }, { PHY_ID_MATCH_MODEL(IP1001_PHY_ID), .name = "ICPlus IP1001", /* PHY_GBIT_FEATURES */ - .config_init = &ip1001_config_init, + .config_init = ip1001_config_init, .suspend = genphy_suspend, .resume = genphy_resume, }, { @@ -355,7 +355,7 @@ static struct phy_driver icplus_driver[] = { .probe = ip101a_g_probe, .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, - .config_init = &ip101a_g_config_init, + .config_init = ip101a_g_config_init, .suspend = genphy_suspend, .resume = genphy_resume, } }; From patchwork Tue Feb 9 16:40:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 379819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C31FC433E0 for ; Tue, 9 Feb 2021 16:43:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1C76B64DD1 for ; Tue, 9 Feb 2021 16:43:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233066AbhBIQmp (ORCPT ); Tue, 9 Feb 2021 11:42:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233007AbhBIQlv (ORCPT ); Tue, 9 Feb 2021 11:41:51 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5190C06174A; Tue, 9 Feb 2021 08:41:10 -0800 (PST) Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id D40AA23E72; Tue, 9 Feb 2021 17:40:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612888860; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hJNVxqE7Xse8XBjBEKAe7Qk6Rnt0Snkjba3AveKRohU=; b=HijcEWfPxGz0uJt/Pxp18MnH9WYukHuyEoxWToXi4cz9PUNuCVEY1DOCKrzBY3RsBKcMQU K461ZQRSyoIK8yEzDE+B70a2SqXdJxUcZW2lBUZFS+wgc0EhmsMMkxZj2xwvuPBVFAJc+E 0RFs3vPUiY75R1nlIlna6k9lZ5jptEc= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next 5/9] net: phy: icplus: add IP101A/IP101G model detection Date: Tue, 9 Feb 2021 17:40:47 +0100 Message-Id: <20210209164051.18156-6-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209164051.18156-1-michael@walle.cc> References: <20210209164051.18156-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Signed-off-by: Michael Walle --- drivers/net/phy/icplus.c | 43 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index 036bac628b11..189a9a34ed5f 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -44,6 +44,8 @@ MODULE_LICENSE("GPL"); #define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1) #define IP101A_G_IRQ_LINK_CHANGE BIT(0) +#define IP101G_PAGE_CONTROL 0x14 +#define IP101G_PAGE_CONTROL_MASK GENMASK(4, 0) #define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d #define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2) @@ -61,8 +63,14 @@ enum ip101gr_sel_intr32 { IP101GR_SEL_INTR32_RXER, }; +enum ip101_model { + IP101A, + IP101G, +}; + struct ip101a_g_phy_priv { enum ip101gr_sel_intr32 sel_intr32; + enum ip101_model model; }; static int ip175c_config_init(struct phy_device *phydev) @@ -175,6 +183,39 @@ static int ip175c_config_aneg(struct phy_device *phydev) return 0; } +/* The IP101A and the IP101G share the same PHY identifier.The IP101G seems to + * be a successor of the IP101A and implements more functions. Amongst other + * things a page select register, which is not available on the IP101. Use this + * to distinguish these two. + */ +static int ip101a_g_detect_model(struct phy_device *phydev) +{ + struct ip101a_g_phy_priv *priv = phydev->priv; + int oldval, ret; + + oldval = phy_read(phydev, IP101G_PAGE_CONTROL); + if (oldval < 0) + return oldval; + + ret = phy_write(phydev, IP101G_PAGE_CONTROL, 0xffff); + if (ret) + return ret; + + ret = phy_read(phydev, IP101G_PAGE_CONTROL); + if (ret < 0) + return ret; + + if (ret == IP101G_PAGE_CONTROL_MASK) + priv->model = IP101G; + else + priv->model = IP101A; + + phydev_dbg(phydev, "Detected %s\n", + priv->model == IP101G ? "IP101G" : "IP101A"); + + return phy_write(phydev, IP101G_PAGE_CONTROL, oldval); +} + static int ip101a_g_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -203,7 +244,7 @@ static int ip101a_g_probe(struct phy_device *phydev) phydev->priv = priv; - return 0; + return ip101a_g_detect_model(phydev); } static int ip101a_g_config_init(struct phy_device *phydev) From patchwork Tue Feb 9 16:40:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 379818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE185C433E9 for ; Tue, 9 Feb 2021 16:43:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8DEF964ECE for ; Tue, 9 Feb 2021 16:43:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233111AbhBIQm6 (ORCPT ); Tue, 9 Feb 2021 11:42:58 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:36215 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233010AbhBIQlx (ORCPT ); Tue, 9 Feb 2021 11:41:53 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 4DB5323E7C; Tue, 9 Feb 2021 17:41:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612888861; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OLq7zojglq/Jan3SGQnLAO0bK4fFOVDgCTTyFGeMNaI=; b=b/7cPTGhXNinL68BjG1IHoJm6Rn8HLVpeMmw+hxdMQXLgrcdcIGIXz43rNCqJtB/5rPNVn MmuHuslkzIE2bHPyjFjf2gPlaLfODkLr+4YfYx8DO/Qrl2bOU5yfkazIAP9HnqUHxVWFJe in7ecyORSfnk+mk8820Pfuf7LmDCrGU= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next 8/9] net: phy: icplus: add PHY counter for IP101G Date: Tue, 9 Feb 2021 17:40:50 +0100 Message-Id: <20210209164051.18156-9-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209164051.18156-1-michael@walle.cc> References: <20210209164051.18156-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- drivers/net/phy/icplus.c | 78 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index 858b9326a72d..d1b57d81f281 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -51,6 +51,12 @@ MODULE_LICENSE("GPL"); #define IP101G_DEFAULT_PAGE 16 +#define IP101G_P1_CNT_CTRL 17 +#define CNT_CTRL_RX_EN BIT(13) +#define IP101G_P8_CNT_CTRL 17 +#define CNT_CTRL_RDCLR_EN BIT(15) +#define IP101G_CNT_REG 18 + #define IP175C_PHY_ID 0x02430d80 #define IP1001_PHY_ID 0x02430d90 #define IP101A_PHY_ID 0x02430c54 @@ -70,9 +76,20 @@ enum ip101_model { IP101G, }; +struct ip101g_hw_stat { + const char *name; + int page; +}; + +static struct ip101g_hw_stat ip101g_hw_stats[] = { + { "phy_crc_errors", 1 }, + { "phy_symbol_errors", 11, }, +}; + struct ip101a_g_phy_priv { enum ip101gr_sel_intr32 sel_intr32; enum ip101_model model; + u64 stats[ARRAY_SIZE(ip101g_hw_stats)]; }; static int ip175c_config_init(struct phy_device *phydev) @@ -254,6 +271,18 @@ static int ip101a_g_config_init(struct phy_device *phydev) struct ip101a_g_phy_priv *priv = phydev->priv; int oldpage, err; + /* Enable the PHY counters */ + err = phy_modify_paged(phydev, 1, IP101G_P1_CNT_CTRL, + CNT_CTRL_RX_EN, CNT_CTRL_RX_EN); + if (err) + return err; + + /* Clear error counters on read */ + err = phy_modify_paged(phydev, 8, IP101G_P8_CNT_CTRL, + CNT_CTRL_RDCLR_EN, CNT_CTRL_RDCLR_EN); + if (err) + return err; + oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE); /* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */ @@ -373,6 +402,52 @@ static int ip101a_g_write_page(struct phy_device *phydev, int page) return __phy_write(phydev, IP101G_PAGE_CONTROL, page); } +static int ip101a_g_get_sset_count(struct phy_device *phydev) +{ + struct ip101a_g_phy_priv *priv = phydev->priv; + + if (priv->model == IP101A) + return -EOPNOTSUPP; + + return ARRAY_SIZE(ip101g_hw_stats); +} + +static void ip101a_g_get_strings(struct phy_device *phydev, u8 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ip101g_hw_stats); i++) + strscpy(data + i * ETH_GSTRING_LEN, + ip101g_hw_stats[i].name, ETH_GSTRING_LEN); +} + +static u64 ip101a_g_get_stat(struct phy_device *phydev, int i) +{ + struct ip101g_hw_stat stat = ip101g_hw_stats[i]; + struct ip101a_g_phy_priv *priv = phydev->priv; + int val; + u64 ret; + + val = phy_read_paged(phydev, stat.page, IP101G_CNT_REG); + if (val < 0) { + ret = U64_MAX; + } else { + priv->stats[i] += val; + ret = priv->stats[i]; + } + + return ret; +} + +static void ip101a_g_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, u64 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ip101g_hw_stats); i++) + data[i] = ip101a_g_get_stat(phydev, i); +} + static struct phy_driver icplus_driver[] = { { PHY_ID_MATCH_MODEL(IP175C_PHY_ID), @@ -402,6 +477,9 @@ static struct phy_driver icplus_driver[] = { .read_page = ip101a_g_read_page, .write_page = ip101a_g_write_page, .soft_reset = genphy_soft_reset, + .get_sset_count = ip101a_g_get_sset_count, + .get_strings = ip101a_g_get_strings, + .get_stats = ip101a_g_get_stats, .suspend = genphy_suspend, .resume = genphy_resume, } }; From patchwork Tue Feb 9 16:40:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 379817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1076AC433E0 for ; Tue, 9 Feb 2021 16:44:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C3E2164DD1 for ; Tue, 9 Feb 2021 16:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233134AbhBIQnz (ORCPT ); Tue, 9 Feb 2021 11:43:55 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:36017 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233011AbhBIQlx (ORCPT ); Tue, 9 Feb 2021 11:41:53 -0500 Received: from mwalle01.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:fa59:71ff:fe9b:b851]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id DE4A923E7F; Tue, 9 Feb 2021 17:41:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1612888862; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hx8lbEiJ+gmDVJOKwmg0FXofM77nJY0HprEqCmZ0HO4=; b=oRBjltWzwVehv8bvEE/KBHhO8Ld+O8d/1tSPFyivCU+elIYjgb+nmTR5CBdYS2wyfCvAts OXhlrEmFbcoyBfi9SEQfnTUfkUrsbtnNQe9UmmbnT/Pjuvv0o8/Ohv/14Sf6LHpqIE60VH pyAbjSWKf3MhKKfuak+weiMrKkyysZ4= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Michael Walle Subject: [PATCH net-next 9/9] net: phy: icplus: add MDI/MDIX support for IP101A/G Date: Tue, 9 Feb 2021 17:40:51 +0100 Message-Id: <20210209164051.18156-10-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210209164051.18156-1-michael@walle.cc> References: <20210209164051.18156-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- drivers/net/phy/icplus.c | 91 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c index d1b57d81f281..a2fee2d08ec2 100644 --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c @@ -37,12 +37,17 @@ MODULE_LICENSE("GPL"); #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ #define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */ +#define IP101A_G_AUTO_MDIX_DIS BIT(11) #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */ #define IP101A_G_IRQ_ALL_MASK BIT(11) /* IRQ's inactive */ #define IP101A_G_IRQ_SPEED_CHANGE BIT(2) #define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1) #define IP101A_G_IRQ_LINK_CHANGE BIT(0) +#define IP101A_G_PHY_STATUS 18 +#define IP101A_G_MDIX BIT(9) +#define IP101A_G_PHY_SPEC_CTRL 30 +#define IP101A_G_FORCE_MDIX BIT(3) #define IP101G_PAGE_CONTROL 0x14 #define IP101G_PAGE_CONTROL_MASK GENMASK(4, 0) @@ -327,6 +332,90 @@ static int ip101a_g_config_init(struct phy_device *phydev) return phy_restore_page(phydev, oldpage, err); } +static int ip101a_g_read_status(struct phy_device *phydev) +{ + int oldpage, ret, stat1, stat2; + + ret = genphy_read_status(phydev); + if (ret) + return ret; + + oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE); + + ret = __phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); + if (ret < 0) + goto out; + stat1 = ret; + + ret = __phy_read(phydev, IP101A_G_PHY_SPEC_CTRL); + if (ret < 0) + goto out; + stat2 = ret; + + if (stat1 & IP101A_G_AUTO_MDIX_DIS) { + if (stat2 & IP101A_G_FORCE_MDIX) + phydev->mdix_ctrl = ETH_TP_MDI_X; + else + phydev->mdix_ctrl = ETH_TP_MDI; + } else { + phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + } + + if (stat2 & IP101A_G_MDIX) + phydev->mdix = ETH_TP_MDI_X; + else + phydev->mdix = ETH_TP_MDI; + + ret = 0; + +out: + return phy_restore_page(phydev, oldpage, ret); +} + +static int ip101a_g_config_mdix(struct phy_device *phydev) +{ + u16 ctrl = 0, ctrl2 = 0; + int oldpage, ret; + + switch (phydev->mdix_ctrl) { + case ETH_TP_MDI: + ctrl = IP101A_G_AUTO_MDIX_DIS; + break; + case ETH_TP_MDI_X: + ctrl = IP101A_G_AUTO_MDIX_DIS; + ctrl2 = IP101A_G_FORCE_MDIX; + break; + case ETH_TP_MDI_AUTO: + break; + default: + return 0; + } + + oldpage = phy_select_page(phydev, IP101G_DEFAULT_PAGE); + + ret = __phy_modify(phydev, IP10XX_SPEC_CTRL_STATUS, + IP101A_G_AUTO_MDIX_DIS, ctrl); + if (ret) + goto out; + + ret = __phy_modify(phydev, IP101A_G_PHY_SPEC_CTRL, + IP101A_G_FORCE_MDIX, ctrl2); + +out: + return phy_restore_page(phydev, oldpage, ret); +} + +static int ip101a_g_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret = ip101a_g_config_mdix(phydev); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + static int ip101a_g_ack_interrupt(struct phy_device *phydev) { int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS); @@ -474,6 +563,8 @@ static struct phy_driver icplus_driver[] = { .config_intr = ip101a_g_config_intr, .handle_interrupt = ip101a_g_handle_interrupt, .config_init = ip101a_g_config_init, + .config_aneg = ip101a_g_config_aneg, + .read_status = ip101a_g_read_status, .read_page = ip101a_g_read_page, .write_page = ip101a_g_write_page, .soft_reset = genphy_soft_reset,