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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id k15sm13483489pgt.35.2021.02.08.15.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Feb 2021 15:39:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/4] exec: Move TranslationBlock typedef to qemu/typedefs.h Date: Mon, 8 Feb 2021 15:39:03 -0800 Message-Id: <20210208233906.479571-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208233906.479571-1-richard.henderson@linaro.org> References: <20210208233906.479571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, cfontana@suse.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This also means we don't need an extra declaration of the structure in hw/core/cpu.h. Signed-off-by: Richard Henderson --- include/exec/tb-context.h | 1 - include/hw/core/cpu.h | 4 +--- include/hw/core/tcg-cpu-ops.h | 3 +-- include/qemu/typedefs.h | 1 + target/arm/internals.h | 3 +-- target/cris/translate.c | 2 +- target/lm32/translate.c | 2 +- target/moxie/translate.c | 2 +- target/unicore32/translate.c | 2 +- 9 files changed, 8 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index ec4c13b455..cc33979113 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -26,7 +26,6 @@ #define CODE_GEN_HTABLE_BITS 15 #define CODE_GEN_HTABLE_SIZE (1 << CODE_GEN_HTABLE_BITS) -typedef struct TranslationBlock TranslationBlock; typedef struct TBContext TBContext; struct TBContext { diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 38d813c389..c005d3dc2d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -74,8 +74,6 @@ typedef enum MMUAccessType { typedef struct CPUWatchpoint CPUWatchpoint; -struct TranslationBlock; - /* see tcg-cpu-ops.h */ struct TCGCPUOps; @@ -375,7 +373,7 @@ struct CPUState { IcountDecr *icount_decr_ptr; /* Accessed in parallel; all accesses must be atomic */ - struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; + TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; struct GDBRegisterState *gdb_regs; int gdb_num_regs; diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index ccc97d1894..ac3bb051f2 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -30,8 +30,7 @@ struct TCGCPUOps { * If more state needs to be restored, the target must implement a * function to restore all the state, and register it here. */ - void (*synchronize_from_tb)(CPUState *cpu, - const struct TranslationBlock *tb); + void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); /** @cpu_exec_enter: Callback for cpu_exec preparation */ void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index dc39b05c30..ee60eb3de4 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -120,6 +120,7 @@ typedef struct ReservedRegion ReservedRegion; typedef struct SavedIOTLB SavedIOTLB; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; +typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; typedef struct Visitor Visitor; typedef struct VMChangeStateEntry VMChangeStateEntry; diff --git a/target/arm/internals.h b/target/arm/internals.h index 448982dd2f..7d26ce0c9d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,8 +172,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); #ifdef CONFIG_TCG -void arm_cpu_synchronize_from_tb(CPUState *cs, - const struct TranslationBlock *tb); +void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ diff --git a/target/cris/translate.c b/target/cris/translate.c index c893f877ab..65c168c0c7 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -132,7 +132,7 @@ typedef struct DisasContext { int delayed_branch; - struct TranslationBlock *tb; + TranslationBlock *tb; int singlestep_enabled; } DisasContext; diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 030b232d66..20c70d03f1 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -93,7 +93,7 @@ typedef struct DisasContext { unsigned int tb_flags, synced_flags; /* tb dependent flags. */ int is_jmp; - struct TranslationBlock *tb; + TranslationBlock *tb; int singlestep_enabled; uint32_t features; diff --git a/target/moxie/translate.c b/target/moxie/translate.c index d5fb27dfb8..24a742b25e 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -36,7 +36,7 @@ /* This is the state at translation time. */ typedef struct DisasContext { - struct TranslationBlock *tb; + TranslationBlock *tb; target_ulong pc, saved_pc; uint32_t opcode; uint32_t fp_status; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 962f9877a0..370709c9ea 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -34,7 +34,7 @@ typedef struct DisasContext { int condjmp; /* The label that will be jumped to when the instruction is skipped. */ TCGLabel *condlabel; - struct TranslationBlock *tb; + TranslationBlock *tb; int singlestep_enabled; #ifndef CONFIG_USER_ONLY int user; From patchwork Mon Feb 8 23:39:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 379153 Delivered-To: patch@linaro.org Received: by 2002:a17:906:48d2:0:0:0:0 with SMTP id d18csp5019438ejt; Mon, 8 Feb 2021 16:28:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJw+Wk96GA+hpIqgPGsD5QrmOphV9N3FXzGaCrfIzCEAAy/AMGGLYD3kE+IriUjIxYLGwOaP X-Received: by 2002:a25:6d8a:: with SMTP id i132mr29856986ybc.337.1612830530529; Mon, 08 Feb 2021 16:28:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612830530; cv=none; d=google.com; s=arc-20160816; b=B91v5tt4S2movAR1Yh3p6mWARTwjHiahyPxxDq9umwTDKXv5sKlkI+MfuaZR9c97Cn V1v7Ml+un1Eb4UFGS/UOlpAw0IH90EWWIPIYfvNwpWGB+StGoQ+vMYqEZ5VuxxEGEAT6 Hl/m8Gtk8K24QLI0BcSF5/rG0BFIdIsLIg3EJn0o3c4VUF312KuKYrFK+fTpgw4U5QJ8 syIMYz97LAGcAfaW6LlNH1j8kw7ge7Uk9m09Ju95BIPFM+WJXlxYi8gpmm10sFVdAolP ue5tWoNk0qyv+uGTU9pr6zD5CJIxKQatOIX6QQu8ifBhtfjl+Hf8beBJHJ5QpfMF1EsD XhSw== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id k15sm13483489pgt.35.2021.02.08.15.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Feb 2021 15:39:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/4] accel/tcg: Create io_recompile_replay_branch hook Date: Mon, 8 Feb 2021 15:39:04 -0800 Message-Id: <20210208233906.479571-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208233906.479571-1-richard.henderson@linaro.org> References: <20210208233906.479571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, cfontana@suse.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a hook in which to split out the mips and sh4 ifdefs from cpu_io_recompile. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 10 ++++++++++ accel/tcg/translate-all.c | 17 +++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index ac3bb051f2..ddf334411f 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -88,6 +88,16 @@ struct TCGCPUOps { */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); + /** + * @io_recompile_replay_branch: Callback for cpu_io_recompile. + * + * The cpu has been stoped, and cpu_restore_state_from_tb has been + * called. If the faulting instruction is in a delay slot, and the + * target architecture requires re-execution of the branch, then + * adjust the cpu state as required and return true. + */ + bool (*io_recompile_replay_branch)(CPUState *cpu, + const TranslationBlock *tb); #endif /* CONFIG_SOFTMMU */ #endif /* NEED_CPU_H */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 81d4c83f22..6eb37883bd 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -60,6 +60,7 @@ #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" #include "qapi/error.h" +#include "hw/core/tcg-cpu-ops.h" #include "internal.h" /* #define DEBUG_TB_INVALIDATE */ @@ -2420,6 +2421,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) CPUArchState *env = cpu->env_ptr; #endif TranslationBlock *tb; + CPUClass *cc; uint32_t n; tb = tcg_tb_lookup(retaddr); @@ -2429,11 +2431,18 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) } cpu_restore_state_from_tb(cpu, tb, retaddr, true); - /* On MIPS and SH, delay slot instructions can only be restarted if - they were already the first instruction in the TB. If this is not - the first instruction in a TB then re-execute the preceding - branch. */ + /* + * Some guests must re-execute the branch when re-executing a delay + * slot instruction. When this is the case, adjust icount and N + * to account for the re-execution of the branch. + */ n = 1; + cc = CPU_GET_CLASS(cpu); + if (cc->tcg_ops->io_recompile_replay_branch && + cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { + cpu_neg(cpu)->icount_decr.u16.low++; + n = 2; + } #if defined(TARGET_MIPS) if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && env->active_tc.PC != tb->pc) { From patchwork Mon Feb 8 23:39:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 379147 Delivered-To: patch@linaro.org Received: by 2002:a17:906:48d2:0:0:0:0 with SMTP id d18csp5017723ejt; Mon, 8 Feb 2021 16:25:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJzL6nnXsU6Z2IRIPCud8H22sAKi2Cnx2qruW6iFElgZ3whyEVZOlXlVitZtYEbDRmST7N9a X-Received: by 2002:a25:412:: with SMTP id 18mr11064704ybe.366.1612830308513; Mon, 08 Feb 2021 16:25:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612830308; cv=none; d=google.com; s=arc-20160816; b=TJKzu59RPxUHfpmF8J6aalGM7+pjKEqvAKoJoGNEijlpd9OBmFC6JMceoc1++Dljlq tS7xPokV6oz0Xt7KCIPNnf61QkQ4ravedyI/KKaqec98I2bpryuQH2tRi0BEsB6WTigp I7jkkJ6UP5M88ayQ/PX9gL1T2M0Fdnvi45BsmE3flO6lYVlNNL4/mqLHazR1NlFNvvqb HoHX8uMnwm0v+CVcTMAtGhJ2rGZH+JWXYjJDhf9+OMZqkMOQPYhCGp8RwK76BzdN5SvC G46IiRrj4lH1tjIJwM7ondpTp4XBRm6L8VaXsGOBaVwEdjthxnGAbNHzbHvzkOVJU82H 4Cdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bvXiadaSGeRqxaWd2p/qsJeoAY+3ssYrogfEW/VR4Cw=; b=pi3773/LV62oqg/mt2Ah0RFrWCcRdVNpBjeLkyV0oqq0lSNDdSct1XTNwZUZnsPU7X XEJEzUPNKJC0PJHDlol7/rNcos44NoLsYCpsmMozrZSxkdt0ZehIbDmbSKmzZrOe8d9P rNHVH9KqCHumlIvBOYal4yDQi5M/AsaWlCDNz3nRgBdUnPEAWj7Yi/aVinaGlp8o5cKC xUuEqgIvLFslxUZvGfpYwWwbceBGZxz4448SkloQxHyOc4yazmXca/GoN31TMJTNahVu e5TCOPwm1dxCf0liwzQguSd3lwwJr5hn/dZgWrmgBxnH62WA6FX4tzHQ+9ktu4lmJWl8 AHAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xshexf77; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id k15sm13483489pgt.35.2021.02.08.15.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Feb 2021 15:39:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/4] target/mips: Create mips_io_recompile_replay_branch Date: Mon, 8 Feb 2021 15:39:05 -0800 Message-Id: <20210208233906.479571-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208233906.479571-1-richard.henderson@linaro.org> References: <20210208233906.479571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, cfontana@suse.de, Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the code from accel/tcg/translate-all.c to target/mips/cpu.c. Signed-off-by: Richard Henderson --- Cc: Philippe Mathieu-Daudé Cc: Aurelien Jarno Cc: Jiaxun Yang --- accel/tcg/translate-all.c | 12 ++---------- target/mips/cpu.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6eb37883bd..470657b02a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2417,7 +2417,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) */ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { -#if defined(TARGET_MIPS) || defined(TARGET_SH4) +#if defined(TARGET_SH4) CPUArchState *env = cpu->env_ptr; #endif TranslationBlock *tb; @@ -2443,15 +2443,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cpu_neg(cpu)->icount_decr.u16.low++; n = 2; } -#if defined(TARGET_MIPS) - if ((env->hflags & MIPS_HFLAG_BMASK) != 0 - && env->active_tc.PC != tb->pc) { - env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - cpu_neg(cpu)->icount_decr.u16.low++; - env->hflags &= ~MIPS_HFLAG_BMASK; - n = 2; - } -#elif defined(TARGET_SH4) +#if defined(TARGET_SH4) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 && env->pc != tb->pc) { env->pc -= 2; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ad163ead62..bf70c77295 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -268,6 +268,23 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } + +# ifndef CONFIG_USER_ONLY +static bool mips_io_recompile_replay_branch(CPUState *cs, + const TranslationBlock *tb) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) != 0 + && env->active_tc.PC != tb->pc) { + env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &= ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} +# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ static bool mips_cpu_has_work(CPUState *cs) @@ -679,6 +696,7 @@ static struct TCGCPUOps mips_tcg_ops = { .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, .do_unaligned_access = mips_cpu_do_unaligned_access, + .io_recompile_replay_branch = mips_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ From patchwork Mon Feb 8 23:39:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378600 Delivered-To: patch@linaro.org Received: by 2002:a17:906:48d2:0:0:0:0 with SMTP id d18csp4993260ejt; Mon, 8 Feb 2021 15:40:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJyjdq9zuNFrnchgsglntkj4Tg3PGB9roYqKph6iLOTvf5+3mCMAMpgopb3IQwTc+6WEGySs X-Received: by 2002:a05:6902:701:: with SMTP id k1mr28762319ybt.342.1612827632164; Mon, 08 Feb 2021 15:40:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612827632; cv=none; d=google.com; s=arc-20160816; b=JAQM+LUsDAuMTxFTMgWrsBk6O4M65QY0LyFIoNC3VROpe6bYHgkzNpCD5/E9ZT75SR jvJhkUeSgUfASJG8LpkhqnnpgDhIiuc160xadm2U5+hlF5ofs+RS7BHlHmxcZUHpOOJh +YX8EQDuSfWF/rOG6EHUoS2fN0ppVKcfHeGlFirYo6Up09iaRUrotStFPmZfP7uHoDMd q6r99UgBZB1VK+m80zw4WmyMKzM3j+/2THncOXzhYZoS0qZp0t2SCTlop2XA+0CFTzpD ebiqy+7YwyYt3CbB8LL3k0oyFcqX1IyJ+yYkoU8NmrsXclr47jFuxD+mVPajHXp2AbgM m29Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eL4WqFDBuNtlcGfpllQU5OAqdTK3sQa+xgiSdwASR9g=; b=xPkjx7xbUoy8QPJJrkCrrzgQDYQQ3VlvVjXX3iOo6VqWzFX9s+5194/0OdNacjyAL1 EU+YoLaD9IHZBLybBbLRdy9NGE3zBthxdKBgEQ3d2ZClq5j7/M40l4OatzLWGqFL4aLY rdMG4eh3nTBlr74Jaow5jvbA2PHK2ml0EKvCG6DBycZ37vZO3ecRFIgoFtpIfpgbuV8S hkqCM4NJPf8tS3TXk/0/qaOrHdY45CS287cq1/kihkFrHCGbE6STsgHgZPHv2kkal5xe zCU+jZqPq8yeRSFN7hHy3qpWldpPh618xCmoZYgA2YSbO9JqMDyM9p4nvR1ecLxjDE3h o/Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mKokqLWp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id k15sm13483489pgt.35.2021.02.08.15.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Feb 2021 15:39:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/4] target/sh4: Create superh_io_recompile_replay_branch Date: Mon, 8 Feb 2021 15:39:06 -0800 Message-Id: <20210208233906.479571-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208233906.479571-1-richard.henderson@linaro.org> References: <20210208233906.479571-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, cfontana@suse.de, Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the code from accel/tcg/translate-all.c to target/sh4/cpu.c. Signed-off-by: Richard Henderson --- Cc: Yoshinori Sato --- accel/tcg/translate-all.c | 12 ------------ target/sh4/cpu.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 470657b02a..b8ad95aa1b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2417,9 +2417,6 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr) */ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { -#if defined(TARGET_SH4) - CPUArchState *env = cpu->env_ptr; -#endif TranslationBlock *tb; CPUClass *cc; uint32_t n; @@ -2443,15 +2440,6 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cpu_neg(cpu)->icount_decr.u16.low++; n = 2; } -#if defined(TARGET_SH4) - if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 - && env->pc != tb->pc) { - env->pc -= 2; - cpu_neg(cpu)->icount_decr.u16.low++; - env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); - n = 2; - } -#endif /* Generate a new TB executing the I/O insn. */ cpu->cflags_next_tb = curr_cflags() | CF_LAST_IO | n; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index a78d283bc8..ac65c88f1f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,6 +43,23 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; } +#ifndef CONFIG_USER_ONLY +static bool superh_io_recompile_replay_branch(CPUState *cs, + const TranslationBlock *tb) +{ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + + if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 + && env->pc != tb->pc) { + env->pc -= 2; + env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); + return true; + } + return false; +} +#endif + static bool superh_cpu_has_work(CPUState *cs) { return cs->interrupt_request & CPU_INTERRUPT_HARD; @@ -217,6 +234,7 @@ static struct TCGCPUOps superh_tcg_ops = { #ifndef CONFIG_USER_ONLY .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, + .io_recompile_replay_branch = superh_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ };