From patchwork Sun Feb 7 23:12:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 378167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 456BBC433E0 for ; Sun, 7 Feb 2021 23:15:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E1F964E32 for ; Sun, 7 Feb 2021 23:15:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229590AbhBGXPT (ORCPT ); Sun, 7 Feb 2021 18:15:19 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:1047 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229570AbhBGXPS (ORCPT ); Sun, 7 Feb 2021 18:15:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612739730; x=1644275730; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6K57gJ4d4JJEae1PJW0yBIWM0fdObKVyG7NMETneATc=; b=oD+RIL1bfmjAwCuVWOhcb+OSUrfW5h55FMOjk1RhLFQ0bb+FnsL2yUBH se7WkJNA6uf+htXOVTxsFbETEWM/4sFoyZ0ti6eAlLhr4UB5ntIJO97ph m4uH5RT+UEIIPUqd8LBeO+71yECfP3Z1USQ//7qjcqZAwAbx733OcEJ3r RuaUS8L0BuYjIboLwcYvTA4VCXakwC0RTJrxF1tjYvY1UX5SyV9PG/cIt N/u+F0vdsxrOQTaEslKJjwKZ+z/7u1Uv+uJ0hPwJG2GEkMELkxXXOiFBR z1hnQlSXmHXB+GnqrVXh/6+YLhXO6lifK24sfVL5kjkmFOwNGdJ4ztec8 Q==; IronPort-SDR: dymqyBjr2fzJC4CsEzDagWg3mbCwZyvSmk6cvUArEvtqV845JY4F0TBaBTGfubNTE0Cd1kp1az f0lKk1w4RfE7no2RFOkkK4v6Lpw4e4xOu8XdDZ+LD6psShAbYKivscXMbIf2iLPMSipUr5RTTZ 4oPd816MJB5Te7BHtgzwtf2sCBsNHQz7qO0J421sj9nvSK1sChUJ9cc+ky68AWVKSIBpdEp473 gICHCcSRGrUsAsvWG6VqWZySSP3FSUKuuMV63HChscDD8/EG2pUSmyc0hPpc5iljj4fxZTAZUp nEU= X-IronPort-AV: E=Sophos;i="5.81,160,1610380800"; d="scan'208";a="263503244" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Feb 2021 07:32:28 +0800 IronPort-SDR: z8EUlrI99NAYdkUttR5AYXWWG3XOJjrUt77dhr28307kZ4ALaDXGecvbcRRq5Xs/gwGK/vdfMr 6apFbbWnztFwDeQ4jlD+X+ysVZSVBwvfTQqxCOF3ARGcVbXTcWWAKAxDTcXaPNsaqMt15RdqCx B4+Yq1N3yExueSB9ca9/C85pkmfBhBR6A+atZcDam8G1r4Pfdgts+E/pAZ3+B2yuyHu7NyWOPC EMHnsw9en+tAltCo26vFBgnRwDHCllp3e67q3SKrLR7hOk39xMZQxZyVtjUscRj0WuEeq2OHaj EcM64+DKS8OlnutBLuEv4JqM Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2021 14:56:59 -0800 IronPort-SDR: GZpnlkHSqUSIz1nLJHVnoFn/yP2F6QQ0+fdh5vknXlqFx0EVk+X7bc+1aj6Kjv7exdCVpJK3Pc 9jik/n472IR6V2Gru/35ssynQ9utMmEvzTCEeWayRBpEpGfOirFxEeHaaaOh8hNHbvZHF2fK01 VZQK4+qcE1uh8SbWJHmhwgtJyHKiVuKzVBBPPD4NMMIa9KPdLLeomsJ0jj2CmaTkHlVqcLoTcv 27hh6HrIdOs8IQ5Gw+hxHn8+1SOwjSBEycDhuxZYK13C21renIOPr0YQJIRsyiZL2MvtwHlUCJ CEs= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:05 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v17 03/16] dt-bindings: update risc-v cpu properties Date: Mon, 8 Feb 2021 08:12:43 +0900 Message-Id: <20210207231256.115130-4-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Reviewed-by: Anup Patel Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: From patchwork Sun Feb 7 23:12:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 378166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1962FC433E0 for ; Sun, 7 Feb 2021 23:16:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0EB664E2A for ; Sun, 7 Feb 2021 23:16:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229609AbhBGXQB (ORCPT ); Sun, 7 Feb 2021 18:16:01 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:1047 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbhBGXQA (ORCPT ); Sun, 7 Feb 2021 18:16:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612739793; x=1644275793; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AIY+mENCG0OfDogqN2TK/zkNool8y2CBwzDhCDvMBTc=; b=i/AphwM5ls+3GH7h3kasb5NdRhXJ+NwAAuTBSnsARBygY6mR4OCPi3Cb 7GUmukB+EZ6B852P9ZJD/9uXWCPuOxCuLjp+4lTN/qRi1POhPv0p7RPYu YPdHZIVBAX/NqkBEfNLWxwnllftVNH67m+SL11RYHluRFK7zT5Jmhurmu 9Xgq1J0DfNOKXFRYZ4AgiJnaAMuQ33nSIY4euhpd7cMxnWgNbgLYThM56 r6NsSXdnhouCkrLERa/CrgTY3GkUaKuqYyL8t1ch0uuW/mhOBcIXXlWUY TQK/DUoUH0HYr1EwcF9eK8iS6imOzwJk9F+ySMex3Pw9VvqmjLYRhS4TN A==; IronPort-SDR: RgkN4UC6EVV0QcpYD+KVkbg+Mwsxbk3kfZ+G0leqN1OX3PIzOHGZ1wE+ao9LulvTZXyaWwCG8H JfJV1aUyEMm/4d0de6GAQOmucFOiDC1ht6DlrH3kTut7T6khXAV6d5Ly8/Oc1m6IbzDhfUhx18 sczdmqPT3TVj2q9A8XCfT8sn7StityVCXJeiIOxfh3ZgMG7vwwe+M7rELFn7Lb8+mzqSkKR7AW GUHoDqUo+iTh9GOZ/jtG+4F8EyzBtCqBooYVT+/9BoQunVkYu8A/t5/OjNqeHArXXXVqfpSdCA JCo= X-IronPort-AV: E=Sophos;i="5.81,160,1610380800"; d="scan'208";a="263503253" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Feb 2021 07:32:36 +0800 IronPort-SDR: hVIqWyTOedhKpeIizrzJJtCeblLxLK0VdLi3rd/ZstQkTG5l2xh47AVOdfxXPr7r85JSh5i4Co O2VRmD+1hbn9lP5yL7hJ9zSlZjBCbxOrheEbRG8vPZGN71Ck42+IR4aXXD+rtnyq2SzuhYwcFs X2Q22VCZxCmO+2v1Jqs7zjX844jnk0+AP6MXFLgPzR666pLVn2ZyifhL6vw5c9KKW3RgBsi2dK 4xh73NRZlQlFJcPUhTiday0yXd6gBou6j5XLH93YsWWOEDXXUMYTnbr9OgFd4bP1JeHjtAWZsB bPetRP6r+HS+XPXbjk6S4RxB Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2021 14:57:04 -0800 IronPort-SDR: hAXhT1+T+Hypmn8iiSEXz+UmnGq2tzSPYwZkH+S3BE8rqCZa0tlhOxGctiQxYb8ypGAflVuQ4S xDGYkC65V3ZrJbcBzh4Y8Wrc6yDVQQsBmQWqMqBTGyRmuU6VY0V5nal8jbtNU4ONxNLTaIZTf8 NBnktXpKHd3D4t8hdIKGmmNEYHepVeVmiINRafDx2X6WHEja1QtWzeWD5oInCBGuvdyZ1pG+4T luIj1aZ+/8JCGMZXOAnJnHQXplYt6sj9wBN9EGfsvylIAoqIkookSNs0GnHdIOsZU9KJ1/hEuu VpU= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:10 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v17 06/16] dt-bindings: update sifive uart compatible string Date: Mon, 8 Feb 2021 08:12:46 +0900 Message-Id: <20210207231256.115130-7-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible string "canaan,k210-uarths" to the sifive uart bindings to indicate the use of this IP block in the Canaan Kendryte K210 SoC. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Acked-by: Rob Herring --- Documentation/devicetree/bindings/serial/sifive-serial.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 3ac5c7ff2758..5fa94dacbba9 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -20,6 +20,7 @@ properties: - enum: - sifive,fu540-c000-uart - sifive,fu740-c000-uart + - canaan,k210-uarths - const: sifive,uart0 description: From patchwork Sun Feb 7 23:12:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 378165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3E8EC433DB for ; Sun, 7 Feb 2021 23:16:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B091964E31 for ; Sun, 7 Feb 2021 23:16:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229581AbhBGXQQ (ORCPT ); Sun, 7 Feb 2021 18:16:16 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:64368 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbhBGXQQ (ORCPT ); Sun, 7 Feb 2021 18:16:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612739817; x=1644275817; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sry4Jcxj7WaCMHpIVu5N/bY5as1f1P4twJ4S9BPW/Dg=; b=ah+fe0HVD0bYZvK27ZtvjVu8b+at/BrRQpkILb86SvY1cShXXPN8uXTa j2otOHAXUJ/Bnh0U8Yaw9c10FJCcG6zK+6UQRMZ8rYUB70LKKsn5u+QBc MVlvAuQl9h8TrLId+vJ9iRhrdgpSPeqTsALID5G77BMIy6aEroAmRzR1I kO1Vg6TeRiZ7ARMAOFhNr3Dl6aecne46631PCN+7Yvoh+sV1GKd4KFE5s eHNkFBi3mOhI648Y0C+QO4GDHF6OZtSKKoP6OvP27kfIkxIJVhPd09Imc x0TEOuetotOpIJKajOrrVMBDt5nzB2y1puMoexJnzKCvYFqf9oi9AmMH6 Q==; IronPort-SDR: n+5X+WyHYvbDwmzb5oBMwTSgwCq65jM4S7Fi6INfv/LNs54GOkI5mYkng2S1D7ARXbdAxHlXIs mTDcNdVbF9aC1FEEFMmE/X7fBJypVXPCtMt/2/XbslYrMOLH7GZJS70/nSqVfqN0tWf8OGcyw8 yRyDyv5Y39f1Hu7WYLvtIFlhEFH7VMbSlAM6MuDwbqzG9cqAO3YeRNg7KlZhGmaqBPrnQxf8aU /2e+Z8gDpU13w2cGhXqwZxnT2FurlAg4Bu9uKAPfmjvyfTOavsExPskbYV5/1n/6MnEUoKdLrd OVs= X-IronPort-AV: E=Sophos;i="5.81,160,1610380800"; d="scan'208";a="263503258" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Feb 2021 07:32:38 +0800 IronPort-SDR: 6IEWDW9r5ttxR5qtA+dW8LAtGddtdenOCVvAHjHxRJvPZKDdW7A7j+uEhz1sjo9VZtIbFKhTs0 xloJ2YFXejCqJ4jE2XjadeDVL/TvClTBVvvCI4MXaDJdqIk422ZVmdnxgylnUJgfJzk54XTGA5 nQedZ8Wa5N/szZL6CnqIOgTjqoOmr1h9DlEYKZ3zeCxrxLnoF+xN4+P8BXl0O7ZP6FF1rfLciJ JKZ8AyGfp2Y4T+Jc1FrHIfcmHjJBjZuUrHZ6l8W6QBDaaExAeOSrwl9T/RLusXojNkx7rorgzL k5DofumSt/LkpS8r+F/cYme4 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2021 14:57:06 -0800 IronPort-SDR: JmjKgpfXVkCBT+7bdnxfN8x4U3vKRwsyAkchQlhGhVz/Z8agTAvv30lBlgo3rkmiN2tS1J9KNL zmdKIJ7FtY21D89/J4z9cyIQFNxh/NPTXYCytci00BQqK6wNEmYJzIc9/ynWPipIPUVP2Ox1mb flBabxnbS+L3aetkWpjUwx2mhEvMfX2hiHy0y8rKlvq8a0z5ehLBf4JdLYoBGtjCK5/BUo7nt9 1fttqoBUu2YoSIi1BHwVXLEWSEnMtTV+54dgXSUo7WZV4x47zE1+ehtpj9t+SzACpnCjl68Pej R4Y= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:12 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v17 07/16] dt-bindings: fix sifive gpio properties Date: Mon, 8 Feb 2021 08:12:47 +0900 Message-Id: <20210207231256.115130-8-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the interrupts property description and maxItems. Also add the standard ngpios property to describe the number of GPIOs available on the implementation. Also add the "canaan,k210-gpiohs" compatible string to indicate the use of this gpio controller in the Canaan Kendryte K210 SoC. If this compatible string is used, do not define the clocks property as required as the K210 SoC does not have a software controllable clock for the Sifive gpio IP block. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index ab22056f8b44..c2902aac2514 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -16,6 +16,7 @@ properties: - enum: - sifive,fu540-c000-gpio - sifive,fu740-c000-gpio + - canaan,k210-gpiohs - const: sifive,gpio0 reg: @@ -23,9 +24,9 @@ properties: interrupts: description: - interrupt mapping one per GPIO. Maximum 16 GPIOs. + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. minItems: 1 - maxItems: 16 + maxItems: 32 interrupt-controller: true @@ -38,6 +39,14 @@ properties: "#gpio-cells": const: 2 + ngpios: + description: + The number of GPIOs available on the controller implementation. + It is 16 for the SiFive SoCs and 32 for the Canaan K210. + minimum: 1 + maximum: 32 + default: 16 + gpio-controller: true required: @@ -46,10 +55,20 @@ required: - interrupts - interrupt-controller - "#interrupt-cells" - - clocks - "#gpio-cells" - gpio-controller +if: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio +then: + required: + - clocks + additionalProperties: false examples: From patchwork Sun Feb 7 23:12:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 378164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EBB9C433E6 for ; Sun, 7 Feb 2021 23:16:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03BFC64E3A for ; Sun, 7 Feb 2021 23:16:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229537AbhBGXQn (ORCPT ); Sun, 7 Feb 2021 18:16:43 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:1538 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbhBGXQm (ORCPT ); Sun, 7 Feb 2021 18:16:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612739856; x=1644275856; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UhfuvaQnlYYGuJoU1DIlmWqBx9DSZHsBnT1jKP6UghI=; b=rtuEyya/7ba14rjdQW31DlgKW2iD2/Pt8t/9R9SdIIK222cl3NN/X74v IfhI9uY1GNRGRQu2VJKiUEoNX10SDacqJsQpAjsTPj/nJU8Cpi3h7eHZJ Le2No5DNpTKVbNdmG4H7bI+7U1MZIFUYlBzgdTHrbGzgAefqM0dAApTKJ 1BhrK9Aosiyey5U4mbgGun2VLG522d18kk49lgRn0fS/lNEc9hqyqKMt7 tloLfNB/K/9s9+eHO3iWXKKC0/9u6Qjq4SB5e8JRMKBjCXsA7aqNfx/sL lb9ikg0l03efDa6NLjbWpTGcvNd//7EeY3bLVQfq5yA5cSlLALEEpNRL/ g==; IronPort-SDR: fBpU2ZmCqtvhp/44AdX1K5R4ZY38nIJWvbd4ofMO1TgomkUbQCEQ5kkwZN2+HHbbJHi+RKfCz1 mxcHQCe5EYhu/XPuW8hrClCXYmJkoMI8T+n2+5PMV0u+nL8ACKvguXrG6JDMrqrP0Fg+w6aCDd lwivA8KJCZgO0Z350eLJg7R3pnG0AdLIQUW7Gr7musFbotG99uTdXrZBLGil5meqIoMRiSGvPQ R7Z3ZFkJ9GZ5mepQ77a2bJTHZbmQPnTzExoX1UIGNgp6HTQ91uTRTYRcqN28YIDmsey2SFen/C 3zw= X-IronPort-AV: E=Sophos;i="5.81,160,1610380800"; d="scan'208";a="263503264" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Feb 2021 07:32:43 +0800 IronPort-SDR: TiyFaFZthNhUNdUMAr290xyOqht9i0Z0iCm0LZqI1hxWARR5YUFY9V9vWWTP4VJxVl/osIWf8H oYwyDoO+maNu6KmNFrRo15hGMm2gOS14T5v1omKefXZRf5EJ2E0BQn7yZaUWXEIP/+PGVKT82k 4z66bl5kVsh8I7e88Y8oBzdV7zaS/5O4UO55hQp/3im/BSjXGj993bBrAIQevKyNDWngRM/8n9 ZJZdkOBb0O9HtUQ/9eglrtj4pCA4Rj4CB5s6p9qIwe7eEu0eBtWJyUxsT/Wp01hnnXfXH8pLnm 5sM1bDi4Pj0g1Gjl6VZGPmng Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2021 14:57:09 -0800 IronPort-SDR: /y5yfjZDDIlWJnBl1EnDvb3CLzDfqosHK05PG6FagpSMTqNcFFc5V+K0r7kC160FthVUJAdBYx 2cJ+SEs/eqGmW+Jd9njswupPfQ/36rWGadYJZhhd/82ue7mvmvXk1YH3SAl95HIIPjUcXdDDew VRXGTS3yy1/FtioZjaMQhwOeRwhLqLuKyC+08TcwXBjp1nOzDgLURZkyaSTcw6fjUXTJHI9d7E w5aoK4iNuqWSREQE8fCzEfEp2JQNC7f8RsBi3KZ4uKhrwBJlTq8MbTvlRi7VOF8PCWHWRWy8Km SNA= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:16 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v17 09/16] riscv: Update Canaan Kendryte K210 device tree Date: Mon, 8 Feb 2021 08:12:49 +0900 Message-Id: <20210207231256.115130-10-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the Canaan Kendryte K210 base device tree k210.dtsi to define all peripherals of the SoC, their clocks and reset lines. The device tree file k210.dts is renamed to k210_generic.dts and becomes the default value selection of the SOC_CANAAN_K210_DTB_BUILTIN_SOURCE configuration option. No device beside the serial console is defined by this device tree. This makes this generic device tree suitable for use with a builtin initramfs with all known K210 based boards. These changes result in the K210_CLK_ACLK clock ID to be unused and removed from the dt-bindings k210-clk.h header file. Most updates to the k210.dtsi file come from Sean Anderson's work on U-Boot support for the K210. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Anup Patel --- arch/riscv/Kconfig.socs | 2 +- arch/riscv/boot/dts/canaan/k210.dts | 23 - arch/riscv/boot/dts/canaan/k210.dtsi | 493 ++++++++++++++++++-- arch/riscv/boot/dts/canaan/k210_generic.dts | 46 ++ include/dt-bindings/clock/k210-clk.h | 1 - 5 files changed, 512 insertions(+), 53 deletions(-) delete mode 100644 arch/riscv/boot/dts/canaan/k210.dts create mode 100644 arch/riscv/boot/dts/canaan/k210_generic.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6402746c68f3..7efcece8896c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -51,7 +51,7 @@ config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" depends on SOC_CANAAN depends on SOC_CANAAN_K210_DTB_BUILTIN - default "k210" + default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the diff --git a/arch/riscv/boot/dts/canaan/k210.dts b/arch/riscv/boot/dts/canaan/k210.dts deleted file mode 100644 index 0d1f28fce6b2..000000000000 --- a/arch/riscv/boot/dts/canaan/k210.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Western Digital Corporation or its affiliates. - */ - -/dts-v1/; - -#include "k210.dtsi" - -/ { - model = "Kendryte K210 generic"; - compatible = "kendryte,k210"; - - chosen { - bootargs = "earlycon console=ttySIF0"; - stdout-path = "serial0"; - }; -}; - -&uarths0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 354b263195a3..05a12255ed3e 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Sean Anderson + * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include +#include / { /* @@ -12,14 +14,17 @@ / { */ #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210"; + compatible = "canaan,kendryte-k210"; aliases { serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; }; /* - * The K210 has an sv39 MMU following the priviledge specification v1.9. + * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". @@ -30,14 +35,14 @@ cpus { timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <0>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -46,14 +51,14 @@ cpu0_intc: interrupt-controller { }; cpu1: cpu@1 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <1>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -64,10 +69,15 @@ cpu1_intc: interrupt-controller { sram: memory@80000000 { device_type = "memory"; + compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; }; clocks { @@ -81,40 +91,467 @@ in0: oscillator { soc { #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210-soc", "simple-bus"; + compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; - sysctl: sysctl@50440000 { - compatible = "kendryte,k210-sysctl", "simple-mfd"; - reg = <0x50440000 0x1000>; - #clock-cells = <1>; + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; }; - clint0: clint@2000000 { - #interrupt-cells = <1>; - compatible = "riscv,clint0"; + clint0: timer@2000000 { + compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; }; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; - interrupt-controller; - compatible = "kendryte,k210-plic0", "riscv,plic0"; + #address-cells = <0>; + compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>, - <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; riscv,ndev = <65>; - riscv,max-priority = <7>; }; uarths0: serial@38000000 { - compatible = "kendryte,k210-uarths", "sifive,uart0"; + compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; - clocks = <&sysctl K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CPU>; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "canaan,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + }; + + kpu0: kpu@40800000 { + compatible = "canaan,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "canaan,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + #dma-cells = <1>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,priority = <0 1 2 3 4 5>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_APB0>, + <&sysclk K210_CLK_GPIO>; + clock-names = "bus", "db"; + resets = <&sysrst K210_RST_GPIO>; + + gpio1_0: gpio-port@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + ngpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + }; + + uart2: serial@50220000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + }; + + uart3: serial@50230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + }; + + spi2: spi@50240000 { + compatible = "canaan,k210-spi"; + spi-slave; + reg = <0x50240000 0x100>; + #address-cells = <0>; + #size-cells = <0>; + interrupts = <3>; + clocks = <&sysclk K210_CLK_SPI2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + }; + + i2s0: i2s@50250000 { + compatible = "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + }; + + apu0: sound@50250200 { + compatible = "canaan,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + }; + + i2s2: i2s@50270000 { + compatible = "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + }; + + i2c0: i2c@50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C0>; + }; + + i2c1: i2c@50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C1>; + }; + + i2c2: i2c@502a0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C2>; + }; + + fpioa: pinmux@502b0000 { + compatible = "canaan,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + canaan,k210-sysctl-power = <&sysctl 108>; + }; + + sha256: sha256@502c0000 { + compatible = "canaan,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502d0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + }; + + timer1: timer@502e0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + }; + + timer2: timer@502f0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT0>; + }; + + wdt1: watchdog@50410000 { + compatible = "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT1>; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "canaan,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + ranges; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@0 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "canaan,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + canaan,k210-misc-offset = <&sysctl 84>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "canaan,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + clocks = <&sysclk K210_CLK_APB1>; + clock-names = "pclk"; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-clk"; + clocks = <&in0>; + }; + + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <48>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "canaan,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "canaan,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI0>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI1>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI3>; + reset-names = "spi"; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + }; }; }; }; diff --git a/arch/riscv/boot/dts/canaan/k210_generic.dts b/arch/riscv/boot/dts/canaan/k210_generic.dts new file mode 100644 index 000000000000..396c8ca4d24d --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_generic.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte K210 generic"; + compatible = "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pins>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pins: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pins: uarths-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h index a48176ad3c23..b2de702cbf75 100644 --- a/include/dt-bindings/clock/k210-clk.h +++ b/include/dt-bindings/clock/k210-clk.h @@ -9,7 +9,6 @@ /* * Kendryte K210 SoC clock identifiers (arbitrary values). */ -#define K210_CLK_ACLK 0 #define K210_CLK_CPU 0 #define K210_CLK_SRAM0 1 #define K210_CLK_SRAM1 2 From patchwork Sun Feb 7 23:12:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 378163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FDEFC433E0 for ; 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07 Feb 2021 14:57:12 -0800 IronPort-SDR: WVcNOXHMYbLbNfnuAC9m0WH//6poCTDgI81cHE5uW0377OO9IQl4Q5vx2qxTcBMDFVj5uRK2GG Gkc9k63Ucesi1Ow61RmFC1X1I8c5xmXk+q73S3U5aN5FpswyxNjTOzM12+3Vhub94zPdgsY7FI 9sXfYvPRAtamBTcz2oXSoVpqWMZKXR2mE0BAvTlM1LdvUjYhKDwPR07TGTNYuh0ymPJdnZ98eL QRPyt4xkJ6tYibE0oMv7NhE9DRPBwwkhWt/vtx17Msw7YsJWy49w7VUCP8XPRgjakJ5XKdezqb crc= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:19 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v17 11/16] riscv: Add SiPeed MAIX DOCK board device tree Date: Mon, 8 Feb 2021 08:12:51 +0900 Message-Id: <20210207231256.115130-12-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maix_dock.dts for the SiPeed MAIX DOCK m1 and m1w boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Anup Patel --- .../boot/dts/canaan/sipeed_maix_dock.dts | 236 ++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts new file mode 100644 index 000000000000..fae0149a8740 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include +#include + +/ { + model = "SiPeed MAIX Dock"; + compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w", + "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + /* + * Note: the board wiring drawing documents green on + * gpio #4, red on gpio #5 and blue on gpio #6. However, + * the board is actually wired differently as defined here. + */ + led0 { + color = ; + label = "blue"; + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + label = "green"; + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + led2 { + color = ; + label = "red"; + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Sun Feb 7 23:12:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 378162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C5F8C433E0 for ; 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07 Feb 2021 14:57:15 -0800 IronPort-SDR: DPLcY7FvIHPsdt65cNd8yR7yqnNW1DDS86PqNwWcvQmydiAC0lF1VbA9zrb5UAd+0TjCWuOA7k z6+mwM7+ju9lMGEgteCWvZAclMXyklG3KYb3sPWJGu2gtxTkl0JdRuxWZjRjqoK03xGVSL5Ju1 16ldBA6u10ea/d+V8NES8XUFt7l3H+7/xDoo8DgQ1k7RXK18lLQ3Trn/z+LtROPM+kyRZzR315 MBUdj+XEe7wCguX+WdYtGM82/ZhRxYQ4HRPS7bMMeSgxOFn89ViSwW0y6/0/WPKgYL1+/Eym9x uFQ= WDCIronportException: Internal Received: from phd004806.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.69]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Feb 2021 15:13:22 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v17 13/16] riscv: Add SiPeed MAIXDUINO board device tree Date: Mon, 8 Feb 2021 08:12:53 +0900 Message-Id: <20210207231256.115130-14-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210207231256.115130-1-damien.lemoal@wdc.com> References: <20210207231256.115130-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maixduino.dts for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Anup Patel --- .../boot/dts/canaan/sipeed_maixduino.dts | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maixduino.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts new file mode 100644 index 000000000000..804edc45eeeb --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; + + vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&fpioa { + status = "okay"; + + uarths_pinctrl: uarths-pinmux { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , /* BOOT */ + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + ; /* Header "13" */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + i2s1_pinctrl: i2s1-pinmux { + pinmux = , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + power-supply = <&vcc_3v3>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +};