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[209.132.180.67]) by mx.google.com with ESMTP id u2si1559777pfd.201.2018.03.13.23.37.05; Tue, 13 Mar 2018 23:37:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753432AbeCNGhE (ORCPT + 6 others); Wed, 14 Mar 2018 02:37:04 -0400 Received: from mx.socionext.com ([202.248.49.38]:51863 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753350AbeCNGhE (ORCPT ); Wed, 14 Mar 2018 02:37:04 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 14 Mar 2018 15:37:02 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 23DB06006F; Wed, 14 Mar 2018 15:37:03 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 14 Mar 2018 15:38:02 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 05C154037B; Wed, 14 Mar 2018 15:37:03 +0900 (JST) Received: from aegis.e01.socionext.com (unknown [10.213.134.210]) by yuzu.css.socionext.com (Postfix) with ESMTP id D2C40120534; Wed, 14 Mar 2018 15:37:02 +0900 (JST) From: Katsuhiro Suzuki To: linux-arm-kernel@lists.infradead.org, Masahiro Yamada , devicetree@vger.kernel.org Cc: Masami Hiramatsu , Jassi Brar , linux-kernel@vger.kernel.org, Katsuhiro Suzuki Subject: [PATCH] arm64: dts: uniphier: divide I2S and S/PDIF audio out pin-mux group Date: Wed, 14 Mar 2018 15:37:00 +0900 Message-Id: <20180314063700.13365-1-suzuki.katsuhiro@socionext.com> X-Mailer: git-send-email 2.16.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch divides large pin-mux group 'aio' of UniPhier LD11/LD20 audio system as following: aout1 : 8ch I2S output: AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2] aoutiec1: S/PDIF output : AO1IEC, AO1ARC Signed-off-by: Katsuhiro Suzuki --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 5 +++-- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 9 +++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) -- 2.16.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index c17b77091129..e64b03fc0cae 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -192,7 +192,8 @@ reg = <0x56000000 0x80000>; interrupts = <0 144 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout>; + pinctrl-0 = <&pinctrl_aout1>, + <&pinctrl_aoutiec1>; clock-names = "aio"; clocks = <&sys_clk 40>; reset-names = "aio"; @@ -578,7 +579,7 @@ #include "uniphier-pinctrl.dtsi" -&pinctrl_aout { +&pinctrl_aoutiec1 { drive-strength = <4>; /* default: 4mA */ ao1arc { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index c85e790fd00d..9a5df24059a2 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -292,7 +292,8 @@ reg = <0x56000000 0x80000>; interrupts = <0 144 4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout>; + pinctrl-0 = <&pinctrl_aout1>, + <&pinctrl_aoutiec1>; clock-names = "aio"; clocks = <&sys_clk 40>; reset-names = "aio"; @@ -633,13 +634,17 @@ #include "uniphier-pinctrl.dtsi" -&pinctrl_aout { +&pinctrl_aout1 { drive-strength = <4>; /* default: 3.5mA */ ao1dacck { pins = "AO1DACCK"; drive-strength = <5>; /* 5mA */ }; +}; + +&pinctrl_aoutiec1 { + drive-strength = <4>; /* default: 3.5mA */ ao1arc { pins = "AO1ARC";