From patchwork Fri Feb 5 06:58:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32193C433DB for ; Fri, 5 Feb 2021 07:00:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D874864F3B for ; Fri, 5 Feb 2021 07:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231339AbhBEG7p (ORCPT ); Fri, 5 Feb 2021 01:59:45 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41743 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231328AbhBEG7o (ORCPT ); Fri, 5 Feb 2021 01:59:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509481; x=1644045481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U5RPnx9naL44L8pODbHMwPFT+udQFeaq9RcnNssxEXo=; b=i7Q7NwxSaPgEUoGCCmU0+05YZonWBWK8fDWN0NzL38wPOAySwql/LX3Y sC5aMS0KPXe986JzAhglgh3dBtq+Qp8brwqVYNRphRRgd4WmbCj/aJDPW LZcUhuWWkAlhLvMhqtiK8HZH4UT9SYlYMpzOVGpPsyVw6ukfQdiSGqkch eFCzkjs47gaeQ9pfXkcD1KGGB/ypEuSoYzbu6s8pniiI3NA1wO7uBivNA B63WmxRjbg3t7RZjgL1EvezpeyYvGjdufGYJxxQ15+M0ZWAuQH3kA0Zrw DLc/fZG35Yy4GvHUC1ZVHfhV42kjTaalx1paDBbyasxrxw/pvytZNCRh/ A==; IronPort-SDR: RwPPhpsS2+cDP5zzsb0TP8ey1AsEbGwpH0c+8+bEwgeixU6Ekh0UL/oiSkTaKDdef7cvSN1hUV O2V3zYoQdrq6RMsf6ea4hb259UA/SqpjhKp6fgSVz//v3Ax1J0dVEiKIP0v9rLDxuwRnd8ehWB kI2/m2adht2QNdkWwaBoLaIjTQO3DOOutZwQLVGj/hbzorD/xR3yvF+KajmwGcNMXcU3UNZ9GI E5AOB1HnsoNuGlN9ppDtdJXhBjkkRO+A0TRMAOHENp3792B7q5rWj4NwXFd/5D01Hs6hKhT+YG LFk= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312040" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:20 +0800 IronPort-SDR: JiMeNKZ0rsALvi6hwfwVjDs4r3SogumUaSEiUNw/9xAaRy8q0zmlFNaZs8FTAZevG16tJ1KkCB sVgvMYRQCWHzynmUNI2yuIXrIY9fYzUjC2K9GwgkyWOqzH8QbAe+lDrCDRE9EBbfZVA3lAK2Bi BXaGc73BUdV1F5HwEV6VvdEpqBxlfc1mpynIlhJr2rT7s8wyK2rieO6shlPNmDOz/Qxp6PKglV dGTLh3WY7qh2k2k1KEWAgBghHQNi345lXTYMkWdtgQYgiwNSANtwk/8nNPwfCO7v285uju0t+/ i5cIKrbRv97Dnw5TitutR9U9 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:39 -0800 IronPort-SDR: YIiF6BDlSAeIMG4U+C7LrTDsAsNhjRYGcoiIbpcdLEPEH+gclLXLKOLWSrjGnfYt47uFLDauJh 7qyzW1u1hJ0yT4Sq8JzZpz7Tagq7Ref3AzT6vT4P7ARLW4iL+kc2wfdeOhfX8Ojc6G4VNqpgtA L+lxDUgLx5FcC/EZcAWU5iZ6hWgPoL4PWunjR33hQJfz4ELb0ew4JYuuEk6qt7nKc2ed7Z4MEI J1ZwUjV2mkLxYUBWK+OP6uJSOjZtyGgXoB+MG9ZqLxYAxSXwZL4MNki8NPeZyultNsUvXcFTwD iaw= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:36 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 02/16] dt-bindings: add Canaan boards compatible strings Date: Fri, 5 Feb 2021 15:58:13 +0900 Message-Id: <20210205065827.577285-3-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce the file riscv/canaan.yaml to document compatible strings related to the Canaan Kendryte K210 SoC. The compatible string "canaan,kendryte-k210" used to indicate the use of this SoC to the early SoC init code is added. This new file also defines the compatible strings of all supported boards based on this SoC. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Reviewed-by: Rob Herring --- .../devicetree/bindings/riscv/canaan.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/canaan.yaml diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml new file mode 100644 index 000000000000..f8f3f286bd55 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/canaan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan SoC-based boards + +maintainers: + - Damien Le Moal + +description: + Canaan Kendryte K210 SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: sipeed,maix-bit + - const: sipeed,maix-bitm + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-go + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maix-dock-m1 + - const: sipeed,maix-dock-m1w + - const: canaan,kendryte-k210 + + - items: + - const: sipeed,maixduino + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-kd233 + - const: canaan,kendryte-k210 + + - items: + - const: canaan,kendryte-k210 + +additionalProperties: true + +... From patchwork Fri Feb 5 06:58:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46103C433E0 for ; Fri, 5 Feb 2021 07:00:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0639064F9D for ; Fri, 5 Feb 2021 07:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbhBEG7s (ORCPT ); Fri, 5 Feb 2021 01:59:48 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41747 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbhBEG7p (ORCPT ); Fri, 5 Feb 2021 01:59:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509482; x=1644045482; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Psza/nTy12u4z4eFovqg8PCnJ6Lt4zZtRvlW1Nk85qs=; b=ZqfAZQ2Cq4qJr0Tig3Tzf5dYDnyvkv0drOARj7t1h7/O7CqGA+hP++sm +EdMAGQkfkGkplew3e9EhZeot1/rRecTBSlYcKuBKxpquwHikpzFDHWxT zgwETkOc05nC45EMAbYhiwj+XZDQNqCqzOlEXnNkNlOcEt9qOqnyTmmN9 7zReUDRMq1ladDJgCSwboKJFCyIW6vOmKk3PKDwwv/NK0aFNQPhDanZqi kvrJrAY4bGRDtZ+Tm4e4Q7TWKXqQJ+CVM6/3nqQ4Yj4PEBS3TbGQqXjy7 zCotsJCdDxO4gYvBdkwKdAWPEIHdhHjo7j9K0bUPesvdOkSk6w/XLcjBM g==; IronPort-SDR: Of8xLOjVPnq/K/mxtVZF31FVsLPusGaMryElzvD6CHODXwd7QoSMFodjKdHmGB3RjCTfBRUtgj lG7tIJ8qJuNUvvz/t1HeZMzt0E7fGZiBZ1Cms0iSGvXeEQg1P9X56RnJEfkmundvFiZyiOzHvx Ev5saFAD82/kigg72piVHRGcvpL81oRXQxp/jRbtpUO/pEd5c913EhatxBo2GyQY3Pf2UVwztF 4InFp38LYE5gcfekHmvNf4Aed3apEytjqMuxvD4WfM7QGpBp/TdMPUOyhtgfnatgxssfCQd5PE egE= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312044" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:23 +0800 IronPort-SDR: qrl17j/KK2lRYEQjH9CBVbMihjangAipf//2qVoSBrvwTt8pU0OOPnA6oyXmf1P7Iboq8IEpWk TmXlTcTvxMXIoUFhDmaluPnVk+CcElykxNCylzfCm/hpu/8agKWydjJSNZQ/t1HCnrxeocxbx/ 34KiterWdzdp9ZZd1LG9W+KpD+Drpd6/L1y7MwlProOhHFSMNJBwUB3Fpx2YuKrdd5ZOT7BE4n +YfQr5mmu7WNxIuNKoEhyrWTpilXr/h791jQxbAFut04VEfLcfjogxoaXSN86/gqczQZsUX3lq iFioCdalrBmE557k86IzW5Kh Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:41 -0800 IronPort-SDR: 4UQThxBkXkhPrN7IK9i+5fbRZ1hgfICpWMDU8lbTR4LtD8JNjkR97Xf2hAG11glW/2tlNj5/FA lkSw5GIuPTbBIF+576TQtbZ6YJbzlLSBWeb8VBFhWFUQJGOTelk7v+zbLjU92vZFJwLavbSkUM C5MlbHf3OgdX7PKpvm731Z9U0XdYdMQosik9Ffso0xI4e6wZ+Ua56e5+eaBDsXcQG8b90LcH1x 4S9+iA+n2NHfz6h2ogxJvyyH7veYMODYrWxtHDGbMGq7uFEosx7nCNYsO1EnKSOJEKrZy0T61X x+w= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:37 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 03/16] dt-bindings: update risc-v cpu properties Date: Fri, 5 Feb 2021 15:58:14 +0900 Message-Id: <20210205065827.577285-4-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Reviewed-by: Anup Patel Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: From patchwork Fri Feb 5 06:58:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87D39C433DB for ; Fri, 5 Feb 2021 07:00:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D55864F9D for ; Fri, 5 Feb 2021 07:00:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231293AbhBEHAd (ORCPT ); Fri, 5 Feb 2021 02:00:33 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41743 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231284AbhBEHAZ (ORCPT ); Fri, 5 Feb 2021 02:00:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509544; x=1644045544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eotfzN0WvUvzgiZvKqxmdTfBb2NiGvb8zj9iv/Vd+cE=; b=GnzHOQaZGM2fFzgjslQtBl7nCKv/gW/9qBKtUkxUT/EoiGYxyKX1AFTN MOrWoH4P6dArlfxmD6vIvv56MjhNQRyW8tkYBoUNTCWaoxMWXfgMdD/3v I2Jbrf2gsYbneBxIKUifhoE3K/HsDyFN6c2/2t3JHHpv8WNmJkEJNsztt u8iN5CARhjsTeo5AGSldQIsYjpoSZKk8Y9og3UKkCT6ndWgaMpbHP0uhJ Qd7/cNq140zLmMUNOnKpcGNgHPnGJhXtpZW3eyJVudJiLLCccNhYTIEHa Tda187HNE3+/HvAenMcEMgnVGEwrkZQ7L0HdYxt2GHHBOaVepG1AJu9MW g==; IronPort-SDR: VhoTrZUH/cB5Vja4nBZp4lF7WY3UE4QncPWGe3Sf2NTCMNj+UWF6Ht49WwaRZ3XEjvMktHVVVO z6Z/Jh3B8QupEotpYqteSo09TYnFIXqytwDjbPvgZAn8vq+Xl9YKC2GwhOjef9mXk0e2/QdOmb e7JJQ7Nx6fNt2VwKC1lYaInLs+QNF+4cKaxSAzgUvEPKRFpVzCyPWvpGxnIzlUS0/49FqcEBWK AA5xDnBxel1lCnqYvg0EIu2G4E43K5g+FWzl6Mzy9VFae7Hmbba7lnhF1HBfN9bEuqNI1BslqF G6A= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312049" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:26 +0800 IronPort-SDR: ERnvEL5xi2EEC2x0YSS4Lmj+yCjUKsyYXx5TtcWti/HlksGGgFkkpVgzFS5/8gZv+9aHc5e0aj R1lwwID4wBfqVDBHeBM8hXxJrVpYxZGu3R6VobQX/xo16tr5K+PCq76vU2QhAZLk8LM2L6T+09 arIbSyJJElHWHRFvQ4Uok/QNygCSdG27+MPKuJF3fPC7/xJFwBeSknZDRgbvN5qjNiU+5AbSLd IsXMxjbhi1lF3Gp8QTKj2g/KL8qAjeF3EHwSCFzXZhkyBcqEaBihnuZVVOJWjIC3WgonCSzkmM xHnKkYTpWs2C0Zkl3fczdW3o Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:43 -0800 IronPort-SDR: iJ+L7v+b7LFPg0PEyuN4SUktS3jBZZhei5E+pgDp2ioB3BVLigE9WyJXbZOD6E6N6MHfapDQMh 0mxnrZxzGpHUQHVTJLPz1X4Xcws1JBWnf5pOCaKwO7pUusjJx0ZoGj46R7V39Z9PTp7yuVMKf7 T43x2YaDTPfWw+sHME4jo0s47pajivgnn+AZrM6ou/a7pt2EHJ3AWwj0Nf3yDCMR54q5o5uZ9f eUBE7nMqH6dRbqMlSZYZZbFipILcO772b3ETozLnnKk4C5+FC7wtDFPLGnGABJX8acsg3WpPqL 5xk= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:39 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 04/16] dt-bindings: update sifive plic compatible string Date: Fri, 5 Feb 2021 15:58:15 +0900 Message-Id: <20210205065827.577285-5-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible string "canaan,k210-plic" to the Sifive plic bindings to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan Kendryte K210 SoC. The description is also updated to reflect this change, that is, that SoCs from other vendors may also use this plic implementation. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../interrupt-controller/sifive,plic-1.0.0.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index b9a61c9f7530..08d5a57ce00f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SiFive Platform-Level Interrupt Controller (PLIC) description: - SiFive SOCs include an implementation of the Platform-Level Interrupt Controller - (PLIC) high-level specification in the RISC-V Privileged Architecture - specification. The PLIC connects all external interrupts in the system to all - hart contexts in the system, via the external interrupt source in each hart. + SiFive SoCs and other RISC-V SoCs include an implementation of the + Platform-Level Interrupt Controller (PLIC) high-level specification in + the RISC-V Privileged Architecture specification. The PLIC connects all + external interrupts in the system to all hart contexts in the system, via + the external interrupt source in each hart. A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two @@ -42,7 +43,9 @@ maintainers: properties: compatible: items: - - const: sifive,fu540-c000-plic + - enum: + - sifive,fu540-c000-plic + - canaan,k210-plic - const: sifive,plic-1.0.0 reg: From patchwork Fri Feb 5 06:58:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDD2CC433E6 for ; Fri, 5 Feb 2021 07:00:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 783DA64F3B for ; Fri, 5 Feb 2021 07:00:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231284AbhBEHAd (ORCPT ); Fri, 5 Feb 2021 02:00:33 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41747 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230482AbhBEHA1 (ORCPT ); Fri, 5 Feb 2021 02:00:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509546; x=1644045546; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=imuithzWrTjkRyQr5q8L7wvXZ0KquIdBdqaL9xNxgNE=; b=qNdZQPgLH+MU0Thuif7dyhsd5v0YhNv+jGiNlvr3Aspli0X0AVSbg/9n v7hlQOUCCHJwG9m3xeH+C6U8nMpui3I9rweL17ZtGcks36MU991+OwYXJ t3rOkv10IpA/ugNzQr1i9maH7R5u3dHIsxx+aVN25IplxJ1+R1768+6Vp JPKps+sWBdCgLHMdoPT9PgJ1HKK40lBEXE4v6mfcWHmjtHzYTEjmG7E4k DXSbJq1EmWdLX6MtElkWHnON9x1LbKN9ttI+0xoCqWLj3apXVElgy54EF yc9pC/7QNbCGLCLq4V36802lselR90s9BALfCFkTip+erNcV6LE3W0JJ6 g==; IronPort-SDR: E+TSq3oJnGe+zVYSSDCfUue011LPFdInlmul/Q/i8/zEqnR1A2NhHJ/9FMn5H85ZT9nUuMzHVf tu/jJRY1bE3GPs0Wy6dXabXMCvmTazcSrmzMykLAYvyEpadFBQXAzlPfThIGt23cQxc11jOlfh Rvxov0RkYJwQcP8HYUS7ClVjaVax1u0adqe9r/aB8GxKDT8I9BNX4oWNW2zDbDLGXSyeTEpjs4 gHy7eD2RTFpnOasd1rNCZOm0+zIUmeVsmjW9iDQR897bXFBc0agP+dT598qFF82n2CdNZTCVzZ uaQ= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312052" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:28 +0800 IronPort-SDR: vG8MWcU+zE/YIt+wloL6MApgybd+3iDGBLWp49Cyx+uN3CNVbJUqMiPrvgAFxp5t34EZ0SOcxp FxtBszbYEa0nH1ZmjG3syzTV9TfqJEXVk4Ch8wz6s/9+6N7leax+d7DVbY3++D5L97Lw2SHQhH lEbo1GPjUNmvBTuPnoH9H2XS1FLKMxXKhkqFN0sBuKeFR3VfOlDGmNYeTGLLouOy480tdmt+Kw 0L3jg+iZ6c62LFHERpKuK50ZdzKk76zZhD87m3lJrxUsh0MTrvlaBaip9caRnlHzliKM6dyYCx mfKZFUguC7wUzwkuR//8dD7T Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:45 -0800 IronPort-SDR: Tat3o1D+8NTnysAH4mEzdLZmm1E8pUTJaWA/jM+PjrGV7w8+z7NX3KMocs4nNRacKJrhK4zxUs Fv1H6T7YLLe1/3r++Ez4VZIgY0LRvm94Mh+xpbhB0CeFLBhUhgFZ/1Rowp5SdDNlz21RpHWgNI P7yjJUiXqKp0fpTDPCqQymuPX2c0/qQGEN8p1AhD3EN1XRaBLUmM/EnWEpeGXNNOAWegCvt3bF LKkYXqjwib+w6KnS/FXDrwCFwxMw4r9bVmhH4JNFJjg1vsiEU/uJcbz/0TOlwBj5XGQoS3zE+Q ElE= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:41 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 05/16] dt-bindings: update sifive clint compatible string Date: Fri, 5 Feb 2021 15:58:16 +0900 Message-Id: <20210205065827.577285-6-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the "canaan,k210-clint" compatible string to the Sifive clint bindings to indicate the use of the "sifive,clint0" IP block in the Canaan Kendryte K210 SoC. The description of the compatible string property is also updated to reflect this addition. Cc: Anup Patel Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/timer/sifive,clint.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 2a0e9cd9fbcf..a35952f48742 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -23,15 +23,19 @@ description: properties: compatible: items: - - const: sifive,fu540-c000-clint + - enum: + - sifive,fu540-c000-clint + - canaan,k210-clint - const: sifive,clint0 description: - Should be "sifive,-clint" and "sifive,clint". + Should be ",-clint" and "sifive,clint". Supported compatible strings are - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated - onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive - CLINT v0 IP block with no chip integration tweaks. + onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and + "sifive,clint0" for the SiFive CLINT v0 IP block with no chip + integration tweaks. Please refer to sifive-blocks-ip-versioning.txt for details reg: From patchwork Fri Feb 5 06:58:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A088AC433E9 for ; Fri, 5 Feb 2021 07:00:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66D1364FBF for ; Fri, 5 Feb 2021 07:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230482AbhBEHAe (ORCPT ); Fri, 5 Feb 2021 02:00:34 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41738 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbhBEHA2 (ORCPT ); Fri, 5 Feb 2021 02:00:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509548; x=1644045548; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AIY+mENCG0OfDogqN2TK/zkNool8y2CBwzDhCDvMBTc=; b=qBh54gNxeudSj75nP5vbqV432hQgzQ/qtYVA6J+9L1/66J0/CwQCcmoJ mg+eYXLwI7S9jpeBS/Czwgx9mL8HpNDDznO2bYkVS4lwccMcNvPEnTCAY LKekTYbSLGq1k/tXUZ8LXbast4dIiwcwqB/9Dm+pgoS6uHKoExThHHwTD 9lbhZuqdyQry32cZ30249A34j5AWE3/+ZCQFftM2Le6ZnypgfpJUjBjTV /n8crbuPr9Q9brzNEIRDb3J/8BcChlbuzSKK5ms19+o8fDSkkbyHrm1H3 FSWDb5YQEnGbngWYU/EGEu/m6LPegfx9JW8tlxyb3BjXVOjG3LCSYTCOS Q==; IronPort-SDR: Br3/TkXhsWS9jmV4luGcpe2yN26Hzfx39cO49cey8dieG8o92TOGrp81m9PAp13wrpz/rIbr0/ QOPfJXPL9lgw+Z/ySVH3QiKyG0fSTT8WpfN+t9ct76D+zwmwbk4I9psuuSaRo/+Qz0k/rJ+RPz S9ozuEz/OromFcDJVOrf2w1NAvefSUGNu3zORDj3Eo2OcysegZsUuIyTTiD9d8MZjK4F6HihMg kz7maDXyI1ywmhqHEcpPlegseyLJN9SGExF9PulAlGk7G8yHCP0PrHIhAyxkW6aiRVYOhD/tHI WZs= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312057" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:31 +0800 IronPort-SDR: wxHUXl2YhSxv3y3BDwTsikBp2/bLAkzUa2m1c2e7uNN6Oe9Ho1bkf+qRPJaPzA14YMXpxB1oYU RNnphjkENOwmCR0V0/DccE37T1pGwOGqGKSSKaPRtmZZQgr+1PXgs72hnsd88xoz0lN2SrtXYs 8+fz7D1dmOfqToh//J0bOxO8y2xpqvaNYlfK1AxoMZeBUwYg9IQpZ1C8xMk4zMOaydC+7jkmJm cEyUZ1OPt7dw1kSwK1F9Mq5tFi+RbE9QhLDSjM5k+m/rUqEAvcQFnBGRKSCPT/sPKDdxEQ5pI4 FGzRiHfCzds2CqBy23tVLCdf Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:46 -0800 IronPort-SDR: tOK9QR/uLe5qNKojkvaVog4neH3PH42jqSB/wQbbd3JFDU/aZibN9daVNXEpJ6eH4dh/EQtNhz szPpe0Qs74J25K/8tGvvIQ0aBBtyCF/pyR3q9ryeUzTTipo8Zz/js4aobQXqO9kNTXcGAS6R+v gGQdZmbKzBv+Cmlk8cz/9G/DyJTFuACEZgv2oJzIo0VtAiNDKnKhPwAU6e6GjH7iWJXXChtoL/ IR9MhpwmBR5720OFQm9ELeAAw285g3lnL+lXYlzk0Qoff4Ii5ywkc3S4g1G0urwzFOvoQX/he0 SAQ= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:43 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 06/16] dt-bindings: update sifive uart compatible string Date: Fri, 5 Feb 2021 15:58:17 +0900 Message-Id: <20210205065827.577285-7-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible string "canaan,k210-uarths" to the sifive uart bindings to indicate the use of this IP block in the Canaan Kendryte K210 SoC. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Acked-by: Rob Herring --- Documentation/devicetree/bindings/serial/sifive-serial.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index 3ac5c7ff2758..5fa94dacbba9 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -20,6 +20,7 @@ properties: - enum: - sifive,fu540-c000-uart - sifive,fu740-c000-uart + - canaan,k210-uarths - const: sifive,uart0 description: From patchwork Fri Feb 5 06:58:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D06FC433DB for ; Fri, 5 Feb 2021 07:01:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EECA064F9D for ; Fri, 5 Feb 2021 07:01:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231221AbhBEHBN (ORCPT ); Fri, 5 Feb 2021 02:01:13 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41743 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230487AbhBEHBL (ORCPT ); Fri, 5 Feb 2021 02:01:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509613; x=1644045613; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GP6wzDUcVmwthNo1PAaSmaRGlhfBY1ttEBVnMlWwZlc=; b=VQ7HlJscJ8lHjEvuAN6NT97KKqXwG/11N7rQbCTn5htQHGLL9SIm3q5e fHeRMn4PXjUyJze22uE2n1VWF+d7WaCA3jGwGts0QB5NpockWl/BvJdCK mTrWhvHhSnMRTG8gCnu2YKVN9VH/SvfHRaAAoSqaedpaJy8iqOqIdrLvq vVvqDknc0g5NN5jjEj5fwxHYpwIrtPmOzXEh5nAXPhVLMXFrI/EZcu72N vUJp0drIOpJytPcJ2FFMfPtJE+gBy83D59n0M2iypKb/FvDwh72gC2nmx xyUoLjdGPS5WKZvPkMNpME2b8wv6EFhtXcllbTv/gxdVSPRjyYqORAZE9 g==; IronPort-SDR: iMe7Bu35AiQLOZENJ4Eduw/F1YHYGiuz3IU7oxscUSfvB47+vNQZQKvJ7zmWSkFdE62U+RJ5R0 Aa8pNheOeQq181WnArvpdN0qSDjRPhrb7U9vXDK3K4lCUPSbEcdt/UC4Mye467mGoeSqBIGbFs CRkCWf4odzWPE1cdkUFjDU+pjCL039iW6Te71BPN4Xp1HczfDxqKJ9LAe0WP9G/0YslX6iUOM2 Lf124y5MUVeicsHNgjmbBsZrGKnj4atF3OEj0n1+nEfzM4S5N1HbvjKoMHXU8Ed+AANqopQnIa b3o= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312064" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:34 +0800 IronPort-SDR: O3uWiyZOQ1bMbkzggJkXXXuNrwBHJI81OApCT92zjWg4Ov5Yb4zny3vCIbRao6tzKSzkUmaomL z53FzJ5ny2Qb/M2R8GfX7m+7xr9VoRHbH1SJyVCmIU4JhxdqZPU7JjstfI+sOMYAXQ3+beJzc0 sLIa7FvdOmhQZQI3O0PueaJHjKAkhI5Uj9qbe92l7qaTHbp0dcp/RT0D47MA3COf8BUrVIPXzF FU8eAGOh4lsXTG/rWJIv+NLfKmG9tJrtZJgg6rJafYjn7YRWJKgSc/yNdeXSK9ggkhn500jGmX iAnbQhzz0EgipOO6HTbH7f/y Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:48 -0800 IronPort-SDR: CZ3zXB/kwdIQ+ZsKpZiCNeEOv7/KjRBRO0VtWZGllYILElv9jeTefuRnBlhzCUHf9W+KIa1scy yQ2O/larN2zHzSGvS61G+/WpiBU54Wvq4mnSVpsX9LUcD3KZ309iUt+Bqt+Vfko8q9pNeRtHSr f8PbCPCeu7Op9+AU+M7kAkQijZLgowyMfrzmcoYhcFTi5+u/Ir5LEbvQe/6tQPwKoJr+NDGcoY vZ7r4d62P/hhy0Ou6H6UVarcMWoqbqgQZgIH9NLpbAet6M7FiA59mlM9GLH2SIcamMT9dZp+Da T00= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:44 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 07/16] dt-bindings: fix sifive gpio properties Date: Fri, 5 Feb 2021 15:58:18 +0900 Message-Id: <20210205065827.577285-8-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sifive gpio IP block supports up to 32 GPIOs. Reflect that in the interrupts property description and maxItems. Also add the standard ngpios property to describe the number of GPIOs available on the implementation. Also add the "canaan,k210-gpiohs" compatible string to indicate the use of this gpio controller in the Canaan Kendryte K210 SoC. If this compatible string is used, do not define the clocks property as required as the K210 SoC does not have a software controllable clock for the Sifive gpio IP block. Cc: Paul Walmsley Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml index ab22056f8b44..211869d30212 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -16,6 +16,7 @@ properties: - enum: - sifive,fu540-c000-gpio - sifive,fu740-c000-gpio + - canaan,k210-gpiohs - const: sifive,gpio0 reg: @@ -23,9 +24,9 @@ properties: interrupts: description: - interrupt mapping one per GPIO. Maximum 16 GPIOs. + interrupt mapping one per GPIO. Maximum 32 GPIOs. minItems: 1 - maxItems: 16 + maxItems: 32 interrupt-controller: true @@ -38,6 +39,11 @@ properties: "#gpio-cells": const: 2 + ngpios: + description: + The number of GPIO pins available for the controller implementation. + It is 16 for the SiFive SoCs and 32 for the Canaan K210 SoC. + gpio-controller: true required: @@ -46,10 +52,20 @@ required: - interrupts - interrupt-controller - "#interrupt-cells" - - clocks - "#gpio-cells" - gpio-controller +if: + properties: + compatible: + contains: + enum: + - sifive,fu540-c000-gpio + - sifive,fu740-c000-gpio +then: + required: + - clocks + additionalProperties: false examples: From patchwork Fri Feb 5 06:58:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B181C433E6 for ; Fri, 5 Feb 2021 07:01:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EE2464DE9 for ; Fri, 5 Feb 2021 07:01:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230487AbhBEHBO (ORCPT ); Fri, 5 Feb 2021 02:01:14 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41747 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231264AbhBEHBO (ORCPT ); Fri, 5 Feb 2021 02:01:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509616; x=1644045616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CdDSnYoUg4x8z9E5kd8zeW/UQhTCXdRY19IDHVs+Ulg=; b=oUwesLtrJ1uvjC4jHfj7JKcbsccVdAQRT0yABZLmG2x2/aun+xIIqcqk 6pRd+ECIxLNHwvDrjwH2D6gnnCX1AwS5EWYW/2KMehZ9UGCxX4jvlskg5 NK8/B1yu/X9KOBrFWvRMjRVfGRNJokqIKoNCclxT7G4U3QlM6LDph2F0e I1bc3vm8TI4olxivbwE/X3tb7+xwKN49BpDDSEJfSJDp3bxF13KTMcbrl JZmS1KBeEOTOumPkJy+TbBhCSxpHQDp69GhExgrA9ZuS2juKFcC1GbXck eEg+xbGMmFGaDUMIHq+bKUMBnR1oBWokv66BwuUlfdpDg9+H+b7h3RHzU g==; IronPort-SDR: c1ASP5fwetKvu+M7Q+ZzbzOnjYKYrDDv06LHS9SyBLGErlUZsyvRFaJno+hOfWeiTdSEVlPIrA LdcoLFiVqGb7wcyJHtKQH/K8DDlo5yMlKshLYjBW4XlC3iXPvM3+3ysEmRCiFgFpyR8PRLJltt OmQ9jnnd/eWFJfJgHRwvHaRsNxNyo9EtC0Tu6wfwhvYp+FpCpLRF6rOQfImBOPMSxB7KGV8Rh4 8kJSsEgiDCw134WKIuS6BoZY+sdhA84hculdfNocCX88WvNQZzZjJERtnsQCpyloE0ogjmCALB JKc= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312072" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:37 +0800 IronPort-SDR: IScSfWeELpiiOhN6fox9jVyMjilneiZy7VT9m2yHL+lUBEWE/88l356IKYuWQeHj6UvDEuPXFp ABsBQ1T4Vq7TjYrfb1DBD2kGsuomrKg+HsbzdIwl+UhVjHb1kHA8BX8YbZnrRn80PI7lSduaUi YJSXQ7tDPMc6lz5TPa+3XO0KnuqInWaDRAHAn3Gno9ABjFSV2lYuIhZ5NvWbbhiushs9PE87qO 417N3hL9XcLwZf6FjJqFrM9J/RZear0sJHh5fKYej9ywQuog5ji/v1OWdwRQPf+s3sZF6kaeUF O1bkU2dbQkqeREOBthxBpk8l Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:50 -0800 IronPort-SDR: LJ4ijRoBawtS+Y/PSYZ+xUZRiROjnv9E/NRd25l/i7x2l1aXhvbcix09p9wjI2aESp4ETkJSeF ecWUaFTTAAUIMafv8g0+MnH5UYD0N2rVDgcpS7dt0VIHfRALGTNcAJ7+eZd6PVyiv5i62em3ih OdYBX8/yWMAwO0J/XYr/LHtsLYWLyPI45HH/A0r3Ng8hOojTlGgksIQgFNpi6zrGC6Oy8wRmJq VMgK3wrAx8mYjJpSLc7r3xbQ9yHc7AhJN3zFtd7DwGlwx8jFM6QXfIoOSuUzlKed+8NFnkr4cq o7Y= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:46 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Daniel Lezcano , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 08/16] dt-bindings: add resets property to dw-apb-timer Date: Fri, 5 Feb 2021 15:58:19 +0900 Message-Id: <20210205065827.577285-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Synopsis DesignWare APB timer driver (drivers/clocksource/dw_apb_timer_of.c) indirectly uses the resets property of its node as it executes the function of_reset_control_get(). Make sure that this property is documented in timer/snps,dw-apb-timer.yaml to avoid make dtbs_check warnings. Cc: Daniel Lezcano Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Acked-by: Rob Herring --- Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml index d65faf289a83..d33c9205a909 100644 --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml @@ -24,6 +24,9 @@ properties: interrupts: maxItems: 1 + resets: + maxItems: 1 + clocks: minItems: 1 items: From patchwork Fri Feb 5 06:58:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61663C433E0 for ; Fri, 5 Feb 2021 07:01:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D9E964F3B for ; Fri, 5 Feb 2021 07:01:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231264AbhBEHBO (ORCPT ); Fri, 5 Feb 2021 02:01:14 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41738 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231286AbhBEHBO (ORCPT ); Fri, 5 Feb 2021 02:01:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1612509616; x=1644045616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3+AZXlQYL+Oi9isOvjtJAUNCWKaUzQuawdKiXp5Ssaw=; b=H0R33upBmrNgHLo+30lgjoc6SiWt+8204bo0KOjrHm4JM/09YXJICEqF hJomVUqXoTv4Yrt4/acKnY7p5fUFs+78eGTB6dTZqfElVrc2Ahf1OKXz3 g5XCwP59qePuGWZJeMRnmypFB3vNW+pBM0UzctNU8xBICDhzxvrtoZrCF 042coCsicUr/CkUbasTyIOxmjKVz0i8EBEbULg5TjbYvd3Ib8PV4X+TsY acnAXv34fZeM5qWGZ9vpX4358lG9JdoDIck/LuLdT0PCTVW6cCHgg0bGK CsmXBnUcJtM0eVSfb/QQtZkWbsphV0FHzqimBlvfAqGR30vtSdzITfCP3 A==; IronPort-SDR: /ILXLv5Qwd9k4PgkYVN3Ggiz7hsU5zyHD0nY7Wy+eLaME0m+lzifbt9RC64LZN7L2gYrE+f8// jBs4d0Z94ScQro5DmquALAjBvGiHMR9IKY2gS8HObrlaGy1xVqSOJFr0oX4GrMKI8uLv5VFHNz 5QTUKEJEyne0DYLKAB45zJOU7HDzbfa6GZLA6B8eAnur59RFFvazpdf3NqH132lrcBRB5B/RqS 5AZk1icG8WpvlZM4iW3xajaTjkhpyZz+Ac5YK2W8pUnNSeTarc+u5y4+29A0frGl4YgyUgRwKK cjI= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312078" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:39 +0800 IronPort-SDR: xMmCmS+25OnsLs9tvdIB4vqV7wanKkaz2gP4l8KY45K8UxKsviQwfNJiHYh1H4NDMwAKy8+Gkg TyDpdoEFM51aG2///PAftKBw/AbYR/vJDXUckbncVuAPtW/TJz1FKOW50EeRpY24/VFTXK14A/ 7rrmcVpA/c7OkZ6rQylV/3sCot/9SzEGUHxPr1JbLWCZAyoVeElF6Cg/57FOLnB5d4+zS/pjTO JTvCUnZKRTOAjNYDGuE2jHZMhBiyUoxMC7N9Lq3B4eCtsD518OYD4GizN2urAe8dLMERX3yBAD LfILjU2twZ2oIbPwrcDtBcnQ Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:52 -0800 IronPort-SDR: yC3oq5ekANJwo7v6wev4ZL+Vbwc31TPc2WYgKjaHIL0hxRewh+O1tzmKOZbq/2pMe+LWOoKeET QaLYudZxjE3qYCN/Pus9iUo5f1ZVtA4NZjgmcIQZx7dTMggRewaPZVho6RQPCeOEiwudJWgovM 7RBkkNGkWFq/TE+3u3Pa0Zb+4Vt3uc5GECoxgtx9ngJSGHkDS7MJskStbU79l3ttJXc5mhHh0K kwQjAqnaAEkdwIoPYejwAjHevtGO64WwpWY15C263fRo9TsYw3WHyjfvsEO6nZOK8YSCCY0so4 uaQ= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:48 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 09/16] riscv: Update Canaan Kendryte K210 device tree Date: Fri, 5 Feb 2021 15:58:20 +0900 Message-Id: <20210205065827.577285-10-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the Canaan Kendryte K210 base device tree k210.dtsi to define all peripherals of the SoC, their clocks and reset lines. The device tree file k210.dts is renamed to k210_generic.dts and becomes the default value selection of the SOC_CANAAN_K210_DTB_BUILTIN_SOURCE configuration option. No device beside the serial console is defined by this device tree. This makes this generic device tree suitable for use with a builtin initramfs with all known K210 based boards. These changes result in the K210_CLK_ACLK clock ID to be unused and removed from the dt-bindings k210-clk.h header file. Most updates to the k210.dtsi file come from Sean Anderson's work on U-Boot support for the K210. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 2 +- arch/riscv/boot/dts/canaan/k210.dts | 23 - arch/riscv/boot/dts/canaan/k210.dtsi | 535 +++++++++++++++++++- arch/riscv/boot/dts/canaan/k210_generic.dts | 46 ++ include/dt-bindings/clock/k210-clk.h | 1 - 5 files changed, 554 insertions(+), 53 deletions(-) delete mode 100644 arch/riscv/boot/dts/canaan/k210.dts create mode 100644 arch/riscv/boot/dts/canaan/k210_generic.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6402746c68f3..7efcece8896c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -51,7 +51,7 @@ config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" depends on SOC_CANAAN depends on SOC_CANAAN_K210_DTB_BUILTIN - default "k210" + default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the diff --git a/arch/riscv/boot/dts/canaan/k210.dts b/arch/riscv/boot/dts/canaan/k210.dts deleted file mode 100644 index 0d1f28fce6b2..000000000000 --- a/arch/riscv/boot/dts/canaan/k210.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Western Digital Corporation or its affiliates. - */ - -/dts-v1/; - -#include "k210.dtsi" - -/ { - model = "Kendryte K210 generic"; - compatible = "kendryte,k210"; - - chosen { - bootargs = "earlycon console=ttySIF0"; - stdout-path = "serial0"; - }; -}; - -&uarths0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 354b263195a3..63c1f4c98d6c 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Sean Anderson + * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include +#include / { /* @@ -12,14 +14,33 @@ / { */ #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210"; + compatible = "canaan,kendryte-k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + dma0 = &dmac0; + gpio0 = &gpio0; + gpio1 = &gpio1_0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + pinctrl0 = &fpioa; serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; }; /* - * The K210 has an sv39 MMU following the priviledge specification v1.9. + * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". @@ -30,14 +51,14 @@ cpus { timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <0>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -46,14 +67,14 @@ cpu0_intc: interrupt-controller { }; cpu1: cpu@1 { device_type = "cpu"; + compatible = "canaan,k210", "riscv"; reg = <1>; - compatible = "kendryte,k210", "sifive,rocket0", "riscv"; riscv,isa = "rv64imafdc"; - mmu-type = "none"; - i-cache-size = <0x8000>; + mmu-type = "riscv,none"; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; + d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -64,10 +85,15 @@ cpu1_intc: interrupt-controller { sram: memory@80000000 { device_type = "memory"; + compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; }; clocks { @@ -81,40 +107,493 @@ in0: oscillator { soc { #address-cells = <1>; #size-cells = <1>; - compatible = "kendryte,k210-soc", "simple-bus"; + compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; - sysctl: sysctl@50440000 { - compatible = "kendryte,k210-sysctl", "simple-mfd"; - reg = <0x50440000 0x1000>; - #clock-cells = <1>; + debug0: debug@0 { + compatible = "canaan,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + status = "disabled"; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + status = "disabled"; }; clint0: clint@2000000 { - #interrupt-cells = <1>; - compatible = "riscv,clint0"; + compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7>; }; - plic0: interrupt-controller@c000000 { + plic0: interrupt-controller@C000000 { #interrupt-cells = <1>; - interrupt-controller; - compatible = "kendryte,k210-plic0", "riscv,plic0"; + #address-cells = <0>; + compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>, - <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; riscv,ndev = <65>; - riscv,max-priority = <7>; }; uarths0: serial@38000000 { - compatible = "kendryte,k210-uarths", "sifive,uart0"; + compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; - clocks = <&sysctl K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "canaan,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "canaan,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "canaan,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,priority = <0 1 2 3 4 5>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_APB0>, + <&sysclk K210_CLK_GPIO>; + clock-names = "bus", "db"; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + + gpio1_0: gpio-port@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + ngpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "canaan,k210-spi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <3>; + clocks = <&sysclk K210_CLK_SPI2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "canaan,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + compatible = "canaan,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + canaan,k210-sysctl-power = <&sysctl 108>; + status = "disabled"; + }; + + sha256: sha256@502C0000 { + compatible = "canaan,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50410000 { + compatible = "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "canaan,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "canaan,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + canaan,k210-misc-offset = <&sysctl 84>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "canaan,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + clocks = <&sysclk K210_CLK_APB1>; + clock-names = "pclk"; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-clk"; + clocks = <&in0>; + }; + + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <48>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "canaan,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "canaan,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI0>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,k210-spi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI1>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI3>; + reset-names = "spi"; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; }; }; }; diff --git a/arch/riscv/boot/dts/canaan/k210_generic.dts b/arch/riscv/boot/dts/canaan/k210_generic.dts new file mode 100644 index 000000000000..396c8ca4d24d --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_generic.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte K210 generic"; + compatible = "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pins>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pins: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pins: uarths-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h index a48176ad3c23..b2de702cbf75 100644 --- a/include/dt-bindings/clock/k210-clk.h +++ b/include/dt-bindings/clock/k210-clk.h @@ -9,7 +9,6 @@ /* * Kendryte K210 SoC clock identifiers (arbitrary values). */ -#define K210_CLK_ACLK 0 #define K210_CLK_CPU 0 #define K210_CLK_SRAM0 1 #define K210_CLK_SRAM1 2 From patchwork Fri Feb 5 06:58:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AFD7C433DB for ; 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IronPort-SDR: sSc8BuwAogeuEGiKeV9TtuhC3sQW8DqvmJ3Po4XasYyGH9nUG4GjlMfpF4TnC1R7WV+ueEtUGR ze9cEwWEiGeX6dLShRztwSGmfMqUrFLKPNcJ/JcZeMkXOzQOlrO3r+KoT7q9r8ODSazwm2pBPD gU/oIgqd6b7eHi8UbRXOcm2bFsN/8WJFQt0CVvhtYr/iBXyL8ZA8yqbxvJ0eWdvh4oTcWBpNPc poXl4Ovh2smy5POlM7uw08k0/WWPCSR6+gUBqMKk/3LcTb0/63DmwnRsJEKhw3evg430Cp+Op9 68w= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312081" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:41 +0800 IronPort-SDR: 9n7o4rdCNRUYba2Xi74RnUrjEttMxvmgyQIfHnMKDMQtStb/zjTVg6+ksZB7aSh8BABb52o8m4 V03w3R1asEN2wz0S0z/ianVd26+Si1yeCKpEBBuMKDWMg7dVQdTxN7eGdlhZ0znHDmrdNvZlbH lxxUhBLa6UM6LziGBo+ZdlT7rKfGrZYmXifsVynEUyLz1ske6htMWh+HVocVeUTLEkzqzmjYyE t+Uppdm1uEKTST1heFJ/kipYAmDc+ApBjXcOWUH8nSBbdOgbWpKIbjkQo6sOiGabPDWjqPxdM0 fx4xjU+EzKTfSedBm1gQsN8J Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:53 -0800 IronPort-SDR: A8BBPlyLJMDAyXDzrWu71yBy1dvVKX1KOWyiHc5iqi0/3PXSrcSyYlRQfV95gwFryGVmVNzVSM zouEU+GDpMGJ8EfTirSk0vlwwtbtrheo8psnuEBP5/NA7YLC/EYcNmeCSXwmLbzJAxQnOawgzp wjcjmwhljmmCDOtMJdRzK/dymm1QwrhN5iZesltPZvINQEkxZvGlSOvrUOKGNw0J0dDCLIUnOu djxpNIXSm8tIHHAjPIGruIxnygCpofZGzjuEX8v92gsVLu/Iq6jW6ZvaTMarZpVQBXAVikbdOw iA4= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:50 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 10/16] riscv: Add SiPeed MAIX BiT board device tree Date: Fri, 5 Feb 2021 15:58:21 +0900 Message-Id: <20210205065827.577285-11-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maix_bit.dts for the SiPeed MAIX BiT and MAIX BiTm boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../riscv/boot/dts/canaan/sipeed_maix_bit.dts | 234 ++++++++++++++++++ 1 file changed, 234 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts new file mode 100644 index 000000000000..11e491410f00 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include +#include + +/ { + model = "SiPeed MAIX BiT"; + compatible = "sipeed,maix-bit", "sipeed,maix-bitm", + "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led0 { + color = ; + label = "green"; + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + label = "red"; + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + led2 { + color = ; + label = "blue"; + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-names = "default"; + pinctrl-0 = <&jtag_pinctrl>; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <15000000>; + spi-cs-high; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Fri Feb 5 06:58:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73DC7C433E6 for ; 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04 Feb 2021 22:40:55 -0800 IronPort-SDR: PSW0GsCjVJINWB8z7FUaSLwfGkwrYe4EwKurAVPYTQzQ46QB/WjahQfFX5R7SHv8X1YhNNIfBZ hW1J+7qaOhdAB0G5Vbt+SU2ucnGuAih+iPzVBIb+Bi/i+ChYyXibC5aL3LIvySvZz65gT7CGYj aSu30ESNe5LL9L/O2N2vYADU10y619Cx0WJYz5HHp/MBCAc42jy4lwJpwjiJrLqqW1iUXXKDQc I5gni3V7mEohFs6wwXZaTCjLAXHFL/h2YURBVrqdmo6QnQT0ascOdgM7mu11leFV6DKYCtMp6Y maI= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:51 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 11/16] riscv: Add SiPeed MAIX DOCK board device tree Date: Fri, 5 Feb 2021 15:58:22 +0900 Message-Id: <20210205065827.577285-12-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maix_dock.dts for the SiPeed MAIX DOCK m1 and m1w boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maix_dock.dts | 236 ++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts new file mode 100644 index 000000000000..fae0149a8740 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include +#include + +/ { + model = "SiPeed MAIX Dock"; + compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w", + "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + /* + * Note: the board wiring drawing documents green on + * gpio #4, red on gpio #5 and blue on gpio #6. However, + * the board is actually wired differently as defined here. + */ + led0 { + color = ; + label = "blue"; + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + label = "green"; + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + led2 { + color = ; + label = "red"; + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Fri Feb 5 06:58:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A5ADC433E0 for ; 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IronPort-SDR: 4XRlzqktWM44lJYlLAQCKqxeev1dgjJUW/c1LexGoQP7rZZDQcM5wfBKZMjeaernfg8WCaD5R4 4wNwMxRCqp/KvXyxwZoNf50PdQfiSd/E5APN4V/V/t5ZTwygByvuN+jCvooMID/OEDEG87FxDF QgP2Qw5M7A1QphpQsuHT1/Z/5V/cQx/hGZxyueW3OOaeGkuuZdmkNJokvn2fMnQot/AHrGmCTS SJty3YR5nA4HDVv7Bx9/G9RQgvCuL6DoKQA13wXsTiKhGmOcop2ylfdxi3mSqe1Ee+IH3UnmLc bng= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312090" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:46 +0800 IronPort-SDR: rTAEOmni0lFZon1GC8U8z7ZxKHWjyT+f6ABhF+M+pbDSn7NmYr98YEaR2+MYlotjaZC9S+OlFr eUABDNosKej5XZByxDehGzJ3yHNgUEoN41cmhVhFF7picFtBJgA2Du6VjcVaSqP6HFEJ9pbHmT isKkYt4bF7jwo0r0ccIZQBvdQIuPMi5Ww29Ed6P701Uumf2XYzDbX4fXdPwoWjBH0/8I84wYJ6 rgInUe9llvG3mcPyUmZvn+FOow+DLiDjl94ASWXTsNMgpoMf6JA0NRQBkQBMVLwkQQW6AKAStG 9+UG2ZDCNMISfgtHSFb5TCuM Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:57 -0800 IronPort-SDR: uXFGcNsMBrrj8ZuT/TO70NfI+mJpz/Le6II/r38+wgcySQpy5yTJKTx1THCrVuZRuhnCIcUzmp AKKdW3dGICK+ANAL3/yyv+w69vbNEyiiI2C65TpTHlmbQxQ4aRo/bR8n6yHqzsIKT1EzErHL70 OvS/H2NxOv9m84QPMpAu2YZ9rq4VDItNm6mlFlq7hOJf6JnViykfa0ky69Aio/FlJrBRvqrHur AP5kYtkkbtgaEWynCYY7ckQW79woyE2K99rYjq72aIzZjm8ufp0mZCiZU0jgf2pMjhA6Fc6tWQ d3s= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:53 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 12/16] riscv: Add SiPeed MAIX GO board device tree Date: Fri, 5 Feb 2021 15:58:23 +0900 Message-Id: <20210205065827.577285-13-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maix_go.dts for the SiPeed MAIX GO board. This device tree enables buttons, LEDs, gpio, i2c and spi/mmc SD card devices. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 244 ++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maix_go.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts new file mode 100644 index 000000000000..373fbaa3ab94 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include +#include + +/ { + model = "SiPeed MAIX GO"; + compatible = "sipeed,maix-go", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led0 { + color = ; + label = "green"; + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + label = "red"; + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + led2 { + color = ; + label = "blue"; + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + up { + label = "UP"; + linux,code = ; + gpios = <&gpio1_0 7 GPIO_ACTIVE_LOW>; + }; + + press { + label = "PRESS"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + down { + label = "DOWN"; + linux,code = ; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Fri Feb 5 06:58:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE399C433DB for ; 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IronPort-SDR: frNkhrYPZ0lov9lXq01kYUCUMUOV01i7Ddw5mhLhh/4HkACGF6BsCYg6lZwN0Y4CYnUufX50+5 +MeFHwmSLb5cSyfe+6nGi3ck41cVSfY5L2UlIMzWLiwSsW2MAtHo1fFkvKpARCRfR+uG5hGQyl +a0D01Ia3aXl/B7Dw4svd+0jmc9dL/ETpZ5h1XxIdNEDjgsFO0u6MhM83Pfk5QuxxjBDt7Oy8z uMUrwzNGp/g608lA9J2X/E3VbcZhSXi+jtccNPN4U/GSYG7sLuv7Qo+7/QDwTKUs1Zn9DOdBjy UYQ= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312096" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:49 +0800 IronPort-SDR: 3gJTK+9OS3hEEF4DzOVbHFQJT1xkk4eFVZk7l/vCrZoWHCG3vzHNNQAWlydXGuEdD35K4hHNRo wWBj+8/S03BghRPHVrqkTHF7WtWwL4S0mjq0Yf4r26rNWxExDvWKXYmvomRTjsxPew/Ai/SDKS dFsELeqrfutkNA2AFkrpAjtQTPWi+vNY4bCi3NFaXm7ywxlIhZ1KDKYy/19SfQs5mK7P7o4vXz 520pIy5EDBXFheMCNxSGjGPtlGhwyMEIzEbI2SpGSUQJgp7e8VUmTZ0YzAObsP0EKaVcb8/JM6 jJVbGMx22jYPRctPicmkkQya Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:40:58 -0800 IronPort-SDR: ZkRKmDBpSYyGZjxEX3twwinUkESwujwP1G8Pk3DBcmaws/EHvUR/6CXejYTTR5V/5RHc4WzjGu oc8sj/OiNpCbjH7SCYXJaY8qVXnh6frTDU5nKgxOEuYNpoO98IwmonemJ17laFY3tDVL8a/zi/ IDTbD9MpsdvD6DORQIWCtWAgju2AWLsq4/oyuMWxHJKBKQhLxhge7wvF+VqRQPgl+VMxqjWWgE k0kTO7odmH/O3fH14rj9tFH1U2wD7AFmrxVJuflsWjJHAFhr3QW4UTgvx3zQpbw5LS3UZqUfYh 92k= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:55 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 13/16] riscv: Add SiPeed MAIXDUINO board device tree Date: Fri, 5 Feb 2021 15:58:24 +0900 Message-Id: <20210205065827.577285-14-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree sipeed_maixduino.dts for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal --- .../boot/dts/canaan/sipeed_maixduino.dts | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/sipeed_maixduino.dts diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts new file mode 100644 index 000000000000..804edc45eeeb --- /dev/null +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; + + vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&fpioa { + status = "okay"; + + uarths_pinctrl: uarths-pinmux { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , /* BOOT */ + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + ; /* Header "13" */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + i2s1_pinctrl: i2s1-pinmux { + pinmux = , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + power-supply = <&vcc_3v3>; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Fri Feb 5 06:58:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 377783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C3D5C433E9 for ; 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IronPort-SDR: n+Lfc53Ttx3gl0wLGavJrgfVySeqyhCLQo2i3IzX6JwygpfPS+GRp/G6/5ErSA/HIUGK9J59Gp niAYzzr+/VkssJnooQdScCfsKzMcmDc0RdPqD60pp7xHkgBDnm1dfTZl75O21vBpjBtxxEOsTD 6QhbRgSFOmEs0GZFuTUnUHeT1Fg1i0VzjnflvmCHxSlnUWhDUJhKg/aruIqgtcK9q6xi7HYdvW 2tiL+sVLD8uiBzjgPR+B3jXbf5WH0qplPxsfcGB83S9i4xZubkYEzyypkaMkXv3l4Q2HDGzlwe WpI= X-IronPort-AV: E=Sophos;i="5.81,154,1610380800"; d="scan'208";a="263312100" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 05 Feb 2021 15:16:51 +0800 IronPort-SDR: oMR8gEjZWw3AG6PhJo16DQQ7lvDTicvnh+dpjJCsTVt7SM6PyYPrlSzFt3N9V3UDw40fKA2EjD Q9AftBGZEvFd1DjvvF0Sxe92K+/aNo4ne8O3d416NPjGmsC+MUAPHX58xu9KOa5ktD3depNg+v PgMVsN0ysOTEFw4/5NBAKuzSwebU5ujcDLCE9Nnmyiq+G5Z38Uh5mBsyKwZ0lRXpM7JS1k2Bn4 Yv2I+VITVi6X+19YpFxQ38joqj6Z/GV50OxIJe+VcICAm1zpkURhPBKKj8nSTUDK9qCKT4U0ga RziVLfuPIVpwovokfGdjHAKF Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 22:41:00 -0800 IronPort-SDR: BhznuHaBuqfd9XgQEXxknXXCNMnkxGsMozXAaNIXVMDnNPAzwk2mtsCMNpDhfTbxesyNDSz01m SeM2quxhRDyyPxI4iF0KGW3iY3d0VOGG/z4b4Z3At2A93NdJFtP/V5JopTH6FMZHl9MWRRfme1 6qs64ArKObLH4xGCQUEkxlqGowFxLnFQbry0nyH2DzL1SIdXue4mwCn0gB5xYoYk+Vq2/u8qbm 8qTCESC7O2otpC+RY3L3uz9gavh90UKK7iu07uPLgUnByXsNUHELNeoWcaTiia8hbvpuQ4o86O mMI= WDCIronportException: Internal Received: from wdapacbjl0003.my.asia.wdc.com (HELO twashi.fujisawa.hgst.com) ([10.84.71.58]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Feb 2021 22:58:56 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v16 14/16] riscv: Add Kendryte KD233 board device tree Date: Fri, 5 Feb 2021 15:58:25 +0900 Message-Id: <20210205065827.577285-15-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205065827.577285-1-damien.lemoal@wdc.com> References: <20210205065827.577285-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the device tree canaan_kd233.dts for the Canaan Kendryte KD233 development board. This device tree enables LEDs, some gpios and spi/mmc SD card device. The WS2812B RGB LED and the 10 positions rotary dip switch present on the board are left undefined. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Anup Patel --- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 177 ++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/canaan_kd233.dts diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts new file mode 100644 index 000000000000..d9af66144938 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte KD233"; + compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key0 { + label = "KEY0"; + linux,code = ; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* wr */ + ; /* dc */ + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , /* Rot. dip sw line 8 */ + , /* Rot. dip sw line 4 */ + , /* Rot. dip sw line 2 */ + , /* Rot. dip sw line 1 */ + , + , + ; + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "ilitek,ili9341"; + reg = <0>; + dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +};