diff mbox series

[edk2,edk2-platforms,v3,11/18] Hisilicon/D06: Add PCI_OSC_SUPPORT

Message ID 20190320080829.52003-12-ming.huang@linaro.org
State New
Headers show
Series Fix issues and improve D0x | expand

Commit Message

Ming Huang March 20, 2019, 8:08 a.m. UTC 
Add PCI_OSC_SUPPORT for remaining host bridges to remove fail
output in kernel:
[  103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND);

Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>

---
 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 200 +++++++++++---------
 1 file changed, 106 insertions(+), 94 deletions(-)

-- 
2.9.5

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diff mbox series

Patch

diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
index 4d9d9d95be68..6dc380f27fa2 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
@@ -17,6 +17,90 @@ 
 **/
 
 //#include "ArmPlatform.h"
+
+/*
+  See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5
+*/
+#define PCI_OSC_SUPPORT() \
+  Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
+  Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
+  Method(_OSC,4) { \
+    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
+      /* Create DWord-adressable fields from the Capabilities Buffer */ \
+      CreateDWordField(Arg3,0,CDW1) \
+      CreateDWordField(Arg3,4,CDW2) \
+      CreateDWordField(Arg3,8,CDW3) \
+      /* Save Capabilities DWord2 & 3 */ \
+      Store(CDW2,SUPP) \
+      Store(CDW3,CTRL) \
+      /* Only allow native hot plug control if OS supports: */ \
+      /* ASPM */ \
+      /* Clock PM */ \
+      /* MSI/MSI-X */ \
+      If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
+        And(CTRL,0x1E,CTRL) \
+      }\
+      \
+      /* Do not allow native PME, AER */ \
+      /* Never allow SHPC (no SHPC controller in this system)*/ \
+      And(CTRL,0x10,CTRL) \
+      If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
+        Or(CDW1,0x08,CDW1) \
+      } \
+      \
+      If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
+        Or(CDW1,0x10,CDW1) \
+      } \
+      \
+      /* Update DWORD3 in the buffer */ \
+      Store(CTRL,CDW3) \
+      Return(Arg3) \
+    } Else { \
+      Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
+      Return(Arg3) \
+    } \
+  } // End _OSC
+
+#define PCI_OSC_SUPPORT_HOTPLUG() \
+  Name(SUPP, Zero) /* PCI _OSC Support Field value */ \
+  Name(CTRL, Zero) /* PCI _OSC Control Field value */ \
+  Method(_OSC,4) { \
+    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \
+      /* Create DWord-adressable fields from the Capabilities Buffer */ \
+      CreateDWordField(Arg3,0,CDW1) \
+      CreateDWordField(Arg3,4,CDW2) \
+      CreateDWordField(Arg3,8,CDW3) \
+      /* Save Capabilities DWord2 & 3 */ \
+      Store(CDW2,SUPP) \
+      Store(CDW3,CTRL) \
+      /* Only allow native hot plug control if OS supports: */ \
+      /* ASPM */ \
+      /* Clock PM */ \
+      /* MSI/MSI-X */ \
+      If(LNotEqual(And(SUPP, 0x16), 0x16)) { \
+        And(CTRL,0x1E,CTRL) \
+      }\
+      \
+      /* Always allow native PME, AER (no dependencies) */ \
+      /* Never allow SHPC (no SHPC controller in this system)*/ \
+      And(CTRL,0x1D,CTRL) \
+      If(LNotEqual(Arg1,One)) { /* Unknown revision */ \
+        Or(CDW1,0x08,CDW1) \
+      } \
+      \
+      If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \
+        Or(CDW1,0x10,CDW1) \
+      } \
+      \
+      /* Update DWORD3 in the buffer */ \
+      Store(CTRL,CDW3) \
+      Return(Arg3) \
+    } Else { \
+      Or(CDW1,4,CDW1) /* Unrecognized UUID */ \
+      Return(Arg3) \
+    } \
+  } // End _OSC
+
 Scope(_SB)
 {
   Device (PCI0)
@@ -139,53 +223,7 @@  Scope(_SB)
       Return (RBUF)
     }                                        // Method(_CRS), this method return RBUF!
 
-  //
-  // OS Control Handoff
-  //
-  Name(SUPP, Zero) // PCI _OSC Support Field value
-  Name(CTRL, Zero) // PCI _OSC Control Field value
-
-  Method(_OSC,4) {
-    // Check for proper UUID
-    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
-      // Create DWord-adressable fields from the Capabilities Buffer
-      CreateDWordField(Arg3,0,CDW1)
-      CreateDWordField(Arg3,4,CDW2)
-      CreateDWordField(Arg3,8,CDW3)
-
-      // Save Capabilities DWord2 & 3
-      Store(CDW2,SUPP)
-      Store(CDW3,CTRL)
-
-      // Only allow native hot plug control if OS supports:
-      //  ASPM
-      //  Clock PM
-      //  MSI/MSI-X
-      If(LNotEqual(And(SUPP, 0x16), 0x16)) {
-        And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
-      }
-
-      // Always allow native PME, AER (no dependencies)
-
-      // Never allow SHPC (no SHPC controller in this system)
-      And(CTRL,0x1D,CTRL)
-
-      If(LNotEqual(Arg1,One)) {  // Unknown revision
-        Or(CDW1,0x08,CDW1)
-      }
-
-      If(LNotEqual(CDW3,CTRL)) {  // Capabilities bits were masked
-        Or(CDW1,0x10,CDW1)
-      }
-
-      // Update DWORD3 in the buffer
-      Store(CTRL,CDW3)
-      Return(Arg3)
-    } Else {
-      Or(CDW1,4,CDW1) // Unrecognized UUID
-      Return(Arg3)
-    }
-  } // End _OSC
+  PCI_OSC_SUPPORT_HOTPLUG ()
 
   Method (_HPX, 0) {
     Return (Package(2) {
@@ -270,6 +308,8 @@  Device (PCI1)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -333,6 +373,8 @@  Device (PCI2)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -382,6 +424,8 @@  Device (PCI3)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -431,6 +475,8 @@  Device (PCI4)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0x0F)
@@ -505,6 +551,8 @@  Device (PCI5)
     Return (RBUF)
   }                                    // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -870,53 +918,7 @@  Device (PCI6)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
-  //
-  // OS Control Handoff
-  //
-  Name(SUPP, Zero) // PCI _OSC Support Field value
-  Name(CTRL, Zero) // PCI _OSC Control Field value
-
-  Method(_OSC,4) {
-    // Check for proper UUID
-    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
-    // Create DWord-adressable fields from the Capabilities Buffer
-    CreateDWordField(Arg3,0,CDW1)
-    CreateDWordField(Arg3,4,CDW2)
-    CreateDWordField(Arg3,8,CDW3)
-
-    // Save Capabilities DWord2 & 3
-    Store(CDW2,SUPP)
-    Store(CDW3,CTRL)
-
-    // Only allow native hot plug control if OS supports:
-    //  ASPM
-    //  Clock PM
-    //  MSI/MSI-X
-    If(LNotEqual(And(SUPP, 0x16), 0x16)) {
-      And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
-    }
-
-    // Always allow native PME, AER (no dependencies)
-
-    // Never allow SHPC (no SHPC controller in this system)
-    And(CTRL,0x1D,CTRL)
-
-    If(LNotEqual(Arg1,One)) { // Unknown revision
-      Or(CDW1,0x08,CDW1)
-    }
-
-    If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
-      Or(CDW1,0x10,CDW1)
-    }
-
-    // Update DWORD3 in the buffer
-    Store(CTRL,CDW3)
-    Return(Arg3)
-    } Else {
-    Or(CDW1,4,CDW1) // Unrecognized UUID
-    Return(Arg3)
-    }
-  } // End _OSC
+  PCI_OSC_SUPPORT_HOTPLUG ()
 
   Method (_HPX, 0) {
     Return (Package(2) {
@@ -1002,6 +1004,8 @@  Device (PCI7)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -1066,6 +1070,8 @@  Device (PCI8)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -1115,6 +1121,8 @@  Device (PCI9)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)
@@ -1164,6 +1172,8 @@  Device (PCIA)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0x0F)
@@ -1238,6 +1248,8 @@  Device (PCIB)
     Return (RBUF)
   }                                         // Method(_CRS), this method return RBUF!
 
+  PCI_OSC_SUPPORT ()
+
   Method (_STA, 0x0, NotSerialized)
   {
     Return (0xf)