From patchwork Wed Feb 20 07:28:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 158781 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4602529jaa; Tue, 19 Feb 2019 23:29:25 -0800 (PST) X-Google-Smtp-Source: AHgI3IbtgB+18LtPKVlYNDmVtLMiE5xrvLc+I1pNs2zzm1z2M+cCd2mf5+Q65jH9nrC8LILBtTyV X-Received: by 2002:a17:902:6b49:: with SMTP id g9mr35776541plt.291.1550647765862; Tue, 19 Feb 2019 23:29:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550647765; cv=none; d=google.com; s=arc-20160816; b=NSvVOv4NzVBIP/yFm2+fK5/P3TCgrFWc8FhnBuX2uW9uVPw8syRw7UKIOBdVzv4YWl Xgzf3YUCtLs34oBpiggMw76nyEWQBo7I1VqzkDmpx22ThsghLa0b/Hvz1aoB+voFeG05 7jd3dTN4sLTURQ1Fgsen99lfBUjmdoj/FiguL9nAVpEr4LoxGe4dRtoglM/hkS3b7Onl UEcLMyKvkavfJ1Mrxml1FA1s+uUN/To06j/izj1UYjWgJGwt6LU/Pfeq8ObwygN9MCMj TGXhd4xDr7p7riXF9XFLKxdA2DOeXb+Bw1AwrgqL0ZjAXE7KifeIRxM7AAi/Fmh9bNHs Y/qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=ka0rNDgKhwsFPf+PwM9K4xmwK3OtP4pH+PRKDYJileA=; b=lyl+t+4f5bCk/eyqOb/TM/1T8dva2vRT30admV1O6L+ISIQLJMezPqqwN4ITNrRbrU TcZTM9rT4soLuVJdoDsmqd+Dt9N+UkQ4DO1FCxHdHH/j4CEH7qfOVQBlSwd2U6jbCj47 Ul7NAVm4gCFsh3lsPrCXa6Hp0WNTcFdmQlCFaz+3CuLULUa8dncMAqOAO8BFWT76YvRq pdhfmx8nmR6YPGjPHRKzRToJ7OIHnpam5jl02t8ynE+Bkz69o7yY56/+VofTvhBDk28X f9J+McuX+EyvucfrgOsr6qPCeV1lx3zIAlKq1RSwtPhmstFmNkQn41TJLI1bE6KLRBiq SfEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cDaHcY0I; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id c65si18293281pfe.202.2019.02.19.23.29.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 23:29:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cDaHcY0I; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9EAFD211CBD06; Tue, 19 Feb 2019 23:29:22 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 55D1D211CBD06 for ; Tue, 19 Feb 2019 23:29:21 -0800 (PST) Received: by mail-pf1-x444.google.com with SMTP id u9so4225134pfn.1 for ; Tue, 19 Feb 2019 23:29:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7O72LbCauLQv6X2A/KQ179vLdajE3FuigezLDUyWdVc=; b=cDaHcY0INklmFSeRu9WbAtyMB9MowxrBmmvnxaYxtn+efGRIgKNRi/r2KtmsCTTrIe YRacUR3SlS7Pfqx7Y0B3rWc97zszZVAdMIqvHfHNnZiCk0BkUxT/2qv+Z4EXPvnRtgc+ 3BLRsdHUC9iIiLbkup9FPzUdoIsJq0tnKZNAuRTUxqU28MUUb3EV/8fwONhaB5uaJUKT UVNpmUpob32YK0yYmH36jIB3zY2gYlK0ie0DjYsy042ifcxce4dVUvzVKI0AmGVL1aWN Lgjfb2N3eW2aL7/MPbjsOZ7L7I4E96E8gaBRKL8AzKPi5mzaMqru+SjxSKWTbGx7JdKk wdSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7O72LbCauLQv6X2A/KQ179vLdajE3FuigezLDUyWdVc=; b=M1dagkxvrSn3T3Vyd/rXvLzcgY/iYpYQOWhddwfzumGvpDdMUCxc3ozyW7VXT1xnuI GaF/ufO5pGZhRuM7HUU9bUaTvJOd36Oxtf8jbiHHUDmOnkma30xtjGhu53h+gmZkvr+q pBOlNWC46gJdo1dTGwt/J5askUT9lsYBUpRdN8waHJCLxnA1AIZvneu/xXTOQg0WaT5k 1j03nlljaVj+XCQLgFBTaG8Y+Y9bovZYQHsMe7GAvCBKOFXearhn+DGgGg2nyOVjcAuc wGhWwRW0dX3fuImLXC2vfYvg78EmvXN0cKcXBPmzTHiiTcGlRa+cZrZYFTWnHulo7xzC GHJg== X-Gm-Message-State: AHQUAubypxPdoCw8Qb8wvgeY0biRxastG55mbtP+0SZe+7p517Yc5ZDG EFFB9Fs1nnmUGluVXS8GtJg9CA== X-Received: by 2002:a63:c0e:: with SMTP id b14mr31830691pgl.236.1550647760984; Tue, 19 Feb 2019 23:29:20 -0800 (PST) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id 23sm19152969pft.187.2019.02.19.23.29.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Feb 2019 23:29:20 -0800 (PST) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Feb 2019 15:28:30 +0800 Message-Id: <20190220072837.35058-12-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190220072837.35058-1-ming.huang@linaro.org> References: <20190220072837.35058-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 11/18] Hisilicon/D06: Add Setup Item "Support DPC" and delete some PCIe menus X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add setup item "Support DPC" to enable or disable PCIe DPC (Downstream Port Containment). The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport; + UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP); - suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif; goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; // + //Set the default value of the PCIe option + // + Configuration.PcieDPCSupport = 0; + // //Set the default value of the Misc option // Configuration.EnableSmmu = 1; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE); - goto VFR_FORMID_PCIE_SOCKET0, - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - goto VFR_FORMID_PCIE_SOCKET1, - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; endoneof; endform; -form formid = VFR_FORMID_PCIE_SOCKET0, - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); - - goto VFR_FORMID_PCIE_PORT2, - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT4, - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT5, - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT6, - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT7, - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET1, - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); - goto VFR_FORMID_PCIE_PORT10, - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT12, - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT13, - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); -endform; - -form formid = VFR_FORMID_PCIE_PORT0, - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); - #undef INDEX - #define INDEX 0 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT1, - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); - - #undef INDEX - #define INDEX 1 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT2, - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); - - #undef INDEX - #define INDEX 2 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT3, - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); - - #undef INDEX - #define INDEX 3 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT4, - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); - - #undef INDEX - #define INDEX 4 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT5, - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); - - #undef INDEX - #define INDEX 5 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT6, - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); - - #undef INDEX - #define INDEX 6 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT7, - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); - - #undef INDEX - #define INDEX 7 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT8, - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); - - #undef INDEX - #define INDEX 8 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT9, - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); - - #undef INDEX - #define INDEX 9 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT10, - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); - - #undef INDEX - #define INDEX 10 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT11, - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); - - #undef INDEX - #define INDEX 11 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT12, - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); - - #undef INDEX - #define INDEX 12 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT13, - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); - - #undef INDEX - #define INDEX 13 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT14, - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); - - #undef INDEX - #define INDEX 14 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT15, - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); - - #undef INDEX - #define INDEX 15 - #include "PciePortConfig.hfr" - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0"