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[198.145.21.10]) by mx.google.com with ESMTPS id a26si7346550pgl.282.2018.11.28.06.34.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Nov 2018 06:34:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bQHCVAYZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F1D1D21196215; Wed, 28 Nov 2018 06:34:12 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::343; helo=mail-wm1-x343.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D698121959CB2 for ; Wed, 28 Nov 2018 06:34:09 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id a18so2159224wmj.1 for ; Wed, 28 Nov 2018 06:34:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K5H32o5b+f2+A6FavyKqEpXujCvWiWZ3Daj5aQkD03s=; b=bQHCVAYZGUfanx6xH4atLhS4873homHhZrj5hBUkhYXS94aMAfe0AAhPT9y8IoVEWo 7DYDott7a77EVOUc8CIlMF6FajQlSCiXGePlAMRVbZoIT2CP5yF8eUrZPlD4Lzc6CLn1 ulIvClcJzMBbzaumZUTOjUey//KJ9GSemwMus= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K5H32o5b+f2+A6FavyKqEpXujCvWiWZ3Daj5aQkD03s=; b=hCvkkA5h19ofb3TIxw+ytaDO8bcDfLGobuGm9+M66oFUKsj1qUilf6Z+yPYtfaiCIr 4hfneht4YzCP+JC1Jifb1LixY7eoaxwR8ylBxGUK7+aL+Hcxovms5HJd2KZD/LtDOuoK 6pQWfUXC2N+/pfm5oBwEtt6SrOqwxthz4HGdsTY85v+sp4tr1Ee84BTEJl7hlWnAVVHT tdunTOna3C3dUJdlzBZ5VJcC8wbxJx9OA0CNFvgZ7MymqUebubaCQpHXKSoERBRrHNSG VSLBI/b5N763a14dc2Ne3V4Ah8wdA5DRkRYbi2tfxovY27/AzgyOOrwxGiPK98nt0p4z gjZA== X-Gm-Message-State: AA+aEWY98kqjtCyKGRUDK1TPOjbQ356/ZQtDu6h9D0yDpOSVwFVmcenR Ht0Df4leC9Z+9OBoV3R9QvR2cHdC1K4= X-Received: by 2002:a1c:70e:: with SMTP id 14mr3107364wmh.139.1543415648011; Wed, 28 Nov 2018 06:34:08 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:296f:238b:c20d:3626]) by smtp.gmail.com with ESMTPSA id 6sm3391891wmk.26.2018.11.28.06.34.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Nov 2018 06:34:07 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 28 Nov 2018 15:33:44 +0100 Message-Id: <20181128143357.991-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181128143357.991-1-ard.biesheuvel@linaro.org> References: <20181128143357.991-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v3 03/16] ArmVirtPkg/FdtPciHostBridgeLib: map ECAM and I/O spaces in GCD memory map X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Laszlo Ersek Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Up until now, we have been getting away with not declaring the ECAM and translated I/O spaces at all in the GCD memory map, simply because we map the entire address space with device attributes in the early PEI code, and so the ECAM space will be mapped wherever it ends up. Now that we are about to make changes to how ArmVirtQemu reasons about the size of the address space, it would be better to get rid of this mapping of the entire address space, since it can get arbitrarily large without real benefit. So start by mapping the ECAM and translated I/O spaces explicitly, instead of relying on the early PEI mapping. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laszlo Ersek --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 1 + ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 46 +++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf index 0995f4b7a156..4011336a353b 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf @@ -42,6 +42,7 @@ [Packages] [LibraryClasses] DebugLib DevicePathLib + DxeServicesTableLib MemoryAllocationLib PciPcdProducerLib diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index 5b9c887db35d..ebfa14a349f4 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -82,6 +83,33 @@ typedef struct { #define DTB_PCI_HOST_RANGE_IO BIT24 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24) +STATIC +EFI_STATUS +MapGcdMmioSpace ( + IN UINT64 Base, + IN UINT64 Size + ) +{ + EFI_STATUS Status; + + Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Base, Size, + EFI_MEMORY_UC); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n", + __FUNCTION__, Base, Size)); + return Status; + } + + Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n", + __FUNCTION__, Base, Size)); + } + return Status; +} + STATIC EFI_STATUS ProcessPciHost ( @@ -266,7 +294,23 @@ ProcessPciHost ( "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size)); - return EFI_SUCCESS; + + // Map the ECAM space in the GCD memory map + Status = MapGcdMmioSpace (ConfigBase, ConfigSize); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Map the MMIO window that provides I/O access - the PCI host bridge code + // is not aware of this translation and so it will only map the I/O view + // in the GCD I/O map. + // + Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize); + ASSERT_EFI_ERROR (Status); + + return Status; } STATIC PCI_ROOT_BRIDGE mRootBridge;