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[91.69.153.33]) by smtp.gmail.com with ESMTPSA id x79sm16469106wmd.42.2018.11.23.04.14.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 04:14:45 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 23 Nov 2018 13:14:28 +0100 Message-Id: <20181123121431.22353-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181123121431.22353-1-ard.biesheuvel@linaro.org> References: <20181123121431.22353-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 2/5] ArmPkg/ArmMmuLib: take the CPU supported maximum PA space into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Laszlo Ersek , Eric Auger MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" In preparation of permitting the virt code to define a larger PA space size via gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize than what the CPU actually supports, take the CPU's capabilities into account when setting up the page tables. This is necessary because KVM will shortly support variable PA space sizes, and to support running the same UEFI binaries regardless of that limit, PcdPrePiCpuMemorySize needs to be treated as an upper bound rather than a fixed size. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 4b62ecb6a476..a4fde9b59383 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -593,6 +593,7 @@ ArmConfigureMmu ( { VOID* TranslationTable; UINT32 TranslationTableAttribute; + UINTN MaxAddressBits; UINT64 MaxAddress; UINTN T0SZ; UINTN RootTableEntryCount; @@ -605,7 +606,9 @@ ArmConfigureMmu ( } // Cover the entire GCD memory space - MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1; + MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), + PcdGet8 (PcdPrePiCpuMemorySize)); + MaxAddress = (1UL << MaxAddressBits) - 1; // Lookup the Table Level to get the information LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);