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[198.145.21.10]) by mx.google.com with ESMTPS id j124-v6si10292619pfg.157.2018.08.31.06.27.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 Aug 2018 06:27:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fp93cBF7; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 59CA62110BD56; Fri, 31 Aug 2018 06:27:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::644; helo=mail-pl1-x644.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F1D242110BD4E for ; Fri, 31 Aug 2018 06:27:28 -0700 (PDT) Received: by mail-pl1-x644.google.com with SMTP id b92-v6so458307plb.0 for ; Fri, 31 Aug 2018 06:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PWtiTXCBKUIkw2KT4pAS7siS+h5xkuJINHB0tLZPi5g=; b=fp93cBF7MtwMuyhuepLJSxIaviJ64wVp05KT+99zmOKKdf+ICw9eZIetQJUiDYjjSf nSMctBYe6t/AnF5CMDJPpZIzdvTHQWyIFpPa+U2s7ZqWRip5/HnTkwfFHiBVtN0p8xUO NgbowwSpp5O/HRw+26q81yZQY7cCuWSdprNGw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PWtiTXCBKUIkw2KT4pAS7siS+h5xkuJINHB0tLZPi5g=; b=GBy3SWM06qK1VxZeJ7nxB0Rk5qbLOfDFV82urOnJoQv+R+kJFSmiTnPgLzUJgC8xdk KjFEQuU5kZ2Q5UZ8mxFjftPuse5xJ723vQjiFNtEUVWW93TGFccsQE16Lz2f0NFTHDgx zj3hOsmF+6BoYEeKlfq9ZqjWPb5XtsCVDF7Z4Hy69iNHFLksOz6l8m+eRFcR9cyMd3iH kJtapafokbTPqo1cE2idC+Cjx/Etiu0uByFisArebiCecXRGqg1Un8zZZ6/Xm5numc1b W3zKmsTbnm2/4jRK8BYWvvZUo8hu2ZTEEaxcAIEnu7yHXGnPBng8gdrwZMXe8PfdZN+9 ceaA== X-Gm-Message-State: APzg51AFep9fWtw6bIyHaC2mFt8g5Y+qHfwlyiyx4xv6euexYf4vYfaH w5hCH1r6qm6+lJfcLkOp4jrxwQ== X-Received: by 2002:a17:902:b283:: with SMTP id u3-v6mr15180962plr.2.1535722048669; Fri, 31 Aug 2018 06:27:28 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id l185-v6sm19081936pga.5.2018.08.31.06.27.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 31 Aug 2018 06:27:28 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 31 Aug 2018 21:26:44 +0800 Message-Id: <20180831132710.23055-3-ming.huang@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180831132710.23055-1-ming.huang@linaro.org> References: <20180831132710.23055-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 02/28] Silicon/Hisilicon/D0x: Move RAS macro to PlatformArch.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Sun Yuanchen , guoheyi@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Sun Yuanchen Move some RAS macros definition to PlatformArch.h for unifying D0x Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm --- Silicon/Hisilicon/Hi1610/Include/PlatformArch.h | 9 +++++++-- Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 12 ++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) -- 2.18.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h index 2ff076901e..f39ae0748c 100644 --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h @@ -1,7 +1,7 @@ /** @file * -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -32,6 +32,11 @@ #define S1_BASE 0x40000000000 +#define RASC_BASE (0x5000) +/* configuration register for Rank statistical information */ +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) +/* configuration register for Sparing level */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) // // ACPI table information used to initialize tables. diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h index 60a60593be..e02e4bdabd 100644 --- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h @@ -30,6 +30,18 @@ // Max NUMA node number for each node type #define MAX_NUM_PER_TYPE 8 +#define RASC_BASE (0x5000) +/* configuration register for Rank statistical information */ +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) +/* configuration register for Sparing level */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) + +// for acpi +#define NODE_IN_SOCKET 2 +#define CORE_NUM_PER_SOCKET 32 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10 +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8 + #define S1_BASE 0x40000000000 //