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[198.145.21.10]) by mx.google.com with ESMTPS id 20-v6si27229804pfr.242.2018.08.16.05.14.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Aug 2018 05:14:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Vjfjr34b; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5AD15210F3761; Thu, 16 Aug 2018 05:14:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::434; helo=mail-pf1-x434.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 94F16210F374A for ; Thu, 16 Aug 2018 05:14:26 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id l9-v6so1942481pff.9 for ; Thu, 16 Aug 2018 05:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lOZbm7l0dbSRHIC+bQh1JiJSC9IGDa6W7Gu1NSOk0zM=; b=Vjfjr34bn4KzZ7RMrlG8jRSK1QoxiFHrUEMY9nouyFmkJ0qwWZYayUWIl80nN8iK7R vAQd25d66WkYFOrtEtm00wa292sX0Oquez3kod8kgFisWA5s7PkjAOlf+BSRxJKlrQMm 35UX4J1PrqwFsGW9tFkxGqsqHauxT8AFJTgOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lOZbm7l0dbSRHIC+bQh1JiJSC9IGDa6W7Gu1NSOk0zM=; b=E2W0iQpLbFt6lGiW8qKn8LIazEXuFEaLoPp0wh5ctYA99T4Td+4Ra59Pp0elmV1yIH CbtCoe4PiXYwXUhovy3XZy8LM3mqlPqqRMDYO4cW36FNJifuHdm67XYgGYJg5Z2uTftD i7xYLs7eJ6JqToo6UV2U8/7P0vQHv7jxkdRrpMvurrxOx6/dHXaIe11NH6Kha1cu/NTd 42x/7JUrUVuCMnPqRWLJpmrsmAloyL/zy/y0MlYDewqZaujWoAGzSpKAbQzGwHtNi5d7 vOdcPedWFn4wh0lXqe8MLuyGrV5sLxFfTfmDMFlQ0Nd9R1JzBfkZcKOvvO49Bf3NnM/o DVpg== X-Gm-Message-State: AOUpUlG1K8gMPmHJrKdjXsBhl7MJ4xLOZMHKDKyhDI+1L3hdnPn/B0pW FMFGak+guy+4dIbpnk45d0sARg== X-Received: by 2002:a63:947:: with SMTP id 68-v6mr29102067pgj.131.1534421666164; Thu, 16 Aug 2018 05:14:26 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id j27-v6sm46736311pfj.91.2018.08.16.05.14.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 05:14:25 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Thu, 16 Aug 2018 20:12:27 +0800 Message-Id: <20180816121239.44129-25-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180816121239.44129-1-ming.huang@linaro.org> References: <20180816121239.44129-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 24/36] Hisilicon/D0x: Update SMBIOS type9 info X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Sun Yuanchen , guoheyi@huawei.com, huangdaode@hisilicon.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Sun Yuanchen Move board level code to OemMiscLibD0x for unifying D0x. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sun Yuanchen --- Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 + Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 4 + Platform/Hisilicon/D06/Include/Library/CpldD06.h | 2 + Silicon/Hisilicon/Include/Library/OemMiscLib.h | 1 + Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 24 ++++++ Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +++++- Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 90 ++++++++++++++++++++ Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +-- 9 files changed, 151 insertions(+), 13 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf index 310bbaea84..0fa7fdf80f 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf @@ -34,6 +34,7 @@ Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] + BaseMemoryLib PcdLib TimerLib diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf index bf44ff7440..022c3e940a 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -33,6 +33,7 @@ Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] + BaseMemoryLib PcdLib TimerLib diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf index 8f68f7cec5..bd984a6fe3 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf @@ -30,9 +30,13 @@ ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Platform/Hisilicon/D06/D06.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] + BaseMemoryLib + CpldIoLib + IoLib PcdLib SerdesLib TimerLib diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h index be3548c8d1..ec9b49f4e7 100644 --- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h +++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h @@ -29,6 +29,8 @@ #define CPLD_LOGIC_COMPILE_DAY (0x3) #define CPLD_RISER_PRSNT_FLAG 0x40 +#define CPU1_RISER_PRESENT BIT6 +#define CPU0_RISER_PRESENT BIT7 #define CPLD_RISER2_BOARD_ID 0x44 #define CPLD_X8_X8_X8_BOARD_ID 0x92 diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index efecb9aa77..86ea6a1b3d 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -34,6 +34,7 @@ typedef struct _REPORT_PCIEDIDVID2BMC{ UINTN Slot; }REPORT_PCIEDIDVID2BMC; extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX]; +extern VOID GetPciDidVid (REPORT_PCIEDIDVID2BMC *Report); BOOLEAN OemIsSocketPresent (UINTN Socket); VOID CoreSelectBoot(VOID); diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index fa1039bda1..c80500276f 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -15,6 +15,7 @@ #include +#include #include #include #include @@ -31,6 +32,29 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { {0xFFFF,0xFFFF,0xFFFF,0xFFFF} }; +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = { + {0x79,0,0,0}, + {0xFF,0xFF,0xFF,1}, + {0xC1,0,0,2}, + {0xF9,0,0,3}, + {0xFF,0xFF,0xFF,4}, + {0x11,0,0,5}, + {0x31,0,0,6}, + {0x21,0,0,7} +}; + +VOID +GetPciDidVid ( + REPORT_PCIEDIDVID2BMC *Report + ) +{ + if (OemIsMpBoot ()) { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P)); + } else { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport)); + } +} + // Right now we only support 1P BOOLEAN OemIsSocketPresent (UINTN Socket) { diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c index b17eeada16..4c4c944dbe 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -1,7 +1,7 @@ /** @file * -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -37,6 +38,28 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { {0xFFFF,0xFFFF,0xFFFF,0xFFFF} }; +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = { + {0x79,0,0,0}, + {0xFF,0xFF,0xFF,1}, + {0xC1,0,0,2}, + {0xF9,0,0,3}, + {0xFF,0xFF,0xFF,4}, + {0x11,0,0,5}, + {0x31,0,0,6}, + {0x21,0,0,7} +}; + +VOID +GetPciDidVid ( + REPORT_PCIEDIDVID2BMC *Report + ) +{ + if (OemIsMpBoot ()) { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P)); + } else { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport)); + } +} BOOLEAN OemIsSocketPresent (UINTN Socket) { diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 95521752ff..2a9db46d1f 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include #include @@ -33,6 +35,94 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { {0xFFFF,0xFFFF,0xFFFF,0xFFFF} }; +//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8) +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = { + {0x01,0,0,0}, + {0x03,0,0,1}, + {0xFF,0xFF,0xFF,2}, + {0x81,0,0,3}, + {0x84,0,0,4}, + {0xFF,0xFF,0xFF,5} +}; + +//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8) +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = { + {0x01,0,0,0}, + {0x03,0,0,1}, + {0xFF,0xFF,0xFF,2}, + {0xFF,0xFF,0xFF,3}, + {0x81,0,0,4}, + {0x85,0,0,5} +}; + +//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8) +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = { + {0xFF,0xFF,0xFF,0}, + {0x01,0,0,1}, + {0x04,0,0,2}, + {0x81,0,0,3}, + {0x84,0,0,4}, + {0xFF,0xFF,0xFF,5} +}; + +//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8) +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = { + {0xFF,0xFF,0xFF,0}, + {0x01,0,0,1}, + {0x04,0,0,2}, + {0xFF,0xFF,0xFF,3}, + {0x81,0,0,4}, + {0x85,0,0,5} +}; + +VOID +GetPciDidVid ( + REPORT_PCIEDIDVID2BMC *Report + ) +{ + UINT32 PresentStatus; + UINT32 CardType; + UINT8 Cpu0CardType = 0; + UINT8 Cpu1CardType = 0; + + PresentStatus = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG); + CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID); + + // Offset 0x40: Bit7 = 1 CPU0 Riser present + if ((PresentStatus & CPU0_RISER_PRESENT) != 0) { + Cpu0CardType = (UINT8) (PresentStatus >> 8); + } + + // Offset 0x40: Bit6 = 1 CPU1 Riser present + if ((PresentStatus & CPU1_RISER_PRESENT) != 0) { + Cpu1CardType = (UINT8)CardType; + } + + if (OemIsMpBoot ()) { + if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) { + if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type1, + sizeof (PcieDeviceToReport_2P_Type1)); + } else { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type2, + sizeof (PcieDeviceToReport_2P_Type2)); + } + } else { + if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type3, + sizeof (PcieDeviceToReport_2P_Type3)); + } else { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type4, + sizeof (PcieDeviceToReport_2P_Type4)); + } + } + } else { + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, + sizeof (PcieDeviceToReport)); + } +} + + // Right now we only support 1P BOOLEAN OemIsSocketPresent ( diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c index 8d8dacd3e0..cc1131577d 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c +++ b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c @@ -18,12 +18,6 @@ extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[]; extern UINT8 OemGetPcieSlotNumber (); -REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = { - {67,0,0,0}, - {225,0,0,3}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, - {0xFFFF,0xFFFF,0xFFFF,0xFFFF} -}; VOID EFIAPI UpdateSmbiosType9Info( @@ -41,11 +35,9 @@ UpdateSmbiosType9Info( UINTN FunctionNumber; UINTN Index; REPORT_PCIEDIDVID2BMC ReportPcieDidVid[PCIEDEVICE_REPORT_MAX]; - if(OemIsMpBoot()){ - (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport_2P,sizeof(PcieDeviceToReport_2P)); - } else { - (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport,sizeof(PcieDeviceToReport)); - } + + GetPciDidVid ((VOID *) ReportPcieDidVid); + Status = gBS->LocateHandleBuffer ( ByProtocol, &gEfiPciIoProtocolGuid,