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[198.145.21.10]) by mx.google.com with ESMTPS id t189-v6si11354539pgb.440.2018.07.24.00.24.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jul 2018 00:24:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QrEPFItM; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 19215210C1B68; Tue, 24 Jul 2018 00:24:58 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D622A210C1B62 for ; Tue, 24 Jul 2018 00:24:56 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id p23-v6so2229854pgv.13 for ; Tue, 24 Jul 2018 00:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vLzkSkncc1Xl4d6tztV1fwWlHEhojUptY46hzWYTSQo=; b=QrEPFItMWjEHrbiwaJl7GL4XVmC59u2LMi8mVufMrevZPrDDOIog4lc308cgjk/L62 Fz0itlzinbukUG67mkwg3pzWybajn1jRP1lq+Zlq7jzgLlq9BySDJqOv4LbhBpDrC8qy vA9ZfAO/kzBcrp+bKn+i+EFNj+DB11lCcyBNk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vLzkSkncc1Xl4d6tztV1fwWlHEhojUptY46hzWYTSQo=; b=gb5Y/Imt9V2eqL/r1Dj+BWBwAxR3RO8/a2p7tGBD5QT3u2AuZndKqKKXjrDMMUafv7 DhmfqMgPikVXXol8V6c5G5Z2BHt44+lnxrkWwx63H/YEtypv7ZK0qgqxkqCWkfhHe//y GXy2nwWlTFxC+TByARFbA0T81FzwH6AHAmy6vfS0pTjBl31LqGgyn1t02cBZPgx+AgsV sCZKlTVUmUW35P7jZubGkGe+iZLELBIAEz1uhQihkz7yPd2vCXpB8oyeIKDXeXEEbsVo mFYET+stIqCMIU/FQzuGQ5psIaigRrR7O4B3gpeiqqjyFqIybwuUEoNWVz3dBYC+HvNj Ao2g== X-Gm-Message-State: AOUpUlHJP22d78VG95RvRfsP7P0NgQFyQizzIYpHxrIs2DoH+q+t4wyC j64K9ZBaZ8xZ4u8NF3elnrI77NbfE9c= X-Received: by 2002:a63:f449:: with SMTP id p9-v6mr15586821pgk.213.1532417096562; Tue, 24 Jul 2018 00:24:56 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id t14-v6sm11449788pgu.0.2018.07.24.00.24.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 00:24:56 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 15:09:20 +0800 Message-Id: <20180724070922.63362-37-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724070922.63362-1-ming.huang@linaro.org> References: <20180724070922.63362-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 36/38] Silicon/Hisilicon/setup: Support SMMU switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Select without SMMU iort while SMMU item is disable, Select with SMMU iort while SMMU item is enable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 81 ++++++++++++++++++++ 1 file changed, 81 insertions(+) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c index 32878ca4f9..4f0998dd24 100644 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c +++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -24,6 +24,83 @@ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET) +#define FIELD_IORT_NODE_OFFSET 40 + +typedef enum { + NodeTypeIts = 0, + NodeTypeNameComponent, + NodeTypePciRC, + NodeTypeSmmuV1, + NodeTypeSmmuV3, + NodeTypePMCG +} IORT_NODE_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 IdMapNumber; + UINT32 IdArrayOffset; +} IORT_NODE_HEAD; +#pragma pack() + +BOOLEAN +IsIortWithSmmu ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + UINT32 *NodeOffset; + UINT32 NextOffset; + IORT_NODE_HEAD *Node; + + NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET); + NextOffset = *NodeOffset; + + while (NextOffset < TableHeader->Length) { + Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset); + NextOffset += Node->Length; + + if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) { + return TRUE; + } + } + + return FALSE; +} + +EFI_STATUS +SelectIort ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + EFI_STATUS Status; + UINTN Size; + OEM_CONFIG_DATA Configuration; + + Configuration.EnableSmmu = 0; + Size = sizeof (OEM_CONFIG_DATA); + Status = gRT->GetVariable (OEM_CONFIG_NAME, &gOemConfigGuid, NULL, &Size, &Configuration); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Get OemConfig variable (%r).\n", Status)); + } + + Status = EFI_SUCCESS; + if (IsIortWithSmmu (TableHeader)) { + if (!Configuration.EnableSmmu) { + Status = EFI_ABORTED; + } + } else { + if (Configuration.EnableSmmu) { + Status = EFI_ABORTED; + } + } + DEBUG ((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n", Configuration.EnableSmmu, Status)); + + return Status; +} + STATIC VOID RemoveUnusedMemoryNode ( @@ -151,6 +228,10 @@ UpdateAcpiTable ( case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: Status = UpdateSlit (TableHeader); break; + + case EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE: + Status = SelectIort (TableHeader); + break; case EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE: Status = IsNeedSpcr (TableHeader); break;