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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id f5-v6si10530579pga.340.2018.07.23.23.33.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jul 2018 23:33:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="b/WDv5Us"; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 12283210C1251; Mon, 23 Jul 2018 23:33:13 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4609A210C124E for ; Mon, 23 Jul 2018 23:33:12 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id e6-v6so2141100pgv.2 for ; Mon, 23 Jul 2018 23:33:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q0hVsUcHpeXMJzUMhklRB48L9QJ5WPgpKEvC/702QZI=; b=b/WDv5Uszsxf7geAkgyXbxc9L5vZTcgme/3SQ8njlwW6/rzUFAsNfSFSy4hDdOlcJK wu79814tPDOAxgyooPflcEbb6ZeI/eiHf4lKfGVwZacnffHo2NpDuAgVkbEhVVAibdQy 3kQvZ9xcQ08SL2AYzpWIT8zlvNxiigRLdmqOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q0hVsUcHpeXMJzUMhklRB48L9QJ5WPgpKEvC/702QZI=; b=H/74AI8bMmNsSKXNnwq9Q+L/TSZEHasAD35WKr5JrXL6GTJJBqk4yJ6G5tLwqh4S1o bixwlJM7jgrAUX8m/IZODXgDvl05MHkY6F9j51kHXwOMhB6yrKtxRGy2OR4AfyuVhha6 aXzGJtESHcGVJBkKuQHXTRMim4IPtVFSdi0k5lb+e0ZOo87SjnNCwM26OeNus3SKZkIH NgFHWIFHzF1Yox1TUlCtmtEeIAt3+/hril5Yu6DPewC1Ko9HpIta0SQLP1lPIk45bAfq E5UFgLHL5jWjPfnYl7i8Zl1knTpEGEf6r+82hFmQVO2oseCDBV5x5qnaJsm3BYA7AI55 d47Q== X-Gm-Message-State: AOUpUlGmKVzcTrkERtibvm7C864Z6GY+Qbpi+5E21pcNqfVcDQhCCcV+ HE9IJgkqjrY2MZa9GQeVp5psfw== X-Received: by 2002:a63:788b:: with SMTP id t133-v6mr15009557pgc.329.1532413991948; Mon, 23 Jul 2018 23:33:11 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e2-v6sm12086575pgo.92.2018.07.23.23.33.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 23:33:11 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 14:32:20 +0800 Message-Id: <20180724063220.61679-13-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org> References: <20180724063220.61679-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 12/12] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , Yi Li , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Heyi Guo In structure PCI_ROOT_BRIDGE_RESOURCE_APPETURE, MemBase is redundant with CpuMemRegionBase, and MemLimit can be calculated by CpuMemRegionBase + PciRegionLimit - PciRegionBase so it is also redundant. Remove these two fields to make things simple and clear. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 16 ---------- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 32 -------------------- Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 2 -- 3 files changed, 50 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index 3a770d17bb..59c468ac4b 100644 --- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -32,8 +32,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB0_ECAM_BASE, //ecam 0, //BusBase 31, //BusLimit - PCI_HB0RB0_PCIREGION_BASE, //Membase - PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit PCI_HB0RB0_IO_BASE, //IoBase (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -49,8 +47,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_ECAM_BASE,//ecam 224, //BusBase 254, //BusLimit - PCI_HB0RB1_PCIREGION_BASE, //Membase - PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB1_IO_BASE), //IoBase (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -65,8 +61,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_ECAM_BASE, 128, //BusBase 159, //BusLimit - PCI_HB0RB2_PCIREGION_BASE ,//MemBase - PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -82,8 +76,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB3_ECAM_BASE, 96, //BusBase 127, //BusLimit - (PCI_HB0RB3_ECAM_BASE), //MemBase - (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit (0), //IoBase (0), //IoLimit 0, @@ -100,8 +92,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB0_ECAM_BASE, 128, //BusBase 159, //BusLimit - (PCI_HB1RB0_ECAM_BASE), //MemBase - (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit (0), //IoBase (0), //IoLimit 0, @@ -116,8 +106,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB1_ECAM_BASE, 160, //BusBase 191, //BusLimit - (PCI_HB1RB1_ECAM_BASE), //MemBase - (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit (0), //IoBase (0), //IoLimit 0, @@ -132,8 +120,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB2_ECAM_BASE, 192, //BusBase 223, //BusLimit - (PCI_HB1RB2_ECAM_BASE), //MemBase - (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit (0), //IoBase (0), //IoLimit 0, @@ -149,8 +135,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB3_ECAM_BASE, 224, //BusBase 255, //BusLimit - (PCI_HB1RB3_ECAM_BASE), //MemBase - (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit (0), //IoBase (0), //IoLimit 0, diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 42bbdd8c98..0dc988a1d3 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -33,8 +33,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB0_ECAM_BASE, //ecam 0x80, //BusBase 0x87, //BusLimit - PCI_HB0RB0_PCIREGION_BASE, //Membase - PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit PCI_HB0RB0_IO_BASE, //IoBase (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -49,8 +47,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_ECAM_BASE,//ecam 0x90, //BusBase 0x97, //BusLimit - PCI_HB0RB1_PCIREGION_BASE, //Membase - PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB1_IO_BASE), //IoBase (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -65,8 +61,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_ECAM_BASE, 0xF8, //BusBase 0xFF, //BusLimit - PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase - PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -82,8 +76,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB3_ECAM_BASE, 0xb0, //BusBase 0xb7, //BusLimit - (PCI_HB0RB3_ECAM_BASE), //MemBase - (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit (PCI_HB0RB3_IO_BASE), //IoBase (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit PCI_HB0RB3_CPUMEMREGIONBASE, @@ -98,8 +90,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB4_ECAM_BASE, //ecam 0x88, //BusBase 0x8f, //BusLimit - PCI_HB0RB4_CPUMEMREGIONBASE, //Membase - PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit PCI_HB0RB4_IO_BASE, //IoBase (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -114,8 +104,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB5_ECAM_BASE,//ecam 0x78, //BusBase 0x7F, //BusLimit - PCI_HB0RB5_CPUMEMREGIONBASE, //Membase - PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -130,8 +118,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB6_ECAM_BASE, 0xC0, //BusBase 0xC7, //BusLimit - PCI_HB0RB6_PCIREGION_BASE ,//MemBase - PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB6_IO_BASE), //IOBase (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -147,8 +133,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB7_ECAM_BASE, 0x90, //BusBase 0x97, //BusLimit - PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase - PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB7_IO_BASE), //IoBase (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit PCI_HB0RB7_CPUMEMREGIONBASE, @@ -165,8 +149,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB0_ECAM_BASE, 0x80, //BusBase 0x87, //BusLimit - (PCI_HB1RB0_ECAM_BASE), //MemBase - (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB0_IO_BASE, //IoBase (PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -181,8 +163,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB1_ECAM_BASE, 0x90, //BusBase 0x97, //BusLimit - (PCI_HB1RB1_ECAM_BASE), //MemBase - (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB1_IO_BASE, //IoBase (PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -197,8 +177,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB2_ECAM_BASE, 0x10, //BusBase 0x1f, //BusLimit - PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase - PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB2_IO_BASE, //IoBase (PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -214,8 +192,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB3_ECAM_BASE, 0xb0, //BusBase 0xb7, //BusLimit - (PCI_HB1RB3_ECAM_BASE), //MemBase - (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB3_IO_BASE, //IoBase (PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -230,8 +206,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB4_ECAM_BASE, 0x20, //BusBase 0x2f, //BusLimit - PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase - PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB4_IO_BASE, //IoBase (PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -246,8 +220,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB5_ECAM_BASE, 0x30, //BusBase 0x3f, //BusLimit - PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase - PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB5_IO_BASE, //IoBase (PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -262,8 +234,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB6_ECAM_BASE, 0xa8, //BusBase 0xaf, //BusLimit - (PCI_HB1RB6_ECAM_BASE), //MemBase - PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB6_IO_BASE, //IoBase (PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase @@ -279,8 +249,6 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB7_ECAM_BASE, 0xb8, //BusBase 0xbf, //BusLimit - (PCI_HB1RB7_ECAM_BASE), //MemBase - PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB7_IO_BASE, //IoBase (PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h index 6725a547d5..5fdc3d3e0a 100644 --- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h @@ -194,8 +194,6 @@ typedef struct { UINT64 Ecam; UINT64 BusBase; UINT64 BusLimit; - UINT64 MemBase; - UINT64 MemLimit; UINT64 IoBase; UINT64 IoLimit; UINT64 CpuMemRegionBase;